CN115940941A - Frequency source for data link frequency hopping communication and rapid locking method thereof - Google Patents
Frequency source for data link frequency hopping communication and rapid locking method thereof Download PDFInfo
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Abstract
The invention provides a frequency source of data link frequency hopping communication and a rapid locking method thereof, wherein the frequency source comprises a clock circuit, a power divider, a phase-locked loop circuit, an amplification filter circuit, an FPGA circuit and an EEPROM memory, wherein the clock circuit is connected to the com end of the power divider, and the power divider divides a clock signal into two paths; the sck end, the sda end, the sen end and the ld end of the phase-locked loop circuit are connected with the high-speed SPI interface of the FPGA circuit, and the radio frequency output port Rfout is connected with the input port in end of the amplifying and filtering circuit; the sck end and the sda end of the EEPROM and the I of the FPGA circuit 2 And C, bus interface connection. The invention adopts domestic hardware, has high degree of autonomy, is safe and reliable, and solves the problem of long locking time of the frequency source of data link frequency hopping communication.
Description
Technical Field
The invention relates to the field of data link frequency hopping communication, in particular to a frequency source of data link frequency hopping communication and a quick locking method thereof.
Background
Frequency hopping communications, which is a method of spreading a spectrum by constantly hopping a carrier frequency using a pseudo random code sequence for frequency shift keying, is an important application in civil communications. In a frequency hopping communication system, a frequency source provides local oscillation signals for a receiving and transmitting channel to generate carrier frequencies, and the frequency source is a core part of the system. The phase-locked loop frequency synthesizer has the advantages of wide frequency range, good spurious suppression, low phase noise and the like and is widely applied as a frequency source. The locking time of the phase-locked loop frequency synthesizer is a key index of a frequency hopping communication system, and directly determines the frequency hopping rate so as to determine the anti-interference capability of the system.
In the face of a complex electromagnetic environment, the frequency hopping rate of modern data link frequency hopping communication is higher and higher, which requires that a frequency source can be locked more quickly. The time of an automatic VCO (voltage controlled oscillator) calibration mode of a phase-locked loop chip used by the current frequency source is very slow, so that the locking time is very long, and the requirement of high hopping speed of modern data link frequency hopping communication cannot be met.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a frequency source for data link frequency hopping communication and a fast locking method thereof, so as to solve the problem of long locking time of the frequency source for data link frequency hopping communication.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
the invention provides a frequency source of data link frequency hopping communication, which comprises a clock circuit, a power divider, a phase-locked loop circuit, an amplification filter circuit, an FPGA circuit and an EEPROM memory, wherein the clock circuit is connected to the com end of the power divider, the power divider divides a clock signal into two paths, one path of out1 end is connected to the Ref end of the phase-locked loop circuit to provide reference frequency for the phase-locked loop circuit, and the other path of out2 end is connected to a high-speed SPI interface of the FPGA circuit to provide the clock signal for the FPGA circuit; the sck end, the sda end, the sen end and the ld end of the phase-locked loop circuit are connected with the high-speed SPI interface of the FPGA circuit, and the radio frequency output port Rfout is connected with the input port in end of the amplifying and filtering circuit; sck terminal and sda terminal of EEPROM memory and I of FPGA circuit 2 And C, bus interface connection.
Preferably, the amplifying and filtering circuit is composed of a radio frequency amplifier and a low-pass filter.
Preferably, the clock circuit is a50 MHz constant temperature crystal oscillator.
Preferably, the fractional-N frequency division phase-locked loop chip XND833MQM of the integrated VC0 is selected for the phase-locked loop circuit.
Preferably, the EEPROM memory is an FM24C512DSO memory chip.
Preferably, the FPGA circuit is a JFM7K325T chip.
The invention provides a method for quickly locking a frequency source of data link frequency hopping communication, which comprises the following steps:
step S101, performing initial register configuration on a phase-locked loop, and configuring the phase-locked loop into an automatic VCO (voltage controlled oscillator) calibration mode;
step S102, establishing a mapping table of corresponding local oscillator output frequency and VCO segment code;
step S103, performing initial register configuration on a phase-locked loop, and configuring the phase-locked loop into a manual VCO (voltage controlled oscillator) calibration mode;
and step S104, when the FPGA circuit configures frequency information, extracting a VCO section code value corresponding to the frequency from the EEPROM memory, writing the VCO section code value into a register reg05h of the VCO, and finding out the VCO section.
Preferably, in step S101, the FPGA configures an initialization register for the phase-locked loop, and configures the phase-locked loop in the automatic VCO calibration mode by setting Reg0A <11> to 0.
Preferably, the step S102 includes: 1MHz stepping sweep frequency is carried out on the required local oscillator output frequency, a state bit at an id end of locking detection is read, if the id end is 1, the VCO is indicated to be locked, a reg10h register is used for reading a VCO segment code of automatic phase locking, namely reg10h <8 > is the segment code value of the VCO and is stored in an EEPROM memory, and a mapping table of the corresponding local oscillator output frequency and the VCO segment code is established.
Preferably, the step S104 includes: the FPGA circuit passes through I when configuring local oscillator frequency information 2 And the C bus interface extracts the VCO segment code value corresponding to the frequency from the EEPROM memory, writes the VCO segment code value into a register reg05h of the VCO and finds the sub-segments of the VCO.
The invention has the beneficial effects that:
according to the invention, through the manual VCO calibration mode of the phase-locked loop, the VCO segment code value corresponding to the local oscillator output frequency in the EEPROM memory is written into the register reg05h of the VCO, the subsegment of the VCO is quickly found, the time for the automatic calibration of the VCO is saved, and the locking time of the phase-locked loop is greatly reduced. The locking time can be less than 50us through actual test, and the requirement of high hopping speed of modern data link frequency hopping communication is met.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic block diagram of a frequency source for data chain frequency hopping communications according to the present invention.
Fig. 2 is a flowchart of a method for fast locking a frequency source for data link frequency hopping communication according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive effort based on the embodiments of the present invention, are within the scope of the present invention.
As shown in fig. 1, the present invention includes a clock circuit 1, a power divider 2, a phase-locked loop circuit 3, an amplifying and filtering circuit 4, an FPGA circuit 6 and an EEPROM memory 5, where the clock circuit 1 is connected to the com end of the power divider 2, the power divider 2 divides a clock signal into two paths, one of the paths out1 is connected to the Ref end of the phase-locked loop circuit 3 to provide a reference frequency for the phase-locked loop circuit, and the other path out2 is connected to the high-speed SPI interface of the FPGA circuit 6 to provide a clock signal for the FPGA circuit. The sck end, the sda end, the sen end and the ld end of the phase-locked loop circuit 3 are connected with the high-speed SPI interface of the FPGA circuit 6, and the radio frequency output port Rfout is connected with the input port of the amplifying filter circuit 4And the in end is connected. Sck terminal and sda terminal of EEPROM (electrically erasable programmable read-Only memory) 5 and I of FPGA (field programmable Gate array) circuit 6 2 And C, bus interface connection.
In this embodiment, the clock circuit is a50 MHz constant temperature crystal oscillator for Guangzhou Dapu communication; the power divider selects 2-10L of BSBTC of Hongda; the phase-locked loop circuit selects a phase-locked loop chip XND833MQM integrated in Chongqing southwest; the amplifying and filtering circuit selects a radio frequency amplifier XA506 of Beijing Xinyueda and a low pass filter BLF1700-3216 of Hada of Ottelia; the EEPROM memory adopts a double denier micro FM24C512DSO; the FPGA circuit adopts a double-denier micro FPGA chip JFM7K325T.
The clock circuit selects a50 MHz constant-temperature crystal oscillator to output a50 MHz clock signal, and is connected to the com end of the power divider, the power divider divides the 50MHz clock signal into two paths, one path of out1 end is connected to the Ref end of the phase-locked loop circuit to provide reference frequency for the phase-locked loop, and the other path of out2 end is connected to the high-speed SPI interface of the FPGA circuit to provide the clock signal for the FPGA.
The phase-locked loop circuit selects a decimal N frequency division phase-locked loop chip XND833MQM integrated with VC 0. Configuration ports sck, sda, sen and ld of the chip are connected with a high-speed SPI interface of the FPGA circuit, and a radio frequency output port Rfout is connected with an input port in of the amplifying and filtering circuit. And configuring an internal register through the FPGA to generate local oscillation frequency output.
The amplifying and filtering circuit consists of a radio frequency amplifier and a low-pass filter, and the radio frequency amplifier has two functions: firstly, amplifying a radio frequency signal input by a phase-locked loop to a power required by a local oscillator; and secondly, the radio frequency amplifier has higher reverse isolation, the frequency traction of the output load change to the VCO can be reduced, and the low-pass filter can effectively filter harmonic interference.
The EEPROM memory selects FM24C512DSO memory chip, sck and sda ports of the chip and I of FPGA 2 And C, bus interface connection, the FPGA stores the read VCO segment code value into the EEPROM during initialization, and the segment code value corresponding to the local oscillation frequency is extracted from the EEPROM during manual VCO calibration. The FPGA circuit is mainly used for configuring frequency information for the phase-locked loop and reading a section code value of the VCO.
As shown in fig. 2, the present embodiment provides a method for quickly locking a frequency source for data link frequency hopping communication, including the following steps:
step S101, performing initial register configuration on a phase-locked loop, and configuring the phase-locked loop into an automatic VCO (voltage controlled oscillator) calibration mode;
step S102, establishing a mapping table of corresponding local oscillator output frequency and VCO segment code;
step S103, performing initial register configuration on a phase-locked loop, and configuring the phase-locked loop into a manual VCO (voltage controlled oscillator) calibration mode;
and step S104, when the FPGA circuit configures frequency information, extracting a VCO section code value corresponding to the frequency from the EEPROM memory, writing the VCO section code value into a register reg05h of the VCO, and finding out the VCO section.
In one embodiment, in step S101, the FPGA performs initial register configuration on the pll, and configures the pll in the automatic VCO calibration mode by setting Reg0A <11> to 0.
In one embodiment, the step S102 includes: 1MHz stepping sweep frequency is carried out on the required local oscillator output frequency, a state bit at an id end of locking detection is read, if the id end is 1, the VCO is indicated to be locked, a reg10h register is used for reading a VCO segment code of automatic phase locking, namely reg10h <8 > is the segment code value of the VCO and is stored in an EEPROM memory, and a mapping table of the corresponding local oscillator output frequency and the VCO segment code is established.
In one embodiment, the step S104 includes: the FPGA circuit passes through I when configuring local oscillator frequency information 2 And the bus interface C is used for extracting the VCO segment code value corresponding to the frequency from the EEPROM memory, writing the VCO segment code value into a register reg05h of the VCO and finding out the subsegment of the VCO.
Firstly, the configuration information is loaded to the FPGA by software, the FPGA carries out initialization register configuration on a phase-locked loop, and Reg0A is used<11>Setting 0 to configure the phase-locked loop as an automatic VCO (voltage controlled oscillator) calibration mode, performing 1MHz stepping frequency sweep on the required local oscillator output frequency, reading the status bit of locking detection ld, if the ld is 1, indicating that the VCO is locked, and reading the VCO segment code (reg 10 h) of the automatic phase lock through a reg10h register<8:1>Is the segment code value of the VCO) is stored in the EEPROM memory. And establishing a mapping table of the corresponding local oscillator output frequency and the VCO segment code. Secondly, the initialization register is performed againDevice configuration by Reg0A<11>The device 1 configures a phase-locked loop into a manual VCO (voltage controlled oscillator) calibration mode, and an FPGA (field programmable gate array) passes through I when configuring local oscillator frequency information 2 And the bus interface C is used for extracting the VCO segment code value corresponding to the frequency from the EEPROM memory and writing the VCO segment code value into a register reg05h of the VCO to quickly find out the sub-segments of the VCO, so that the time for automatically calibrating the VCO is saved, and the locking time of the phase-locked loop is greatly reduced.
The specific embodiments are given above, but the present invention is not limited to the described embodiments. The basic idea of the present invention lies in the above basic scheme, and it is obvious to those skilled in the art that no creative effort is needed to design various modified models, formulas and parameters according to the teaching of the present invention. Variations, modifications, substitutions and alterations may be made to the embodiments without departing from the principles and spirit of the invention, and still fall within the scope of the invention.
Claims (10)
1. A frequency source for data chain frequency hopping communications, comprising: the power divider divides a clock signal into two paths, wherein one path of out1 end is connected to a Ref end of the phase-locked loop circuit to provide reference frequency for the phase-locked loop circuit, and the other path of out2 end is connected to a high-speed SPI interface of the FPGA circuit to provide the clock signal for the FPGA circuit; the sck end, the sda end, the sen end and the ld end of the phase-locked loop circuit are connected with the high-speed SPI interface of the FPGA circuit, and the radio frequency output port Rfout is connected with the input port in end of the amplifying and filtering circuit; sck terminal and sda terminal of EEPROM memory and I of FPGA circuit 2 And C, bus interface connection.
2. The frequency source of claim 1, wherein: the amplifying and filtering circuit consists of a radio frequency amplifier and a low-pass filter.
3. A frequency source for data chain frequency hopping communications according to claim 1, wherein: the clock circuit adopts a50 MHz constant temperature crystal oscillator.
4. The frequency source of claim 1, wherein: the phase-locked loop circuit selects a decimal N frequency division phase-locked loop chip XND833MQM integrated with VC 0.
5. The frequency source of claim 1, wherein: the EEPROM memory is an FM24C512DSO memory chip.
6. The frequency source of claim 1, wherein: the FPGA circuit adopts a JFM7K325T chip.
7. The method of claim 1, wherein the method comprises: the method comprises the following steps:
step S101, performing initial register configuration on a phase-locked loop, and configuring the phase-locked loop into an automatic VCO (voltage controlled oscillator) calibration mode;
step S102, establishing a mapping table of corresponding local oscillator output frequency and VCO segment code;
step S103, performing initial register configuration on a phase-locked loop, and configuring the phase-locked loop into a manual VCO (voltage controlled oscillator) calibration mode;
and step S104, when the FPGA circuit configures the frequency information, the FPGA circuit extracts the VCO segment code value corresponding to the frequency from the EEPROM memory, writes the VCO segment code value into a register reg05h of the VCO and finds out the VCO subsection.
8. The method of claim 7, wherein the method for rapidly locking a frequency source of data chain frequency hopping communication comprises: in step S101, the FPGA configures an initialization register for the phase-locked loop, and configures the phase-locked loop in an automatic VCO calibration mode by setting Reg0A <11> to 0.
9. The method of claim 8, wherein the method further comprises: the step S102 includes: the method comprises the steps of performing 1MHz stepping sweep frequency on required local oscillator output frequency, reading a state bit at an id end of locking detection, if the id end is 1, indicating that a VCO is locked, reading a VCO segment code of automatic phase locking through a reg10h register, namely reg10h <8 > is a segment code value of the VCO, storing the segment code value into an EEPROM memory, and establishing a mapping table of the corresponding local oscillator output frequency and the VCO segment code.
10. The method of claim 7, wherein the method further comprises: the step S104 includes: the FPGA circuit passes through I when configuring local oscillator frequency information 2 And the C bus interface extracts the VCO segment code value corresponding to the frequency from the EEPROM memory, writes the VCO segment code value into a register reg05h of the VCO and finds the sub-segments of the VCO.
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| CN114172511A (en) * | 2021-12-13 | 2022-03-11 | 四川九洲电器集团有限责任公司 | Frequency preset control method, device, medium and electronic equipment based on FPGA |
| CN114744999A (en) * | 2022-06-09 | 2022-07-12 | 中星联华科技（北京）有限公司 | Frequency hopping source implementation method and device, frequency hopping source, electronic equipment and storage medium |
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- 2023-03-09 CN CN202310222571.9A patent/CN115940941A/en active Pending
Patent Citations (6)
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| CN104202047A (en) * | 2014-08-22 | 2014-12-10 | 武汉中元通信股份有限公司 | Monolithic integration frequency synthesizer based on VHF (very high frequency) band |
| CN106067810A (en) * | 2016-07-21 | 2016-11-02 | 中兵通信科技股份有限公司 | A kind of control system of restructural frequency synthesizer platform |
| CN211791477U (en) * | 2020-09-10 | 2020-10-27 | 成都雷通科技有限公司 | PLL agile frequency source with agile function based on voltage presetting |
| CN213521883U (en) * | 2020-12-23 | 2021-06-22 | 四川中科微芯电子有限公司 | Channel system based on high-speed frequency synthesis chip |
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