CN103178782B - A kind of swept signal generator - Google Patents
A kind of swept signal generator Download PDFInfo
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- CN103178782B CN103178782B CN201110431637.2A CN201110431637A CN103178782B CN 103178782 B CN103178782 B CN 103178782B CN 201110431637 A CN201110431637 A CN 201110431637A CN 103178782 B CN103178782 B CN 103178782B
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Abstract
The present invention provides a kind of swept signal generator, this swept signal generator includes processor, memorizer, Subscriber Interface Module SIM, clock circuit, D/A converter module, analog module and fpga chip, this fpga chip includes: frequency sweep state machine, it is provided that different frequency sweep states；Skew multiplier, is connected with described frequency sweep profile memory, by calculating the incremental portion obtaining swept frequency word；Phase accumulator, for adding up the frequency word of carrier wave, and exports accumulation result；Frequency marker comparator, is used for producing frequency marker signal.A kind of swept-frequency signal generator that the embodiment of the present invention provides, uses FPGA to produce swept-frequency signal as core component, it is achieved scheme is the most reasonable, and software burden is little, response is fast, and the resource consuming FPGA is few；Meanwhile, some functions meeting market demand, frequency sweep mode more horn of plenty are increased.
Description
Technical field
The present invention relates to signal generator, particularly relate to a kind of swept signal generator.
Background technology
The frequency of swept signal generator output signal repeats consecutive variations the most according to certain rules, within the specific limits, in electronic surveying, is often used in the impedance operator to network and transmission characteristic measures.In tradition swept signal generator, the agitator being used for producing swept-frequency signal commonly uses discrete component realization.Such as: in LC agitator, use voltage variable capacitance diode, use thyrite to realize the control to frequency of oscillation in RC agitator, in magnetic modulation frequency sweep method, utilize inductance frequency sweep.All there is the shortcoming that control accuracy is low, frequency stability is poor in this kind of circuit.
Along with the development of microelectric technique, the application in frequency synthesis field of direct digital synthesis technique (DirectDigitalSynthesis, the DDS) technology is more and more extensive.DDS is a kind of frequency synthesis technique being directly synthesized required waveform from phase place concept.Signal generator based on DDS technology has relative bandwidth width, frequency switching time is short, frequency resolution is high, export Phase Continuation, can produce more modulation signal, control the plurality of advantages such as flexible.Some advantages of DDS technology are apparent from, and therefore it is a kind of highly desirable solution of current swept signal generator.
Having a kind of swept signal generator based on DDS technology in prior art, this swept signal generator uses programmable logic array (FPGA) as core component, uses DDS technology to produce swept-frequency signal.FPGA realizes principle as it is shown in figure 1, DDS is largely divided into two-way: a road produces swept-frequency signal medium frequency incremental portion；One tunnel produces swept-frequency signal medium frequency base unit weight part.
The generation process of swept-frequency signal medium frequency incremental portion: achieve a swept frequency word RAM and read address generator, actually one accumulator.Constantly add up with certain speed to produce and read the address depositing swept frequency word RAM.The parameter adjustment of necessity is carried out after reading.Carry out phase-accumulated afterwards；Value obtained by cumulative again with an other rood to data i.e. frequency swept signal base unit weight is added, obtain with the address being exactly reading and saving carrier wave wave table ROM.Initial frequency word is just just constantly added up by swept-frequency signal medium frequency base unit weight part.Two paths of data is added the address obtaining reading carrier wave wave table, reads final frequency sweep range value from the RAM preserving carrier wave wave table.
These range values through the conversion of digital to analog converter (DAC), just obtain the swept-frequency signal of analog quantity again.
The FPGA internal structure of above-mentioned swept-frequency signal generator is unreasonable, and the frequency sweep function realized also is weak:
First, before frequency sweep starts, each swept frequency word required during needing computed in software frequency sweep, then it be all written to deposit the RAM of swept frequency word.The most not only increase the burden of software, and can reduce system response time.
Secondly, two each and every one accumulators are employed respectively to frequency word base unit weight and increment accumulation.Accumulator not only consumes FPGA internal resource, and reduces the timing performance of FPGA.Particularly with the application of those parallel DDS structures used to improve the bandwidth of output swept-frequency signal, the fault of construction of this pair of accumulator can become apparent from.
Again, it is achieved swept-frequency signal excessively simple, be not enough to deal with practical measurement requirement.Termination frequency can only be scanned from initial frequency, not terminate the holding function of frequency, can not be from terminating frequency flyback to initial frequency.
Finally, as swept signal generator, lack frequency marker function at least.
Summary of the invention
The purpose of the embodiment of the present invention is to provide a kind of swept signal generator, to overcome all deficiencies of prior art.
For achieving the above object, the present invention provides a kind of swept signal generator, this swept signal generator includes processor, memorizer, Subscriber Interface Module SIM, clock circuit, D/A converter module, analog module and fpga chip, it is characterised in that this fpga chip includes:
Communication interface modules, is connected with described processor, for receiving the instruction of processor；
Clock module, is connected with described clock circuit, is used for providing work clock；
Frequency sweep state machine, is used for providing different frequency sweep states；
Frequency sweep time totalizer, is connected with described frequency sweep state machine, for the marking signal completed to described frequency sweep state machine feedback time, and produces the output of reading address；
Frequency sweep profile memory, is connected with described frequency sweep state machine, and for storing the frequency sweep curve that described frequency sweep state machine determines, and frequency sweep curve sampling point is read in the reading address produced according to described frequency sweep time totalizer；
Skew multiplier, is connected with described frequency sweep profile memory, by calculating the incremental portion obtaining swept frequency word；
Frequency word adder, is connected with described skew multiplier, for the increment of frequency word is added the frequency word obtaining carrier wave with frequency word fundamental quantity；
Phase accumulator, is connected with described frequency word adder, for adding up the frequency word of described carrier wave, and is exported by accumulation result；
Carrier wave memorizer, receives the output result of described phase accumulator as reading address, for storing the sampling point in one cycle of shape of carrier wave；
Frequency marker comparator, is used for producing frequency marker signal.
Described frequency sweep state machine provides four kinds of state swept-frequency signals, including:
Initial hold mode, with initial frequency output signal；
Scanning mode, the frequency of output signal changes to terminate frequency from initial frequency；
Terminate hold mode, to terminate frequency output signal；
Flyback state, the frequency of output signal changes to initial frequency from terminating frequency.
Described skew multiplier provides frequency sweep deviation ratio and frequency sweep curve sampling point product, thus obtains the incremental portion of swept frequency word.
Described frequency marker comparator obtain that described processor transmits by the mark frequency address threshold of user setup, and compared with the reading address of described frequency sweep time totalizer output, when the two is equal, produce a marking signal as frequency marker signal.
A kind of swept-frequency signal generator that the embodiment of the present invention provides, uses FPGA to produce swept-frequency signal as core component, it is achieved scheme is the most reasonable, and software burden is little, response is fast, and the resource consuming FPGA is few；Meanwhile, some functions meeting market demand, frequency sweep mode more horn of plenty are increased.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, is not intended that limitation of the invention.In the accompanying drawings:
Fig. 1 is prior art one FPGA internal structure block diagram；
Fig. 2 is the structured flowchart of a kind of swept signal generator of the present invention；
Fig. 3 is the FPGA inner function module schematic diagram of a kind of swept signal generator of the present invention；
Fig. 4 is the frequency marker signal generating circuit figure of a kind of swept signal generator of the present invention；
Fig. 5 is 4 view of the linear frequency sweep of a kind of swept signal generator of the present invention；
Fig. 6 be in a kind of swept signal generator of the present invention frequency sweep state machine redirect schematic flow sheet.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with embodiment and accompanying drawing, the embodiment of the present invention is described in further details.Here, the schematic description and description of the present invention is used for explaining the present invention, but not as a limitation of the invention.
Embodiment one
A kind of swept signal generator of the present invention uses FPGA to add the structure of processor, and FPGA produces swept-frequency signal as core component, and the inner function module of this signal generator is as in figure 2 it is shown, the structural principle block diagram of Fig. 2 a kind of swept signal generator that is the present invention.
In Fig. 2, a kind of swept signal generator of the present invention includes processor 201, memorizer 203, Subscriber Interface Module SIM 202, clock circuit 204, D/A converter module 606, analog module 207 and fpga chip 205, wherein:
Processor 201 realizes system control and signal processing, connects user controlled including (1) by Subscriber Interface Module SIM 202；(2) flash storage 203 is controlled；(3) calculate the parameters of swept-frequency signal, and be allocated to fpga chip 205, these parameters include 311 in Fig. 3,312,313,314,315,316.
Subscriber Interface Module SIM 202 includes keyboard, shows and controls port, such as GPIB, LAN, USB etc..
Flash storage 203 is for storing carrier waveform sampling point and the sampling point of frequency sweep curve.
Clock circuit 204 is for providing high-precision reference clock to fpga chip 205.
Fpga chip 205 is according to the setting of processor 201, the swept-frequency signal 212 of output digital form and frequency marker signal 211.
Digital to analog converter DAC module 206, is converted to analog quantity 213 by digital signal 212.
Analog circuit 207, processes the analogue signal of DAC206 output, including filtering, decay, amplification etc., just creates final swept-frequency signal 214.
Fpga chip 205 therein is concrete as it is shown on figure 3, Fig. 3 is fpga chip inner function module schematic diagram in one frequency sweep generator of the present invention, including:
Communication interface modules 300, is connected with described processor, and for receiving the instruction of processor, then the instruction 331 sent by processor is transmitted to fpga chip other module internal.
Clock module 301, is connected with described clock circuit, and the reference clock 332 providing outside carries out frequency synthesis, provides work clock 321 for other module internal.
Frequency sweep state machine 302, is used for providing different frequency sweep states；
The frequency sweep state machine 302 of the present invention, it is provided that four State-output swept-frequency signals, respectively:
Initial hold mode, with initial frequency output signal；
Scanning mode, the frequency of output signal changes to terminate frequency from initial frequency；
Terminate hold mode, to terminate frequency output signal；
Flyback state, the frequency of output signal changes to initial frequency from terminating frequency.
As a example by linear frequency sweep, Fig. 4 illustrates the frequency change procedure of these four states.The persistent period of these four states can be respectively provided with；Even can directly skip, the most only open " scanning " state, other three states are all closed.Therefore, before output swept-frequency signal, processor needs to arrange the opening and closing of these four states, and the time control word 311 corresponding to each state duration.
In frequency sweep state machine 302, these four states redirects flow process as shown in Figure 5.After starting frequency sweep, first judge whether this state opens, if not unlatching, then leap to NextState；If opened, then, after waiting until that the persistent period of this state completes, frequency sweep time totalizer can feed back a marking signal 322, and frequency sweep state machine 302 jumps into NextState after receiving this marking signal.
Frequency sweep state machine 302 is according to redirecting situation, and the time control word 323 selecting each state corresponding gives frequency sweep time totalizer 303.
Frequency sweep time totalizer 303, is connected with described frequency sweep state machine 302, for the marking signal that completes to described frequency sweep state machine 302 feedback time, and produces reading address 324 and exports to frequency sweep profile memory 325.
Under each state, time control word corresponding to four states is given frequency sweep time totalizer 303 by frequency sweep state machine 302 respectively, frequency sweep time totalizer 303 adds up with time control word, accumulator overflows and then illustrates that the persistent period of this state completes, and a marking signal is fed back to frequency sweep state machine 302.
The swept-frequency signal that the present invention realizes has four states, and therefore the accumulated value of frequency sweep time totalizer cannot function as reading address and is directly fed to frequency sweep profile memory 303, but is handled as follows respectively under each state:
Initial hold mode: read address and remain 0, reads first point under this state all the time from frequency sweep profile memory 304；
Scanning mode: accumulated value is given frequency sweep profile memory 303；
Terminate hold mode: read address and remain maximum, under this state, from frequency sweep profile memory 304, read last point all the time；
Flyback state: give frequency sweep profile memory 304 after being negated by accumulated value, implies that and starts value from last point, until first point.
Frequency sweep profile memory 304, is connected with described frequency sweep state machine 302, and for storing the frequency sweep curve that described frequency sweep state machine 302 determines, and frequency sweep curve sampling point is read in the reading address produced according to described frequency sweep time totalizer 303；The work of described frequency sweep profile memory 304 is after determining sweep method, and before swept-frequency signal starts output, the corresponding frequency sweep curve 312 of sweep method is written in frequency sweep profile memory 304 by processor；After frequency sweep starts, frequency sweep curve sampling point 325 is taken out in the reading address provided according to frequency sweep time totalizer 303.
Skew multiplier 305, is connected with described frequency sweep profile memory 304, by calculating the incremental portion obtaining swept frequency word；Specific practice is that frequency sweep curve sampling point is multiplied by a frequency sweep deviation ratio 313, and product is exactly the incremental portion 326 of swept frequency word.
Frequency word adder 306, is connected with described skew multiplier 305, for using the increment of frequency word and frequency word fundamental quantity sum as the frequency word 327 of carrier wave, it is assumed that the data bit width of frequency word 327 is K bit；
Phase accumulator 307, is connected with described frequency word adder 306, for adding up the frequency word of described carrier wave, and is exported as the reading address 328 of carrier wave memorizer by accumulation result；
Carrier wave memorizer 308, receives the output result of described phase accumulator 307 as reading address, for storing the sampling point 315 in one cycle of shape of carrier wave, such as sine wave, square wave, sawtooth waveforms etc..The result of carrier wave memorizer output is exactly the swept-frequency signal 333 that frequency changes according to sweep method；
Frequency marker comparator 309, is used for producing frequency marker signal 334.
Frequency marker is that the frequency in sweep measurement is spent surely, i.e. exports a marking signal when the frequency of swept-frequency signal changes to " mark frequency " place of user setup.The basic skills producing frequency marker signal is beat method, and its principle schematic is as shown in Figure 6.The signal that it uses a reference signal generator generation frequency to be " mark frequency ", the signal that this signal exports with swept signal generator is mixed, then through narrow-band filtering and vertical amplification, thus produce marking signal.The shortcoming of beat method is it is clear that not only circuit is complicated, cost is high, and owing to the non-linear distortion of analog device causes the degree of stability of frequency marker signal and accuracy the most poor, simultaneously because circuit delay can cause frequency surely to spend error.
Output frequency corresponding to each sampling point of frequency sweep curve can be calculated according to formula 1,2.
The frequency of swept-frequency signal 333=master clock 321 frequencies × frequency word 327/2K(formula 1)
Frequency word 327=fundamental quantity 314+ frequency sweep curve sampling point 325 × frequency sweep deviation ratio 313 (formula 2)
Frequency sweep curve is write by processor, and the address at each sampling point place is also known to processor.Therefore, address threshold 316 corresponding to the mark frequency of user setup is allocated to FPGA by processor, and frequency marker comparator compares reading address 324 and the address threshold 316 of frequency sweep time totalizer output, when the two is equal, then produce a marking signal, be frequency marker signal.
The swept signal generator realized according to the present invention, has the advantage that
Frequency sweep mode more horn of plenty, the most only scan function, also support initial holding, terminate holding, flyback, and the time of these four states can be arranged the most flexibly；
Fpga chip reasonable in internal structure, uses skew multiplier, it is not necessary to the software efforts plenty of time calculates swept frequency word, thus alleviates the burden of software, also accelerates system response time；
Compared with existing, only use an accumulator, not only reduce the resource occupation to FPGA, and the raising of beneficially FPGA timing performance, it is also beneficial to expand to parallel DDS structure；
The generation circuit of frequency marker signal has only to a comparator, the most simply；Owing to using digital methods, effect is the best, and not only frequency stability and accuracy are high, and do not have circuit delay, and frequency also would not be had surely to spend error；Additionally, only need to increase the number of comparator, the present invention is just easy to increase the number of frequency marker signal, and owing to current FPGA resource is the abundantest, the cost spent by increase on this frequency marker signal number is almost negligible；
FPGA is used to produce swept-frequency signal in DDS technical foundation, having that opposite band is wide, frequency switching time is short, frequency resolution is high, controls is flexible, upgrade and debug plurality of advantages such as facilitating the most naturally.
Particular embodiments described above; the purpose of the present invention, technical scheme and beneficial effect are further described; it is it should be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain being not intended to limit the present invention; all within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, should be included within the scope of the present invention.
Claims (4)
1. a swept signal generator, this swept signal generator includes processor, memorizer, Subscriber Interface Module SIM, clock circuit, D/A converter module, analog module and fpga chip, it is characterised in that this fpga chip includes:
Communication interface modules, is connected with described processor, for receiving the instruction of processor；
Clock module, is connected with described clock circuit, is used for providing work clock；
Frequency sweep state machine, is used for providing different frequency sweep states；
Frequency sweep time totalizer, is connected with described frequency sweep state machine, for the marking signal completed to described frequency sweep state machine feedback time, and produces the output of reading address；
Frequency sweep profile memory, is connected with described frequency sweep state machine, and for storing the frequency sweep curve that described frequency sweep state machine determines, and frequency sweep curve sampling point is read in the reading address produced according to described frequency sweep time totalizer；
Skew multiplier, is connected with described frequency sweep profile memory, by calculating the incremental portion obtaining swept frequency word；
Frequency word adder, is connected with described skew multiplier, for the increment of frequency word is added the frequency word obtaining carrier wave with frequency word fundamental quantity；
Phase accumulator, is connected with described frequency word adder, for adding up the frequency word of described carrier wave, and is exported by accumulation result；
Carrier wave memorizer, receives the output result of described phase accumulator as reading address, for storing the sampling point in one cycle of shape of carrier wave；
Frequency marker comparator, is used for producing frequency marker signal.
Swept signal generator the most according to claim 1, it is characterised in that described frequency sweep state machine provides four kinds of state swept-frequency signals, including:
Initial hold mode, with initial frequency output signal；
Scanning mode, the frequency of output signal changes to terminate frequency from initial frequency；
Terminate hold mode, to terminate frequency output signal；
Flyback state, the frequency of output signal changes to initial frequency from terminating frequency.
Swept signal generator the most according to claim 1, it is characterised in that:
Described skew multiplier provides frequency sweep deviation ratio and frequency sweep curve sampling point product, thus obtains the incremental portion of swept frequency word.
Swept signal generator the most according to claim 1, it is characterised in that:
Described frequency marker comparator obtain that described processor transmits by the mark frequency address threshold of user setup, and compared with the reading address of described frequency sweep time totalizer output, when the two is equal, produce a marking signal as frequency marker signal.
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| CN104935258B (en) * | 2014-03-18 | 2019-08-13 | 苏州普源精电科技有限公司 | A kind of swept signal generator can produce multiple frequency markings |
| CN105577121B (en) * | 2014-10-14 | 2021-01-22 | 普源精电科技股份有限公司 | Segmented frequency sweeping device and signal generator with segmented frequency sweeping function |
| CN104734639A (en) * | 2015-04-08 | 2015-06-24 | 中国科学院光电技术研究所 | Three-section type addressing high-precision DDS frequency sweeping signal generator |
| CN107231151B (en) * | 2017-05-24 | 2020-10-09 | 中国电子科技集团公司第四十一研究所 | Broadband frequency sweeping source design circuit and design method |
| CN107450417B (en) * | 2017-09-21 | 2023-04-25 | 广东电网有限责任公司电力科学研究院 | Nonlinear signal generation method and nonlinear signal generator |
| CN108983069A (en) * | 2018-05-28 | 2018-12-11 | 北京比特大陆科技有限公司 | chip scanning system and method |
| CN108761363B (en) * | 2018-05-31 | 2021-12-21 | 上海东软医疗科技有限公司 | Frequency sweep signal output method and device |
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