CN201548603U - Digital oscilloscope with equivalent sampling functions - Google Patents
Digital oscilloscope with equivalent sampling functions Download PDFInfo
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- CN201548603U CN201548603U CN2009202465489U CN200920246548U CN201548603U CN 201548603 U CN201548603 U CN 201548603U CN 2009202465489 U CN2009202465489 U CN 2009202465489U CN 200920246548 U CN200920246548 U CN 200920246548U CN 201548603 U CN201548603 U CN 201548603U
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Abstract
The utility model discloses a digital oscilloscope with equivalent sampling functions, which comprises an A/D conversion module 23, a control module 266 and a clock module 25. The control module 266 is connected to the A/D conversion module 23 and the clock module 25, the clock module 25 comprises a D/A conversion module 253, a reference clock module 252 and a sampling clock generating module 251, wherein the D/A conversion module 253 is controlled by the control module 266 to generate a control signal varying periodically, the reference clock module 252 is controlled by the control signal to generate a reference clock with periodically variable frequency, the sampling clock generating module 251 generating clocks according to the reference clock, the control module 266 is connected to the reference clock module 252 via the D/A conversion module 253, and the reference clock module 252 is connected to the sampling clock generating module 251 which is connected to the A/D conversion module 23. Sampling clock signals in the digital oscilloscope 2 is free of phase stepping, and then can achieve high equivalent sampling rate.
Description
Technical field
The utility model relates to the electric signal measurement field, particularly has the digital oscilloscope of equivalent sampling function.
Background technology
In the digital oscilloscope technology, the method for sampling commonly used has two kinds: real-time sampling and equivalent sampling.Real-time sampling is sampling to cycle or nonperiodic signal of constant duration normally, and the highest sample frequency of real-time sampling is the nyquist limit frequency.Equivalent sampling (Equivalent Sampling) is meant a plurality of cycle continuous samplings of cyclical signal and is combined as one-period and reappears signal waveform.Utilize the method for equivalent sampling can reappear the waveform that frequency substantially exceeds the signal of nyquist limit frequency.
Please refer to Fig. 1, shown in Fig. 1 is a kind of traditional digital oscilloscope with equivalent sampling function 1, and this digital oscilloscope 1 comprises a signal input part 11, A/D modular converter 12, data processing module 13, control module 14, clock module 15, two 16,17, display modules 18 of storer and load modules 19.Signal input part 11 is connected to A/D modular converter 12, A/D modular converter 12 is connected to data processing module 13, data processing module 13 is connected to control module 14, control module 14 is connected with storer 16,17, display module 18, load module 19 and clock module 15 respectively, and clock module 15 is connected to A/D modular converter 12.
During digital oscilloscope 1 work, the measured signal of signal input part 11 input one-periods, A/D modular converter 12 can be sampled to this measured signal under the control of the sampled clock signal that clock module 15 provides, the frequency and the phase place of the sampled clock signal that described control module 14 may command clock modules 13 send, described control module 14 are responsible for that also display module 18 is handled, preserves and controlled to the sampled data that A/D modular converter 12 is gathered and are shown work such as this sampled data.Clock module 13 is to be realized by FPGA.
Below in conjunction with the process and the principle that specify this digital oscilloscope 1 equivalent sampling with reference to figure 1 and Fig. 2.
Contrast for convenience and description, a plurality of cycles with measured signal 100 among Fig. 2 only illustrate with the form of one-period.
At first, control module 14 sends an equivalent sampling rate to clock module 15, and clock module 15 calculates a respective phase step value Δ t according to this equivalence sampling rate.Wherein, this equivalence sampling rate can be that the user passes through load module 19 inputs, also can be the pre-configured acquiescence equivalent sampling rate in digital oscilloscope 1 inside.
Then, sampled clock signal 191 of clock module output.Under the control of sampled clock signal 191, first cycle of 12 pairs of measured signals 100 of A/D modular converter carries out the 1st and takes turns sampling, gathers corresponding sampled data at a plurality of sampled point a, b, c.This control module 14 will this a plurality of sampled point a, b, the sampled data of c correspondence deposits this first memory 16 in.Putting down in writing the amplitude information of sampling point information and sampling point position measured signal etc. in this sampled data.
The 1st takes turns after the sampling, and clock module 15 increases a phase place step value Δ t on sampled clock signal 191 frequency basis of invariable, and has obtained sampled clock signal 192, makes the rising edge of a pulse of control sampling postpone Δ t arrival.Under the control of sampled clock signal 192, a plurality of sampled point d, e, f in the second period of 12 pairs of measured signals 100 of A/D modular converter carry out the 2nd and take turns sampling, obtain the sampled data of a plurality of sampled point d, e, f correspondence.With the 1st take turns the sampling identical, control module 14 also deposits a plurality of sampled datas of a plurality of sampled point d, e, f correspondence in first memory 16.
Similarly, third round is sampled at sampled point g, h, i up-sampling, and four-wheel is sampled at sampled point j, k, l up-sampling.By that analogy, each is taken turns after the sampling, and this sampled clock signal all can increase this phase place step value Δ t, and the next cycle of measured signal is sampled, up to this phase place step value Δ t one-period of sampled clock signal of having accumulated stepping.Control module 14 deposits a plurality of sampled datas that collect in each cycle in first memory 16.
Then, control module 14 is binned in the sampled data in the middle of the first memory 16 in the middle of the same cycle according to the sequencing of its sampled point.Because each is taken turns the sampling of sampling and previous round and compares and postponed Δ t, and, it is identical that each takes turns in the middle of the sampling interval time between the sampled point, so this sequencing can be according to following rule: the 2nd sampled point of the 1st sampled point of the 1st to N wheel sampling, the 1st to N wheel sampling ..., the 1st to N wheel sampling M sampled point.Wherein, N represents to sample and takes turns the maximal value of number, and M represents to take turns the maximal value of sampling number in the sampling.Specific to this for example, this sequencing is sampled point a, d, g, j, b, e, h, k, c, f, i, l.Sampled data after control module 14 will be recombinated according to the reorganization after sequential storage in the middle of second memory 17.
Then, the sampled data of control module 14 after according to the reorganization in the middle of the second memory 17 is depicted as curve, is presented on the display module 17, promptly realized the process of equivalent sampling.
As mentioned above, because clock module 15 need carry out the phase place step-by-step operation to sampled clock signal, therefore module 15 is to be realized by the higher FPGA of cost all the time.
But traditional digital oscilloscope with equivalent sampling function 1 but exists following problem:
Because after each periodic sampling, this sampled clock signal need increase a phase place step value Δ t, and the phase place step value Δ t that the clock module 15 that utilizes FPGA to realize is produced can be subjected to the restriction of the precision of FPGA own.
The utility model content
Realize that in order to solve the prior art digital oscilloscope equivalent sampling need rely on the problem of phase place step value, the utility model provides a kind of digital oscilloscope that does not need the phase place step value to realize equivalent sampling.
A kind of digital oscilloscope with equivalent sampling function, be used for the measured signal of one-period is measured, described digital oscilloscope comprises an A/D modular converter, a control module and a clock module, described control module is connected to described A/D modular converter and clock module, described clock module comprises a D/A modular converter that is used to be subjected to described control module control and produces the control signal of one-period variation, a reference clock module and a sampling clock generation module that produces sampling clock according to described reference clock that is used to be subjected to described control signal control and produces the reference clock of a frequency period variation, described control module is connected to described reference clock module by described D/A modular converter, described reference clock module is connected to described sampling clock generation module, and described sampling clock generation module is connected to described A/D modular converter.
Digital oscilloscope of the present utility model is because when sampling to a plurality of cycles of measured signal, adopt the sampled clock signal of a frequency change, make that the sampled point in a plurality of cycles of measured signal can be not just the same, therefore need not when each cycle, to carry out the phase place stepping, and then this sampled clock signal can reach higher frequency, realizes higher equivalent sampling rate.
Description of drawings
Fig. 1 is a kind of modular structure synoptic diagram of the traditional digital oscilloscope with equivalent sampling function 1.
Fig. 2 is the principle schematic of the equivalent sampling process that adopted of digital oscilloscope 1 shown in Figure 1.
Fig. 3 is the modular structure synoptic diagram of the new digital oscillograph 2 of this practical better embodiment.
Fig. 4 is the function curve of analog control signal amplitude U1 t variation in time.
Fig. 5 is the circuit diagram of VCXO 270.
Fig. 6 is the frequency f of the reference clock signal of VCXO 270 output pin OUTPUT output
1T in time
1The function curve that changes.
Fig. 7 is the principle schematic of the equivalent sampling process when being measured signal frequency positive integer times of the frequency when sampled clock signal.
Fig. 8 is the synoptic diagram of the equivalent sampling principle that adopted of digital oscilloscope 2 shown in Figure 3.
Fig. 9 is the synoptic diagram with a plurality of periodic sampling data rearrangements and building-up process.
Figure 10 is the circuit diagram of reference clock module 252 another embodiment.
Figure 11 is the circuit diagram of an embodiment of reference clock module 252 shown in Figure 10.
Embodiment
Introduce a better embodiment of the utility model digital oscilloscope below.
Please refer to Fig. 3, the digital oscilloscope 2 with equivalent sampling function comprises a signal input part 21, trigger module 22, A/D modular converter 23, clock module 25, control module 266, memory module 27, a display module 28 and a load module 29.Control module 266 comprises a synthesis module 24 and a microprocessor 26.Synthesis module 24 comprises a pulsewidth amplification module 241 and a data processing module 242.Clock module 25 comprises a sampling clock generation module 251, a reference clock module 252 and a D/A modular converter 253.
One first digital controlled signal of microprocessor 26 outputs is to D/A modular converter 253, and one first analog control signal of control D/A modular converter 253 outputs is to reference clock module 252.This first analog control signal is the signal of a voltage cycle variation.Please refer to Fig. 4, in the present embodiment, first analog control signal is an amplitude U1 t continually varying triangular wave in time.This triangle wave frequency is 1Hz.
Please refer to Fig. 5, reference clock module 252 is a VCXO (VCXO) 270 in the middle of present embodiment, and VCXO 270 comprises the power pins VDD, the ground pin GND that is connected to common port, a Control of Voltage pin VC_ON and the output pin OUTPUT that are connected to logic voltage+3.3V.The Control of Voltage pin VC_ON of VCXO 270 links to each other with D/A modular converter 253, receives this first analog control signal, and output pin OUTPUT then links to each other with sampling clock generation module 251, is its output reference clock signal.The characteristic of VCXO 270 is: change the voltage that is applied on the Control of Voltage pin VC_ON, can change the frequency that output pin OUTPUT goes up the reference clock signal of output.Therefore, when this Control of Voltage pin VC_ON has imported this triangular wave, please refer to Fig. 6, the frequency f of the reference clock signal of output pin OUTPUT output
1T in time
1Also being the triangular wave form changes.In the middle of present embodiment, the frequency trim ratio of this reference clock signal has only 100ppm, such as, the reference clock signal of 25MHz, the scope of its frequency change has only 2.5kHz.
Referring again to Fig. 3, sampling clock module 251 receives this reference clock signal, and it is produced this sampled clock signal as the reference clock.Microprocessor 26 is also exported one second digital controlled signal to sampling clock module 251, and the frequency of this sampled clock signal is subjected to the control of this second digital controlled signal and changes.Because in the present embodiment, sampling clock module 251 is phase-locked loop chip in the middle of present embodiment, so can directly be controlled by second digital controlled signal, and needn't be converted to the form of simulating signal.
As previously mentioned, why first analog control signal is arranged to an amplitude continually varying triangular wave, purpose is constantly to change for the frequency that makes reference clock signal, the frequency that causes sampled clock signal also constantly changes, and then makes the sampled clock signal frequency can not rest on the state of the integral multiple of measured signal frequency always.That is to say, even if a certain moment or sometime the section, the frequency of sampled clock signal is the integral multiple of the frequency of measured signal, but because the characteristic that the frequency of sampled clock signal constantly changes, so next moment or next time period, the sampled clock signal frequency can not be the integral multiple of the frequency of measured signal yet.Do further explanation again, prevent that the sampled clock signal frequency from being that the reason of the integral multiple of measured signal frequency is: if the sampled clock signal frequency is the integral multiple of measured signal frequency, then this A/D modular converter 23 will be sampled in the same position in each cycle of this measured signal, cause the overlapping of sampling location in each cycle, therefore can't realize equivalent sampling.For example, please refer to Fig. 7, when the sampled clock signal frequency was 2 times of measured signal frequency, the mistiming t1 between sampled point 611 and the trigger point 610 and sampled point 621 equated with mistiming t2 between the trigger point 620.Promptly, sampled point 611 position in the period 1 in sinusoidal wave 600 is identical with sampled point 621 position in second round in sinusoidal wave 600, sampled point 612 position in the period 1 in sinusoidal wave 600 is identical with sampled point 622 position in second round in sinusoidal wave 600, should the period 1 and the sampled point 611,612,621,622 of second round when being incorporated in the one-period, sampled point 611 will overlap with 621, sampled point 612 will overlap with sampled point 622, therefore can't realize equivalent sampling.
Referring again to Fig. 3, in addition, microprocessor 26 also is responsible for 27 pairs of data of control store module and is stored, controls instruction and the work such as control display module 28 display waveforms, status bar and other information that load module 29 received and resolved outside input.Load module 29 is a keyboard in the middle of present embodiment, and display module 28 is a LCD.Pulsewidth amplification module 241 can receive the pulse signal from data processing module 242, and the pulsewidth of this pulse signal is amplified, and the pulse after again pulsewidth being amplified sends back to data processing module 242.
For the structure of digital oscilloscope 2 more clearly is described, be described in detail below in conjunction with the process of this measured signal being carried out equivalent sampling.
Please together with reference to Fig. 3 and Fig. 8, in the middle of present embodiment, illustrate as one, this measured signal is that frequency is a F sinusoidal signal 400.In order to simplify description, four cycles with sinusoidal signal 400 illustrate here.
Because the sampled data that equivalent sampling need will collect in a plurality of cycles of measured signal merges in the one-period and shows, and digital oscilloscope 2 needs the waveform of stable demonstration measured signal, so trigger module 22 identical location triggered in each cycle of this measured signal.Particularly, trigger module 22 has a triggering level, and when this measured signal rises to when being higher than this triggering level by being lower than this triggering level, this trigger module 22 just can be exported this trigger pip.The part that this sinusoidal signal 400 rose in each cycle and these triggering level 500 intersections are the trigger point 410,420,430,440 in each cycle, the i.e. pairing position of chain line among Fig. 7.
Behind the trigger point 410 in first cycle of sinusoidal signal 400, a plurality of sampled points 411～414 up-samplings of A/D modular converter 23 offset of sinusoidal signal 400 on the basis of this sampled clock signal 450 and obtain corresponding a plurality of sampled datas.Same, behind the trigger point 420 in the second period of this measured signal, sampled point 421～424 up-samplings of A/D modular converter 23 offset of sinusoidal signal 400 on the basis of this sampled clock signal 450 and obtain corresponding a plurality of sampled datas.Sample respectively and obtain corresponding a plurality of sampled datas at the sampled point 431～435 and 441～444 in the 3rd and the 4th cycle of measured signal.By that analogy.Because the frequency of sampled clock signal constantly changes, therefore the identical situation of sampled point in two cycles can not appear.
Next, for the sampled data with four cycles combines, need know the relative position of first sampled point 411,421,431,441 in sinusoidal signal 400 in each cycle.Because the trigger point 410,420,430,440 in each cycle is arranged in the same position of sinusoidal signal 400, therefore can know the relative position of first sampled point 411,421,431,441 in sinusoidal signal 400 in each cycle with the mistiming between the corresponding trigger point 410,420,430,440 by measuring first sampled point 411,421,431,441 in each cycle.Again because the frequency of sampled clock signal is generally higher, mistiming between trigger point and the sampled point is less, therefore, according to burst pulse of mistiming t1 generation of the unknown between this first cycle internal trigger point 410 and the 1st sampled point 411, the pulsewidth size of this burst pulse is corresponding to mistiming t1 earlier for data processing module 242.Data processing module 242 exports this burst pulse to pulsewidth amplification module 241, pulsewidth amplification module 241 returns to data processing module 242 with this broad pulse after this burst pulse is enlarged into a broad pulse that is convenient for measuring according to a predefined known enlargement factor again.Data processing module 242 is measured the pulse width of these broad pulses, obtains the pairing time span of this pulse, again with this time span divided by this enlargement factor, thereby calculate this mistiming t1.
Based on same process, data processing module 242 also calculates the mistiming t4 between mistiming t3 between mistiming t2 between second period internal trigger point 420 and the 1st sampled point 421, the 3rd cycle internal trigger point 430 and the 1st sampled point 431 and the 4th cycle internal trigger point 440 and the 1st sampled point 441.Can obtain t3＜t2＜t4＜t1 by calculating.
Because the frequency trim ratio of this reference clock signal has only 100ppm, in a plurality of cycles, the variation of sampling interval relatively and sampling interval be very little, therefore, can be similar to and think in four cycles that the relative position of the 1st sampled point 411,421,431,441 is the same in the relative position of the 2nd sampled point in sinusoidal signal 400 and four cycles, in four cycles in the relative position of the 3rd sampled point in sinusoidal signal 400 and four cycles the relative position of the 1st sampled point 411,421,431,441 also be the same, by that analogy.Because mistiming t1, t2, t3, t4 between trigger point 410,420,430,440 and first sampled point 411,421,431,441 have measured acquisition, promptly the relative position of the 1st sampled point 411,421,431,441 is known in four cycles, and therefore the relative position of other sampled points is also decided in four cycles.Please refer to Fig. 9, pulsewidth amplification module 241 according to mistiming t1, t2 between the 1st sampled point 411,421,431,441 in four cycles and the trigger point 410,420,430,440, t3, t4 with sampled point 411～414,421～424,431～435,441～444 orderings in the same cycle, and send microprocessor 26 to.Sampled point 411～414,421～424,431～435,441～444 pairing sampled datas after microprocessor 26 will be resequenced are saved in the memory module 27 according to the order after arranging, and convert waveform to and be presented on the display module 28.
As other giving an example, data processing module 242 also can produce this burst pulse according to the mistiming between each cycle internal trigger point and the 2nd sampled point, perhaps produce this burst pulse, by that analogy according to the mistiming between each cycle internal trigger point and the 3rd sampled point.For example, can calculate the mistiming t1 ' between first cycle internal trigger point 410 and the 2nd sampled point 412, mistiming t2 ' between second period internal trigger point 420 and the 2nd sampled point 422, mistiming t3 ' between the 3rd cycle internal trigger point 430 and the 2nd sampled point 432, the mistiming t4 ' between the 4th cycle internal trigger point 440 and the 2nd sampled point 442.According to this t1 ', t2 ', t3 ', t4 ' whole sampled points are sorted.
As other giving an example, data processing module 242 can produce a burst pulse according to each sampled point and trigger point in each cycle, process pulsewidth amplification module 241 is enlarged into strides pulse accordingly, measure and calculate the mistiming between this sampled point and the trigger point again by data processing module 242, and whole sampled points are sorted with this.
As other giving an example, please refer to Figure 10, reference clock module 252 can also be circuit 271.Circuit 271 comprises an oscillatory circuit 272, crystal X1, resistance R 1, capacitor C 1, a diode D1, a control voltage input terminal 273 and a reference clock output terminal 274, oscillatory circuit 272 is in parallel with crystal X1, control voltage input terminal 273 is connected to crystal X1 through resistance R 1, capacitor C 1 in regular turn, the negative pole of diode D1 is connected to the public connecting end 275 of resistance R 1 and capacitor C 1, the plus earth of diode, oscillatory circuit 272 is connected to reference clock output terminal 274.
Please refer to Figure 11, as one for example, oscillatory circuit 272 comprises a not gate U1A, a resistance R 2, a resistance R 3, a resistance R 4, a capacitor C 2 and a capacitor C 3, resistance R 2 and not gate U1A parallel connection, the input end of not gate U1A is through capacitor C 2 ground connection, the output terminal of not gate U1A is through capacitor C 3 ground connection, the output terminal of not gate U1A also is connected to reference clock output terminal 274 through resistance R 3, the input end of not gate U1A is also connected to the public connecting end 291 of capacitor C 1 and crystal X1, and the output terminal of not gate U1A also is connected to the other end 292 of crystal X1 through resistance R 4.
Resistance R 3 is the build-out resistor of source end, is used to reduce the overshoot of clock.Capacitor C 2, C3 are the load capacitance of crystal X1, and its size has determined the oscillation frequency of crystal X1.The control voltage that applies on the voltage input end 273 is loaded into diode D1 negative pole by resistance R 1, diode D1 oppositely ends, it is equivalent to a little electric capacity, and capacitor C 1, diode D1 just are equivalent to be added in the electric capacity of two series connection of crystal X1 public connecting end 291 like this.Regulate the control voltage that applies on the control voltage input terminal 273, just can change the equivalent capacity of diode D1, thereby change the load capacitance of crystal X1, thereby change oscillation frequency.
As other for example, first analog control signal can also be the amplitude U1 signal that gradually changes with certain stepping of t in time.In addition, the frequency of this first analog control signal can also be made as other values according to actual needs.
As other giving an example, data processing module 242 can be programmable logic device (PLD) such as CPLD, and microprocessor 26 is processors such as DSP, ARM, single-chip microcomputer or CPU.
In addition, the clock module 25 of digital oscilloscope 2 of the present utility model can not rely on FPGA and realize, has therefore improved design freedom, has reduced cost.
Claims (8)
1. digital oscilloscope with equivalent sampling function, be used for the measured signal of one-period is measured, described digital oscilloscope comprises an A/D modular converter, a control module and a clock module, described control module is connected to described A/D modular converter and clock module, it is characterized in that: described clock module comprises a D/A modular converter that is used to be subjected to described control module control and produces the control signal of one-period variation, a reference clock module and a sampling clock generation module that produces sampling clock according to described reference clock that is used to be subjected to described control signal control and produces the reference clock of a frequency period variation, described control module is connected to described reference clock module by described D/A modular converter, described reference clock module is connected to described sampling clock generation module, and described sampling clock generation module is connected to described A/D modular converter.
2. digital oscilloscope according to claim 1 is characterized in that: described D/A modular converter is the D/A modular converter that is used to produce triangular wave.
3. digital oscilloscope according to claim 1 is characterized in that: described sampling clock generation module is a phaselocked loop.
4. digital oscilloscope according to claim 1 is characterized in that: described reference clock module is a VCXO.
5. digital oscilloscope according to claim 4, it is characterized in that: described reference clock module comprises an oscillatory circuit, a crystal, one first resistance, one first electric capacity, a diode, a control voltage input terminal and a reference clock output terminal, described oscillatory circuit connects described crystal, described control voltage input terminal is passed through described first resistance in regular turn, first electric capacity is connected to described crystal, the negative pole of described diode is connected to the public connecting end of described first resistance and first electric capacity, the plus earth of described diode, described oscillatory circuit are connected to described reference clock output terminal.
6. digital oscilloscope according to claim 5, it is characterized in that: described oscillatory circuit comprises a not gate, one second resistance, one the 3rd resistance, one the 4th resistance, one second electric capacity and one the 3rd electric capacity, described second resistance and described not gate parallel connection, the input end of described not gate is through described second capacity earth, the output terminal of described not gate is through described the 3rd capacity earth, the output terminal of described not gate also is connected to described reference clock output terminal through described the 3rd resistance, the input end of described not gate is also connected to the public connecting end of described first electric capacity and crystal, and the output terminal of described not gate also is connected to the other end of described crystal through described the 4th resistance.
7. digital oscilloscope according to claim 1, it is characterized in that: described control module comprises a synthesis module and a microprocessor, synthesis module comprises a data processing module and a pulsewidth amplification module, described data processing module is connected with described control module with described A/D modulus of conversion respectively, and described pulsewidth amplification module is connected with described data processing module.
8. digital oscilloscope according to claim 7 is characterized in that: described data processing module comprises FPGA.
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