CN103155131A - 半导体模块和制造半导体模块的方法 - Google Patents

半导体模块和制造半导体模块的方法 Download PDF

Info

Publication number
CN103155131A
CN103155131A CN2011800497358A CN201180049735A CN103155131A CN 103155131 A CN103155131 A CN 103155131A CN 2011800497358 A CN2011800497358 A CN 2011800497358A CN 201180049735 A CN201180049735 A CN 201180049735A CN 103155131 A CN103155131 A CN 103155131A
Authority
CN
China
Prior art keywords
contact element
metal level
semiconductor module
deepening
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011800497358A
Other languages
English (en)
Inventor
N.舒尔茨
S.哈特曼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ABB Research Ltd Switzerland
ABB Research Ltd Sweden
Original Assignee
ABB Research Ltd Switzerland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ABB Research Ltd Switzerland filed Critical ABB Research Ltd Switzerland
Publication of CN103155131A publication Critical patent/CN103155131A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding

Abstract

本发明涉及半导体模块（10），其包括衬底（24），特别地由陶瓷绝缘体形成，以及至少一个金属层（26），特别地在所述衬底（24）上形成，其中金属层（26）包括延深部（40），用于放置和固定接触元件（16），该接触元件（16）至少部分是“L”型并且包括用于将接触元件（16）固定在延深部（40）处的第一臂（34）以及用于互连接触元件（16）的第二臂（36），其中延深部（40）具有大于接触元件（16）的水平尺寸约≤0.5mm的水平尺寸。根据本发明的半导体模块（10）展现提高的可靠性并且此外以高度可再制造方式生产。

Description

半导体模块和制造半导体模块的方法
技术领域
本发明涉及半导体模块。本发明进一步涉及制造半导体模块的方法。
背景技术
已知多种半导体模块并且在许多不同的电子装置中使用它们。为了形成或相应地制造半导体模块，半导体模块的不同电部件必须互相接触来提供互连内部结构。另外，需要提供外部接点来使半导体模块的一个或多个电部件连接到外部接触装置。
作为示例，为了实现与半导体模块的外部电接触，提供端子作为接触元件并且将它钎焊在陶瓷衬底的金属化的顶部上，这是众所周知的。已知的钎焊技术的主要缺点是在端子与衬底之间的钎焊连接的热和机械循环下可靠性受限。因此，该连接并且从而整个半导体模块仅具有有限的寿命。
此外，钎焊连接仅承受有限的操作温度。具体地，为了在大部分情况下提供安全且可靠的操作状况，不应超过125℃的温度。
因此已知通过用焊接连接来代替半导体模块的一个或多个接点之间的钎焊连接而克服该问题。特别地，超声波或相应地能量用于形成焊接连接。
例如在W. Rusche等人的“Ultrasonic Metal Welding（超声金属焊接）”（2008年10月，Bodo's Power Magazine，40-41页）中，描述了使用超声金属焊接用于功率模块内的内部接触。具体地，描述了焊接工具在可移动联接搭配物中引入压力和超声能量。
在使用这样的技术的情况下，将在水平面中产生超声波，由超声波发生器采用示范性方式产生。由于超声波发生器的水平振荡，平行于振幅的力可作用于接触元件。因此，可存在接触元件在水平面中移动的风险。这导致将接触元件焊接的位置可能不是预计位置的劣势。因此，形成的半导体模块可能是不能使用的。另外，存在接触元件变形并且因此在它移动或相应地滑动时被机械削弱的风险。这再次导致形成的半导体模块不能使用的劣势。此外，焊接工艺变得不能再制造。
为了避免这些劣势，使用更强的焊接参数可是可能的。具体地，使用更高的焊接能量和/或更高的压紧力是可能的。然而，这可导致接触元件焊接到的接触区或接触元件自身的损坏。
因此从WO 2007/033829 A2获悉功率半导体模块和生产其的方法。根据该现有技术，接点凭借超声发生器经由超声焊接而形成。超声焊接操作还可以用于使接触区与接触端联接，并且因此用于使接点与功率半导体模块的脚区联接。具体地，超声发生器被带到接触元件的接触端，其中接触端被压到要连接的接触区。通过将超声能量引入接触元件与衬底之间的界面，该脚被焊接到衬底上。在实施该步骤中，保持和定位装置使接触元件保持在适当位置以避免接触元件在水平面中移动。
然而，这样的保持和定位装置总是导致工艺变得更复杂并且从而必需相当复杂的设备要求。
从EP 1 711 040 A1获悉这样的电路装置，其中半导体和汇流母线接合到陶瓷基板。根据该文献，在衬底上提供布线层，在该衬底的一部分上形成涂覆金属层来提供布线层被涂覆在其中的区。另外，提供暴露区，在该暴露区中暴露布线层。半导体连接到涂覆区，而汇流母线直接连接到暴露区内的布线层。
根据该文献，考虑到汇流母线的末端部分的接触区域的变化，暴露区域确定为具有适当的余量。因此，该暴露区域适应于允许固定具有不同形状和尺寸的汇流母线。
发明内容
本发明的目的是提供改进的半导体模块，其将避免本领域内已知的劣势中的至少一个。
本发明的另外的目的是提供改进的制造半导体模块的方法，其将避免本领域内已知的劣势中的至少一个。
特别地，本发明的目的是提供半导体模块和制造半导体模块的方法，其中更容易以更高的可再制造性进行该制造方法并且其中该半导体模块具有提高的可靠性。
该目的由根据权利要求1的半导体模块实现。此外，该目的由根据权利要求7的制造半导体模块的方法实现。本发明的优选实施例在从属权利要求中限定。
本发明涉及半导体模块，其包括：衬底，特别地由陶瓷绝缘体形成；和至少一个金属层，特别地在该衬底上形成，其中该金属层包括用于放置和固定接触元件的延深部，该接触元件至少部分是“L”型并且包括用于将接触元件固定在该延深部处的第一臂，和用于互连接触元件的第二臂，其中该延深部具有大于接触元件的水平尺寸约≤0.5mm的水平尺寸。
根据本发明，接触元件可在预形成的延深部处在金属层上放置或相应地排列以及设置在预计位置处。因为延深部可在进行接触元件在金属层上的固定工艺之前形成，延深部可容易设置和定位在明确限定的位置处。因此，除这样的延深部外，接触元件可定位在明确限定和预计位置中。
此外，由于接触元件被精确地定位并且此外通过延深部而保持在适当位置中这一事实，在固定工艺期间（特别地，在焊接工艺期间）避免接触元件在金属层上的水平面中滑动或相应地移动。因此，避免了焊接工艺的不利影响。因此，可以采用明确限定和可再制造的方式制造根据本发明的半导体模块。
由于接触元件通过延深部而保持在适当位置这一事实，不需要使接触元件保持在适当位置的另外和单独的固定装置。尤其可省略使接触元件保持在适当位置的单独的保持和定位装置。这允许以容易的方式制造根据本发明的半导体模块而不需要高度复杂的设备设置由此以非常可再制造的方式制造。
延深部从而设计成特别在焊接工艺期间使接触元件在水平面中保持在适当位置，该水平面特别地由金属层的平面限定。从而大致上防止接触元件在水平面上移动。然而，接触元件在水平面中的有限可移动性可以是优选的并且是没有问题的。
具体地，延深部具有大于接触元件（特别地是固定到金属层的接触元件的那部分）的水平尺寸约≤0.5mm的水平尺寸。这允许接触元件在水平面上的有限以及根据本发明的可接受的可移动性，由此无论如何都确保接触元件大致上固定在预计位置。然而，该特征进一步简化将接触元件放置在延深部中或延深部处。
因此，延深部不适应于每个具有不同大小的多个接触元件。与此相反，假设延深部具有大于接触元件的水平尺寸约≤0.5mm的水平尺寸，延深部适应于限定的接触元件，从而基本上防止接触元件的可移动性，从而无论如何都允许容易且舒适地固定接触元件。
除此之外，接触元件从而可容易地定位在延深部中，由此以简单的方式定位在预计位置。此外，可容易形成延深部。例如，延深部可在金属层的沉积步骤或类似形成，或通过在沉积后使金属层结构化而形成。另外，延深部是避免接触元件在水平面中移动（尤其在焊接工艺期间）的容易且特别牢固的方法。
接触元件由此可以是适合于接触所述金属层的任何接触元件。例如，接触元件可以是这样的接触元件，用于内部接触半导体模块的不同电路或相应地电元件。然而，接触元件包括用于将金属层或相应地这样的半导体模块外部接触至外部接触装置的端子，这是最优选的。
另外，接触元件至少部分是“L”型并且包括用于将接触元件固定在延深部处的第一臂，和用于使接触元件与例如外部装置互连的第二臂。这样的接触元件尤其优选地用于将它焊接在延深部处，或相应地在延深部中。根据本发明的至少部分是“L”型的接触元件将由此意指至少底部部分（接触元件的底部部分固定到金属层）是“L”型的。第一臂由此可容易定位在延深部处并且压紧力可以明确限定的方式施加于延深部上，由此施加超声能量以将第一臂或相应地接触元件焊接到金属层。由于接触元件的“L”型形式，第二臂与金属层间隔开而定位，由此，它可容易与例如外部接触装置互连。
根据本发明，“L”型形式由此将意指第一和第二臂设置成关于彼此大致上成矩形的设计。然而，如果第一臂大致上位于金属层上或相应地延深部处的平面，接触元件可偏离矩形形状，并且第二臂这样进行：它的末端与金属层的平面间隔开，使得可容易建立互连。
根据本发明，金属层可以是涂层，其沉积在衬底上或在另一个层上，或它可以是沉积在衬底上或另一个层上的小型金属化区。然而，金属层可以是任何金属或金属化层或板，其设置在半导体模块中并且其将被接触。金属层优选地由从下列材料选择的材料制成：铜（Cu）、金（Au）、银（Ag）、铝（Al）或包括Cu、Au、Ag和/或Al的合金。
半导体模块可优选地包括本领域内已知的任何功率半导体模块。特别地，功率半导体模块包括功率半导体器件。功率半导体器件的示例采用非限制性的方式包括二极管、晶体管、类似绝缘栅双极晶体管（IGBT）和集成电路。
根据本发明的实施例，接触元件包括配合部件，特别地在它的第一臂处，用于与延深部配合。此外，这提高将接触元件放置并且保持在预计位置处的效果。如将在下文意识到的，如果配合部件设置成与延深部配合或相应地交互，则它可以是任何适合的部件。
根据另外的实施例，延深部具有≥100μm的深度。这样的设置确保接触元件保留在延深部处，尤其在焊接工艺时，并且从而可靠地保持在适当位置。从而避免在将接触元件固定到金属层时它滑出延深部。
根据另外的实施例，延深部至少部分由斜切边环绕。这也简化了将接触元件放置在延深部中或延深部处。
在本发明的再另外的实施例中，中间层设置在金属层与衬底之间。该设置导致衬底受到附加中间层的机械和/或热保护的优势。另外，比起在衬底金属化自身中的延深部，更容易制作在一侧上具有延深部的金属层。附加层，特别地金属层，可在其中半导体芯片也附连到衬底的相同的工艺步骤中附连到衬底。
此外，本发明涉及制造半导体模块的方法，其包括使接触元件与金属层接触的步骤，该接触元件至少部分是“L”型并且包括用于将接触元件固定在延深部处的第一臂和用于互连接触元件的第二臂，并且该金属层包括用于放置接触元件的延深部，其中该延深部具有大于接触元件的水平尺寸约≤0.5mm的水平尺寸，所述方法进一步包括以下步骤：
－在延深部处将接触元件按压到金属层上，
－将超声能量施加到接触元件与金属层的界面用于将接触元件焊接到金属层。
根据本发明，接触元件从而通过延深部而被放置在金属层上。这导致类似在上文关于根据本发明的半导体模块描述的优势。
除此之外，接触元件通过超声焊接工艺连接到金属层。根据本发明制造的半导体模块从而未展现与循环有关的劣势。关于本发明，循环意指周期变化的条件的影响，尤其关于温度和/或机械影响。这也使根据本发明的半导体模块的可靠性特性提高。
根据本发明的半导体模块的可靠性进一步通过焊接连接可维持200℃或以上的温度这一事实而提高。这另外使根据本发明的方法制造的半导体模块甚至适合于高功率应用。
另外，半导体模块可根据本发明制造而不需要类似焊料或接合线的消耗品。此外，可在没有另外的覆镀或额外的清洗步骤的情况下进行制造工艺。这导致根据本发明的方法关于环境的角度是有利的优势。另外，传统的工作步骤可省略，从而使根据本发明的方法节省时间并且从而节省成本。
此外通过将接触元件焊接到金属层而形成高传导连接。这使根据本发明的半导体模块特别适合于高功率应用，其中大量的电流必须通过该连接而传导。因此，根据本发明的半导体模块优选地包括高功率半导体模块。
附图说明
本发明的主旨的另外的特征、特性和优势在从属权利要求、图和相应的图和示例的下列说明中公开，其采用示范性的方式示出根据本发明的半导体模块的实施例和示例。
在图中：
图1示出半导体模块的设置的截面侧视图；
图2示出根据本发明的半导体模块的实施例的局部截面侧视图；
图3示出根据本发明的半导体模块的另外的实施例的局部截面侧视图；
图4示出不是本发明的一部分的半导体模块的实施例的局部截面侧视图；
图5示出根据本发明的半导体模块的另外的实施例的局部截面侧视图；
图6示出根据本发明的半导体模块的另外的实施例的局部截面侧视图；
图7示出不是本发明的一部分的半导体模块的另外的实施例的局部截面侧视图。
具体实施方式
在图1中，示意地示出半导体模块10的设置。具体地，描述所述半导体模块10的内部结构。该半导体模块10包括外壳12，在其中设置至少一个半导体器件14。在优选实例中该半导体器件14可以是例如绝缘栅双极晶体管（IGBT）、二极管、金属氧化物半导体场效应晶体管（MOSFET）或类似物的功率半导体器件。根据图1，提供二极管和IGBT。该半导体器件14或多个半导器件14经由接触端子或相应地接触元件16并且优选地经由辅助端子18而能连接，其中该半导体器件14优选地由铝接合线20接合。
作为绝缘体，环氧树脂层22可设置在半导体器件14上。半导体器件14可进一步设置在衬底24或相应地晶圆（由陶瓷绝缘体、特别地由氮化铝陶瓷绝缘体形成）上。接触元件16以及辅助端子18经由金属化或相应地金属层26、特别地经由铜金属化而连接到衬底24。另外，衬底24在它的底侧连接到另外的金属化28，特别是铜金属化，并且经由焊料29连接到基板32。外壳12内部余下的容积用例如硅凝胶30填充。
接触元件16与金属层26之间的连接具体地在下面的图2至7中示出，其中相同或相当的元件由相同的标号引用。
在图2中，示出衬底24连同金属层26和另外的金属化28。为了接触金属层26，提供接触元件16。
接触元件16至少部分是“L”型，即至少在它的底侧处。因此它包括用于将接触元件16固定在金属层26处的第一臂34和用于使它例如与外部接触装置互连的第二臂36，未如此示出该外部接触装置。
为了将接触元件16放置或相应地使它定位在预计位置，根据本发明，金属层26包括金属层26中的延深部40并且从而可包括收容部。因此，接触元件16或相应地接触元件16的第一臂34可装配到所述延深部40中以便定位在预计位置，这是明显的。接触元件16，特别是它的第一臂34，可固定到金属层26。因此，延深部40的目的中的一个是易于发现接触元件16在金属层26上的预计位置。
延深部40优选地具有≥100μm的深度。这允许接触元件16在延深部40中的牢固装配以牢固地保持在适当位置。
即使预计延深部40具有在固定工艺期间（特别地在焊接工艺时）使接触元件16保持在适当位置的第二主要目的，延深部40具有大于接触元件16的水平尺寸、特别大于接触元件16的第一臂34的水平尺寸约≤0.5mm的水平尺寸，这可是适合的。这改进将接触元件16设置在延深部40中的步骤。
一旦接触元件16被定位在延深部40中，它必须固定在金属层26上。该步骤描述如下，其中必须注意，该步骤可独立于接触元件16和/或延深部40的特殊设置而进行并且从而可相似地在根据下列图的实施例中进行。
将接触元件16固定到金属层26的步骤特别地是制造半导体模块的方法的步骤。在使接触元件16与金属层26接触之后，接触元件16被压靠着金属层26。在类似上文描述的实施例中，接触元件16经由第一臂34被压靠着金属层26。这可通过将焊接工具42压靠着接触元件16、特别地靠着第一臂34而进行。这由在图2中示出的箭头44示意地示出。
焊接工具42优选地包括用于产生超声波或相应地超声能量的部件。作为示例，焊接工具42可包括超声发生器。因此，超声能量施加到接触元件16与金属层26的界面46。凭借超声能量，因为接触元件16通过超声焊接工艺而固定到金属层26或相应地延深部40，接触元件16和金属层26连接到彼此。
由于提供延深部40，接触元件16牢固地保持在适当位置，从而导致接触元件16被固定在预计位置处。
本发明的另外的实施例在图3中示出。根据图3，延深部40至少部分由斜切的边缘或相应地边48环绕。可根据期望的应用选择斜切的量或程度。然而，为了确保接触元件16不滑出延深部40，斜切相对于水平面在≥45°的范围中，这是最优选的，其中该水平面由金属层26的平面限定。此外，接触元件16在一个或多个侧面也包括斜切的边缘50，这可是有利的。优选地，这些斜切的边缘50适应于斜切的边48，使得接触元件16在金属层26上或相应地在延深部40处的装配被改进。
不是本发明的一部分的实施例在图4中示出。根据图4，固定部件38包括在金属层26上形成的至少一个高部52。优选地，接触元件16完全由高部52环绕。因此，根据该实施例，固定部件38完全在金属层26上形成。这具有金属层26不会被延深部40所削弱并且从而尤其有利于非常薄的金属层26的优势。采用示范性方式，高部52可由形成接触元件16的止动器的至少一个特别扁的线接合来形成。在该情况下，非常容易制备固定部件38。高部例如可在接触元件的预计位置的一个或若干侧面形成。另外，在直接定位在接触元件的位置的位点上形成高部是可能的。在该情况下，接触元件包括用于与高部配合或相应地交互的配合部件，这是最优选的。该配合部件在该情况下可实现为接触元件中的延深部（其在它的大小和几何形状方面适应于高部）或相应地固定部件。接触元件16可包括一个或多个斜切的边缘50和/或一个或多个矩形边缘54。另外，高部52可包括斜切的边缘，用于便于将接触元件16放置在固定部件处。
根据本发明的另外的实施例在图5中示出。该实施例对应于根据图3的实施例。然而，根据图5的实施例包括中间层56设置在金属层26与衬底24之间这一另外的特征。该中间层56可以是任何适合的层，特别是金属层，并且它例如可作为金属板而提供。该中间层56可通过焊料58或低温接合而附连到金属层26。此外，它可通过任何适合的方式附连到衬底24，例如通过沉积工艺。根据图5，中间层56可形成为衬底24上的金属化，而包括延深部40的金属层26可形成为金属板。
根据图6的实施例可再次包括类似上文描述的中间层56。另外，根据图6，金属层26包括金属层26中的延深部40。除所述延深部40外，接触元件16包括配合部件，特别在它的第一臂34处，用于与延深部40配合。具体地，根据图6，接触元件16包括高部60，优选地在第一臂34处。高部60和延深部40优选地关于大小和几何形状而适应于彼此。因此，接触元件16的高部60充当用于与延深部40配合的固定部件。这允许接触元件16在延深部40处的装配变得更紧密。
不是本发明的一部分的另外的实施例在图7中示出。根据图7的实施例对应于图6的实施例，所不同的是金属层26包括高部62作为固定部件38，而接触元件16，特别是接触元件16的第一臂34包括与固定部件38交互的延深部64。再次地，固定部件38（即，高部62）和延深部64优选地关于大小和几何形状而适应于彼此。
必须注意，类似上文描述的特征不限于描述的实施例。特别地，固定部件38的设置可与中间层56组合以及不与中间层56组合。此外，固定部件38的不同设置的组合是可能的而不脱离本发明本身。
尽管已经在图和前面的描述中详细说明和描述本发明，这样的说明和描述要视为说明性或示范性而非限制性的；本发明不限于公开的实施例。对公开的实施例的其他变化形式可以被本领域内技术人员理解和实现并且从对附图、公开和附上的权利要求的学习而实践要求保护的本发明。在权利要求中，单词“包括”不排除其他要素或步骤，并且不定冠词“一”不排除多数。某些措施在互不相同的从属权利要求中记载，仅这样的事实并不指示无法有利地使用这些措施的组合。权利要求中的任何标号不应该解释为限制范围。
。

Claims (7)

1.一种半导体模块（10），其包括衬底（24），特别地由陶瓷绝缘体形成，以及至少一个金属层（26），特别地在所述衬底（24）上形成，
其中所述金属层（26）包括延深部（40），用于放置和固定接触元件（16），所述接触元件（16）至少部分是“L”型并且包括用于将所述接触元件（16）固定在所述延深部（40）处的第一臂（34）以及用于互连所述接触元件（16）的第二臂（36），
其中所述延深部（40）具有大于所述接触元件（16）的水平尺寸约≤0.5mm的水平尺寸。
2.如权利要求1所述的半导体模块，其中所述半导体模块是功率半导体模块，其包括功率半导体器件，例如二极管、晶体管和/或集成电路。
3.如权利要求1或2所述的功率半导体模块，其中所述接触元件（16）包括配合部件，特别地在它的第一臂（34）处，用于与所述延深部（40）配合。
4.如权利要求1至3中任一项所述的半导体模块，其中所述延深部（40）具有≥100μm的深度。
5.如权利要求1至4中任一项所述的半导体模块，其中所述延深部（40）至少部分由斜切边（48）环绕。
6.如权利要求1至5中任一项所述的半导体模块，其中中间层（56）设置在所述金属层（26）与所述衬底（24）之间。
7.一种制造半导体模块（10）的方法，其包括使接触元件（16）与金属层（26）接触的步骤，所述接触元件至少部分是“L”型并且包括用于将所述接触元件（16）固定在所述延深部（40）处的第一臂（34）以及用于互连所述接触元件（16）的第二臂（36），其中所述金属层（26）包括延深部（40），用于放置接触元件（16），其中所述延深部（40）具有大于所述接触元件（16）的水平尺寸约≤0.5mm的水平尺寸，所述方法进一步包括以下步骤：
－在所述延深部处将所述接触元件（16）按压到所述金属层（26）上，
－将超声能量施加到所述接触元件（16）与所述金属层（26）的界面用于将所述接触元件（16）焊接到所述金属层（26）上。
CN2011800497358A 2010-10-13 2011-10-07 半导体模块和制造半导体模块的方法 Pending CN103155131A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP10187399 2010-10-13
EP10187399.0 2010-10-13
PCT/EP2011/067558 WO2012049087A2 (en) 2010-10-13 2011-10-07 Semiconductor module and method of manufacturing a semiconductor module

Publications (1)

Publication Number Publication Date
CN103155131A true CN103155131A (zh) 2013-06-12

Family

ID=43568265

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011800497358A Pending CN103155131A (zh) 2010-10-13 2011-10-07 半导体模块和制造半导体模块的方法

Country Status (6)

Country Link
US (1) US20130221504A1 (zh)
EP (1) EP2628173A2 (zh)
JP (1) JP2013539919A (zh)
KR (1) KR20130051498A (zh)
CN (1) CN103155131A (zh)
WO (1) WO2012049087A2 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738138A (zh) * 2012-06-05 2012-10-17 嘉兴斯达微电子有限公司 一种针对电动汽车应用的igbt功率模块
JP5755601B2 (ja) * 2012-06-07 2015-07-29 株式会社日立製作所 パワーモジュールおよびその製造方法
JP6406983B2 (ja) 2014-11-12 2018-10-17 三菱電機株式会社 半導体装置およびその製造方法
CN110178219B (zh) * 2017-01-17 2022-11-22 三菱电机株式会社 半导体装置以及电力变换装置
JP7181217B2 (ja) * 2017-04-04 2022-11-30 クリック アンド ソッファ インダストリーズ、インク． 超音波溶接システムおよびその使用方法
JP7026451B2 (ja) * 2017-05-11 2022-02-28 三菱電機株式会社 パワー半導体モジュール及びその製造方法並びに電力変換装置
JP6937729B2 (ja) * 2018-09-06 2021-09-22 三菱電機株式会社 半導体装置、電力変換装置および半導体装置の製造方法
EP3918886A4 (en) * 2019-01-29 2022-11-02 Butterfly Network, Inc. PACKAGING STRUCTURES AND METHODS FOR ULTRASONIC ON-CHIP DEVICES

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0844664A2 (en) * 1996-11-25 1998-05-27 Texas Instruments Incorporated A bond pad for an integrated circuit
US5891756A (en) * 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
US6110816A (en) * 1999-03-05 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for improving bondability for deep-submicron integrated circuit package
JP2001308123A (ja) * 2000-04-19 2001-11-02 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP2002261116A (ja) * 2000-12-25 2002-09-13 Hitachi Ltd 半導体装置およびその製造方法ならびに半導体製造装置
US20050150933A1 (en) * 2003-07-01 2005-07-14 Stmicroelectronics, Inc. System and method for increasing the strength of a bond made by a small diameter wire in ball bonding
EP1711040A1 (en) * 2005-03-30 2006-10-11 Toyota Jidosha Kabushiki Kaisha Circuit device and manufacturing method thereof
DE102005019574A1 (de) * 2005-04-27 2006-11-09 Infineon Technologies Ag Kontaktierungsanordnung für ein Halbleiterbauelement
US20070063318A1 (en) * 2005-09-14 2007-03-22 Infineon Technologies Ag Semiconductor device for bonding connection
US20090098687A1 (en) * 2007-10-10 2009-04-16 Joze Eura Antol Integrated circuit package including wire bonds
JP2010040615A (ja) * 2008-08-01 2010-02-18 Hitachi Ltd 半導体装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4576900A (en) * 1981-10-09 1986-03-18 Amdahl Corporation Integrated circuit multilevel interconnect system and method
CA2135241C (en) * 1993-12-17 1998-08-04 Mohi Sobhani Cavity and bump interconnection structure for electronic packages
US7071089B1 (en) * 2000-10-13 2006-07-04 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with a carved bumped terminal
JP4635564B2 (ja) * 2004-11-04 2011-02-23 富士電機システムズ株式会社 半導体装置
JP4674522B2 (ja) * 2004-11-11 2011-04-20 株式会社デンソー 半導体装置
DE102005045100A1 (de) 2005-09-21 2007-03-29 Infineon Technologies Ag Verfahren zum Herstellen eines Leistungshalbleitermoduls
JP5331610B2 (ja) * 2008-12-03 2013-10-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0844664A2 (en) * 1996-11-25 1998-05-27 Texas Instruments Incorporated A bond pad for an integrated circuit
US5891756A (en) * 1997-06-27 1999-04-06 Delco Electronics Corporation Process for converting a wire bond pad to a flip chip solder bump pad and pad formed thereby
US6110816A (en) * 1999-03-05 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for improving bondability for deep-submicron integrated circuit package
JP2001308123A (ja) * 2000-04-19 2001-11-02 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP2002261116A (ja) * 2000-12-25 2002-09-13 Hitachi Ltd 半導体装置およびその製造方法ならびに半導体製造装置
US20050150933A1 (en) * 2003-07-01 2005-07-14 Stmicroelectronics, Inc. System and method for increasing the strength of a bond made by a small diameter wire in ball bonding
EP1711040A1 (en) * 2005-03-30 2006-10-11 Toyota Jidosha Kabushiki Kaisha Circuit device and manufacturing method thereof
DE102005019574A1 (de) * 2005-04-27 2006-11-09 Infineon Technologies Ag Kontaktierungsanordnung für ein Halbleiterbauelement
US20070063318A1 (en) * 2005-09-14 2007-03-22 Infineon Technologies Ag Semiconductor device for bonding connection
US20090098687A1 (en) * 2007-10-10 2009-04-16 Joze Eura Antol Integrated circuit package including wire bonds
JP2010040615A (ja) * 2008-08-01 2010-02-18 Hitachi Ltd 半導体装置

Also Published As

Publication number Publication date
JP2013539919A (ja) 2013-10-28
KR20130051498A (ko) 2013-05-20
WO2012049087A2 (en) 2012-04-19
WO2012049087A3 (en) 2012-06-21
EP2628173A2 (en) 2013-08-21
US20130221504A1 (en) 2013-08-29

Similar Documents

Publication Publication Date Title
CN103155131A (zh) 半导体模块和制造半导体模块的方法
US9209114B2 (en) Power module package with a fastening unit including a non-conductive portion
CN108352355B (zh) 具有预模制双引线框的半导体系统
CN103035542B (zh) 用于生产功率半导体设置的方法
JP4950280B2 (ja) 高電力密度装置用、特にｉｇｂｔおよびダイオード用の低インダクタンスのボンドワイヤレス共同パッケージ
US9202798B2 (en) Power module package and method for manufacturing the same
CN107210279B (zh) 电力用半导体装置
CN107615464B (zh) 电力用半导体装置的制造方法以及电力用半导体装置
EP2273545A1 (en) Method for insertion bonding and device thus obtained
US20140167237A1 (en) Power module package
JP3573133B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2011515842A (ja) 高密度インターコネクトのためのシリコンパッチ含有マイクロエレクトロニクスパッケージおよびその製造方法
JP2003243436A (ja) バンプの形成方法、バンプ付き半導体素子及びその製造方法、半導体装置及びその製造方法、回路基板並びに電子機器
CN103035601A (zh) 在烧结银层上包括扩散焊接层的半导体器件
CN101924046A (zh) 在半导体器件中形成引线键合的方法
US20090243079A1 (en) Semiconductor device package
US20150091160A1 (en) 3d device packaging using through-substrate posts
CN207381382U (zh) 电力电子模块和电力电子元器件封装基板
EP2903024A1 (en) Contact element, power semiconductor module and method of fabricating same
JP5233853B2 (ja) 半導体装置
US20100181675A1 (en) Semiconductor package with wedge bonded chip
JP2015026791A (ja) 半導体装置及びリードフレーム
US20120075812A1 (en) Multi-chip package
DK177868B1 (en) Contact mechansim for electrical substrates
JP5884625B2 (ja) 半導体デバイス

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20130612