CN103107150B - 用于半导体器件的中介层及其制造方法 - Google Patents
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- CN103107150B CN103107150B CN201210022531.1A CN201210022531A CN103107150B CN 103107150 B CN103107150 B CN 103107150B CN 201210022531 A CN201210022531 A CN 201210022531A CN 103107150 B CN103107150 B CN 103107150B
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Abstract
本发明公开了用于半导体器件的中介层及其制造方法。在一个实施例中,一种中介层包括:衬底;在衬底上设置的接触焊盘;以及位于衬底中的连接至接触焊盘的第一通孔;连接至第一通孔的第一熔丝;位于衬底中的连接至接触焊盘的第二通孔;以及连接至第二通孔的第二熔丝。
Description
技术领域
本发明涉及半导体器件制造,更具体而言,涉及用于半导体器件的中介层及其制造方法。
背景技术
半导体器件用于各种电子应用,作为实例,比如个人计算机、手机、数码相机、以及其他电子设备。半导体工业通过持续减小集成电路(IC)的最小部件尺寸,从而能够将更多元件集成到给定面积上,进而持续改进各种电子元件(例如,晶体管、二极管、电阻器、电容器等等)的集成密度。在一些应用中,这些更小的电子元件也需要比过去的封装件更小的应用更少面积的封装件。
已开发出来的一种类型的较小封装件是三维(3D)IC,在这种封装件中,将两个管芯或者IC接合在一起,并且在管芯和中介层上的接触焊盘之间形成电连接。一些3DIC利用硅通孔从中介层的一侧至另一侧形成连接。
熔丝是有时在半导体器件上形成的器件,可以利用激光通过从半导体器件的顶部或者底部将激光束打在熔丝上,对熔丝进行编程。例如,可以使用熔丝通过连接或者断开冗余电路或者存储器单元来改变IC,从而修复IC或者增加晶圆上的可用IC的数量。
发明内容
一方面,本发明提供了一种中介层,包括:衬底;接触焊盘,所述接触焊盘被设置在所述衬底上;第一通孔,所述第一通孔位于所述衬底中,连接至所述接触焊盘;第一熔丝,所述第一熔丝连接至所述第一通孔;第二通孔,所述第二通孔位于所述衬底中,连接至所述接触焊盘;以及第二熔丝,所述第二熔丝连接至所述第二通孔。
根据上面所述的中介层,其中,所述第一熔丝和所述第二熔丝被设置在再分布层(RDL)中。
根据上面所述的中介层还包括:连接至所述接触焊盘的至少一个第三通孔;以及至少一个第三熔丝,其中,所述至少一个第三熔丝中的每一个都连接至所述至少一个第三通孔之一。
根据上面所述的中介层还包括:连接至所述第一熔丝的第一接合焊盘;以及连接至所述第二熔丝的第二接合焊盘。
根据上面所述的中介层还包括:连接至所述第一接合焊盘的第一凸块;以及连接至所述第二接合焊盘的第二凸块。
根据上面所述的中介层还包括:连接至所述接触焊盘的第三凸块。
根据上面所述的中介层,其中,所述第三凸块大于所述第一凸块和所述第二凸块。
根据上面所述的中介层,其中,所述第一凸块、所述第二凸块、或者所述第三凸块包含焊料。
另一方面,本发明还提供了一种用于封装半导体器件的中介层,其包括:衬底,所述衬底具有第一侧和与所述第一侧相对的第二侧;多个通孔,所述多个通孔被设置在邻近所述第一侧的所述衬底中;互连结构,所述互连结构被设置在邻近所述第二侧的所述衬底中,所述互连结构包括多个熔丝;接触焊盘,所述接触焊盘连接至邻近所述第一侧的所述多个通孔中的至少两个,所述多个通孔中的至少两个中的每一个连接至所述多个熔丝之一;以及凸块,所述凸块连接至所述接触焊盘。
根据上面所述的中介层,其中,所述衬底基本上不具有集成电路器件。
根据上面所述的中介层,其中,所述中介层包括三维集成电路(3DIC)中介层。
根据上面所述的中介层,其中,在使用所述中介层封装集成电路之前或者之后,能够利用激光对所述多个熔丝进行编程。
根据上面所述的中介层,其中,所述凸块包括第一凸块,还包括:连接至所述互连结构的凸块下金属化(UBM)结构;以及连接至所述UBM结构的多个第二凸块,并且其中,部分所述UBM结构连接至与所述多个通孔中的至少两个相连接的所述多个熔丝。
根据上面所述的中介层,其中,所述多个第二凸块能够连接至集成电路管芯。
根据上面所述的中介层,其中,所述第一凸块能够连接至衬底、印刷电路板(PCB)、或者集成电路管芯。
本发明还提供了一种使用根据本发明所述的用于封装半导体器件的中介层封装的半导体器件,其中,集成电路管芯的多个接触件电连接至所述多个第二凸块。
根据上面所述的封装半导体器件还包括:在所述集成电路管芯下方设置的底部填充材料。
根据上面所述的封装半导体器件还包括:在所述集成电路管芯和所述中介层的上方设置的模塑料。
另一方面,本发明还提供了一种制造用于封装半导体器件的中介层的方法,所述方法包括:提供衬底;在所述衬底中形成多个通孔;在所述衬底上方形成再分布层(RDL),在所述RDL中形成有多个熔丝,将每个熔丝连接至所述多个通孔之一;将接触焊盘连接至与所述熔丝相连接的所述多个通孔中的至少两个;将第一凸块连接至所述接触焊盘;以及将第二凸块连接至所述多个熔丝中的每一个。
根据上面所述的方法还包括:使用在所述衬底设置的至少一条导线、至少一个通孔、或者其组合将每个熔丝连接至所述多个通孔之一。
附图说明
为了更全面地理解本发明及其优点,现在结合附图进行的以下描述作为参考,其中:
图1示出了根据本发明的实施例的包括多个连接至单个接触焊盘的熔丝的中介层的横截面图;
图2是包括图1中示出的中介层的熔丝的导电段的俯视图;
图3是包括连接至中介层上的接触焊盘和接合焊盘的凸块的图1的中介层的横截面图;
图4是包括图3中示出的中介层的封装半导体器件的横截面图;
图5是示出了根据实施例的制造中介层的方法的流程图;
图6示出了根据本发明的另一个实施例的中介层的横截面图;
图7是图6中示出的中介层的一部分的仰视图;
图8是图6中示出的中介层的一部分的俯视图;
图9示出了利用激光对其中一个熔丝进行编程之后的图6中示出的中介层的横截面图;
图10是包括图9中示出的经过编程的熔丝的导电段的俯视图;
图11和图12分别示出了在编程之前和之后的本发明的实施例的熔丝的示意图。
除非另有说明,否则在不同的附图中,对应的数字和符号通常指的是对应的部件。绘制附图,用于清晰地示出各个实施例的相关方面,并且,对这些附图不必必须按比例绘制。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境中实现的可应用的概念。所论述的具体实施例仅仅是制造和使用本发明的说明性具体方式,而不用于限制本发明的范围。
本发明的实施例涉及利用中介层作为元件用于半导体器件的封装件,比如3DIC。在本文中,将描述包括连接至中介层的单个接触件或者凸块的多个熔丝的中介层的结构及其形成方法。
首先,参考图1,示出了根据本发明的实施例的包括多个熔丝120a和120b的中介层100的横截面图。中介层100包括衬底102,以及在该衬底102上设置的接触焊盘112。衬底102中的第一通孔108a和第二通孔108b连接至接触焊盘112。第一熔丝120a连接至第一通孔108a,以及第二熔丝120b连接至第二通孔108b。图1(以及图3、图6、和图7)中只示出了一个接触件112;然而,根据本发明的实施例,可以在衬底102的表面上方形成多个接触件112。例如,根据集成电路管芯130(未在图1中示出;见图4)的应用和尺寸,可以在衬底102的整个表面上形成数十个或者数百个接触件112、通孔108a和108b、以及熔丝120a和120b。
再次参考图1,为了制造中介层100,提供衬底102。衬底102可以由半导体材料(比如硅、硅锗、碳化硅、砷化镓、或者其他常用的半导体材料)形成。可选地,衬底102可以由介电材料形成。在一些实施例中,衬底102基本上不具有集成电路器件(包括有源器件,比如晶体管和二极管)。另外,在一些实施例中,衬底102可以包括或者可以不包括无源器件,比如电容器、电阻器、电感器、和/或变容二极管等等。
在衬底102上形成多个衬底通孔(TSV)108a和108b。如所示,TSV108a和108b延伸穿过整个衬底102。TSV108a和108b是导电的,并且提供了从中介层衬底102的第一侧104至与该第一侧104相对的第二侧106的连接。例如,TSV包含诸如金属的导电材料、诸如硅的半导体材料、或者其组合或者多层结构。在本文中,TSV108a和108b还被称为通孔108a和108b。
在邻近衬底102的第二侧106的衬底102上方形成互连结构110。互连结构110包括一层或者多层绝缘材料层122、以及在该绝缘材料层122中形成的导线160a、160b、和160c以及通孔162a、162b、162c、164a、和164b(未在图1中示出;见图6,将在本文中进行进一步的描述)。作为实例,可以采用减蚀刻(subtractiveetching)、直接蚀刻、镶嵌光刻技术、和/或其组合形成互连结构110的各层。例如,互连结构110可以包括再分布层(RDL),并且在本文中还可以将该互连结构110称为再分布层(RDL)。将通孔108a和108b中的至少一些电连接至RDL110。在一些实施例中,RDL110可以包括扇出区域(fan-outregion,未示出),该扇出区域用于扇出集成电路管芯130(见图4)与衬底102的第一侧104上的较大足迹(foorprint)的外部连接。
RDL110中形成有多个熔丝120a和120b。如图1中和图2中以俯视图所示,熔丝120a和120b可以分别是导电段114a和114b的一部分。在一些实施例中,导电段114a和114b可以包含铝或者铝合金。可选地,例如,导电段114a和114b可以包含适合用作熔丝120a和120b材料的其他金属和/或材料。导电段114a包括在每个端部上设置的连接区域116a/118a,以及导电段114b包括在每个端部上设置的连接区域116b/118b。在导电段114a的连接区域116a和118a之间设置熔丝120a,以及在导电段114b的连接区域116b和118b之间设置熔丝120b。在一些实施例中,例如,可以在RDL110的上层或者顶层中形成导电段114a和114b。可选地,在未示出的其他实施例中,可以在RDL110的下层中形成导电段114a和114b。
在俯视图中,熔丝120a和120b具有尺寸d1,尺寸d1包括约30μm的宽度,但是可选地,熔丝120a和120b可以具有其他尺寸。例如,在一些实施例中,尺寸d1可以包括中介层100的最小部件尺寸。连接区域116a/118a和116b/118b的宽度可以大于熔丝120a和120b的宽度d1。作为实例,连接区域116a/118a和116b/118b的宽度可以是熔丝120a和120b的宽度尺寸d1的大约4倍至5倍。可选地,在一些实施例中,连接区域116a/118a和116b/118b可以比尺寸d1的大约4倍至5倍更大或者更小。例如,连接区域116a和116b可以分别包括用于与通孔10ga和108b形成连接的区域,因此,连接区域116a和116b的尺寸可以分别基本上等于或者大于通孔10ga和108b的宽度。在一些实施例中,连接区域118a和118b可以包括用于与集成电路管芯130(见图4)形成电连接(例如,分别通过凸块124a和124b(见图3))的区域。例如,在一些实施例中,连接区域118a和118b可以包括接合焊盘。
在第一侧104上的衬底100上设置接触焊盘112。作为实例,可以使用减蚀刻、直接蚀刻、和/或镶嵌光刻技术形成接触焊盘112。如图3中所示,接触焊盘112可以包含适合于与凸块126相连接的金属。将衬底102中的第一通孔10ga电连接至接触焊盘112。例如通过导电段114a的连接区域116a将第一熔丝120a电连接至第一通孔10ga。将衬底102中的第二通孔108b电连接至接触焊盘112。例如通过导电段114b的连接区域116b将第二熔丝120b电连接至第二通孔108b。
在形成RDL110和接触件112之后,可以将凸块124a连接至导电段114a的连接区域118a,以及将凸块124b连接至导电段114b的连接区域118b,并且可以在接触焊盘112上形成凸块126,如图3中以横截面图所示。凸块124a、124b、和126可以包括焊料凸块,比如共晶焊料凸块。可选地,凸块124a、124b、和126可以包括铜凸块或者由金、银、镍、钨、铝、其他金属、和/或其合金形成的其他金属凸块。例如,凸块126可以包括在诸如倒装芯片的半导体互连技术中所用的可控塌陷芯片连接(ControlledCollapseChipConnection,C4)凸块。在一些实施例中,凸块126大于凸块124a和124b。如所示,凸块124a和124b可以从第二侧106上的互连结构或者RDL110的表面凸出来,以及凸块126可以从第一侧104上的衬底102凸出来。例如,在形成凸块124a、124b、和/或126之前,可以在第一侧104和/或第二侧106的上方形成焊料掩模(未示出),以免凸块材料形成在不期望的区域中。
例如,在一些实施例中,凸块124a和124b可以包括微凸块。凸块124a和124b每一个都可以包括任选的金属嵌钉(metalstud)以及在该金属嵌钉上方形成的焊料,该金属嵌钉可以包含铜、铜合金、或者其他金属。凸块124a和124b可以可选地包含其他材料。凸块124a和124b的金属嵌钉可以由任何适当的导电材料(包括Cu、Ni、Pt、Al、其组合)形成,并且可以通过许多适当技术(包括PVD、CVD、电化学沉积(ECD)、分子束外延(MBE)、原子层沉积(ALD)、和电镀等等)形成。可以在凸块124a和124b的金属嵌钉和焊料之间形成任选的导电保护层(conductivecaplayer)(同样未示出)。例如,在其中金属嵌钉是由铜形成的实施例中,可以期望由镍形成导电保护层。其他材料(比如Pt、Au、Ag、或其组合等等)也可以用于凸块124a和124b的任选的导电保护层。
例如,在本文中,根据在具体的凸块124a、124b、和126的片段或者描述中、以及权利要求书中的引入顺序,也可以将凸块124a、124b、和126(以及图7中示出的凸块124c)称为第一凸块、第二凸块、和/或第三凸块。
凸块124a、124b、和126可以形成在中介层100的周边区域中,并且可以在该周边区域中以一行或者多行进行布置。作为实例,凸块124a、124b、和126可以沿着中介层100的边缘或者角部分别在中介层100的每侧上以三行进行布置。可选地,凸块124a、124b、和126可以以其他图案进行布置,并且可以被设置在其他位置中。例如,其他实施例可以包括凸块124a、124b、和126沿着中介层100的内部设置的情况。给出凸块124a、124b、和126的布置仅仅是为了说明目的,并且第一侧104和第二侧106上的凸块124a、124b、和126的特定位置和图案可以改变,并且可以包括例如凸块阵列、中介层100的中央区域中的凸块线、或者交错凸块(staggeredbumps)。
本发明的实施例包括利用本文中所描述的新式中介层100进行封装的封装半导体器件。图4是包括图3中示出的中介层100的封装半导体器件136的横截面图。将集成电路管芯130的接触件131电连接至中介层100的凸块124(其包括图3中示出的凸块124a和124b)。例如,可以将管芯130设置在中介层100上,并且可以通过实施焊料回流工艺将管芯130接合至中介层100,并且形成电连接。焊料回流工艺将凸块124的焊料回流,并且将管芯130电连接至中介层100。在焊料回流工艺之前,可以使用粘合剂将管芯130接合至中介层100,或者,焊料也可以起到机械接合至中介层100的作用。作为实例,可以采用焊料工艺、焊料回流工艺、和/或热压接合将凸块124连接至集成电路管芯130的接触件131。可选地,可以使用其他方法将集成电路管芯130电连接至中介层100。注意到,例如,在一些实施例中,可以在将集成电路管芯130接合至中介层100之后形成凸块126。
如所示,可以任选地在集成电路管芯130下方设置底部填充材料132。底部填充材料132可以包括例如填充剂、环氧树脂、硬化剂、或者多层或者其组合,然而,可选地,该底部填充材料132可以包括其他材料。例如,底部填充材料132可以包含具有足以在集成电路管芯130下方至少部分地流动,以及在一些实施例中完全流动的粘性的材料。
任选的模塑料(moldingcompound)134(在图4中以透视图(phantom)示出)可以任选地设置在集成电路管芯130和中介层100的上方。模塑料134可以包括例如环氧树脂、填充剂、有机材料、或者多层或者其组合,然而,模塑料134还可以包括其他材料。例如,模塑料134可以在集成电路管芯130的顶面上方延伸大约10μm或者更多。在一些实施例中,如果集成电路管芯130较大,则可以使用较大量的模塑料134,从而为封装件提供更多的稳健性。
在划片槽(scribeline)或者切割线(singlulationline)处将封装半导体器件136单分出来,使得封装半导体器件136相互分隔开。然后,可以使用凸块126将封装半导体器件136连接至外部电路(未示出)。作为实例,可以将凸块126连接至衬底、印刷电路板(PCB)、另一集成电路管芯、或者其他应用装置(未示出)。作为一个实例,可以将封装半导体器件136设置在有机衬底或者具有与凸块126相匹配的焊盘布局的其他外部电路上,并且可以对凸块126的焊料进行回流,从而完成互连。
本发明的实施例还包括形成中介层100的方法。例如,图5是示出了根据实施例的制造中介层100的方法的流程图140。该方法包括:提供衬底102(步骤142),以及在衬底102中形成多个通孔108a和108b(步骤144)。在衬底102上方形成再分布层(RDL)110(步骤146),在该RDL110中形成有多个熔丝120a和120b,每个熔丝120a和120b都连接至通孔108a和108b之一。该方法包括:将接触焊盘112连接至与熔丝120a和120b相连接的多个通孔108a和108b中的至少两个(步骤148)。将第一凸块126连接至接触焊盘126(步骤152),并且将第二凸块124a和124b连接至多个熔丝120a和120b中的每一个(步骤150)。注意到,在一些实施例中,流程图140中的步骤146和148、以及步骤150和152的顺序不需要必然以任何顺序或者以流程图140中所示出的顺序来实施。
根据实施例的形成中介层100的方法还可以任选地包括:使用设置在衬底102中的导线160a、160b、和160c中的至少一条、通孔162a、162b、164a、和164b中的至少一个、或者其组合,将每个熔丝120a和120b连接至多个通孔108a和108b之一,在本文中,将参考图6对上述内容进行进一步描述。
根据其他实施例,还可以在中介层100的衬底102上方形成其他材料层。例如,图6示出了包括有多层任选的其他材料层的根据本发明的另一实施例的中介层100的横截面图。使用相似的标号来描述各个元件,并且为了避免重复,在本文中不再对每个元件都进行描述。
在填充衬底100中的孔以形成通孔108a和108b之前,在衬底100上方形成绝缘材料层122a。绝缘材料层122b包括多条导线160a、160b、和160c以及连接至导线160a、160b、和160c的通孔162a和162b,其中,通孔162a和162b被设置在导线160a层、160b层、和160c层中的每层之间。
例如,导线160a可以形成在M1金属化层中,通孔162a可以形成在V1金属化层中,导线160b可以形成在M2金属化层中,通孔162b可以形成在V2金属化层中,以及导线160c可以形成在M3金属化层中。可选地,导线160a、160b、和160c以及通孔162a和162b可以形成在中介层100的其他金属化层中。通孔164a形成在绝缘材料层122c内的导电段114a的连接区域116a下方,以及通孔164b形成在绝缘材料层122c内的导电段114b的连接区域116b下方。凸块下金属化(under-ballmetallization,UBM)结构166可以形成在导电段114a和114b以及绝缘材料层122c的上方。UBM166包括包含有金属的导线168,该导线168形成在部分绝缘材料层122d之内和上方。UBM166是任选的,并且便于形成凸块124a和124b。
作为实例,绝缘材料层122a、122b、122c、和122d可以包含二氧化硅、未掺杂的硅玻璃(USG)氧化物、或者其他绝缘体,并且导线160a、160b、160c、和168以及通孔162a、和162b可以包含铜、铜合金、或者其他导体。作为实例,通孔164a和164b以及导电段114a和114b可以包含铝、铝合金、或者其他金属。可以在绝缘材料层122a、122b、122c、和122d中的每层之间形成任选的蚀刻停止层(未示出)。蚀刻停止层可以包含SiC、SiN、或者其他绝缘材料。
图7是图6中示出的中介层100的一部分的仰视图。其中,图7是沿着图6中的A-A线截取而获得的。在透视图中可以看到位于接触焊盘112上形成的凸块126之上的形成在中介层100上的另一位置的第三凸块124c。第三凸块124c还连接至第三熔丝,该第三熔丝是第三导电段的一部分(未在附图中示出)。同样,根据实施例,可以使用额外的通孔108、导线160和168、以及通孔162和164将多于三个的凸块和熔丝(例如,四个或更多个凸块126和熔丝120)电连接在凸块126之上(未在附图中示出)。例如,通孔108可以直接设置在凸块126的下方或者设置在邻近凸块126的位置上,以及熔丝120和导电段114可以沿着远离布局中的凸块126的方向伸展开。图7还示出了仰视图中的用于凸块126的接触焊盘112的可能的形状。图7还示出了仰视图中的用于凸块126的接触焊盘112的可能的形状。作为实例,接触焊盘112的形状可以是梯形、正方形、矩形、圆形、或者其他形状。
注意到,根据一些实施例,本文所描述的多个凸块124a、124b、和124c可以连接至集成电路管芯130的不同的电连接件,或者可选地,多个凸块124a、124b、和124c可以连接至集成电路管芯130的同一电连接件,从而为单个凸块126提供冗余连接件。
图8是图6中示出的中介层100的一部分的俯视图,示出了导电段114b。其中,图8是沿着图6中的B-B线截取而获得的。在图8中以透视图示出了设置在导电段114b下方的通孔164b以及设置在导电段114b上方的凸块124b。
接下来,参考图9,在封装半导体器件136正常运行期间,通过在凸块126和凸块124a、124b、和/或124c之间施加电压,可以施加通过中介层100的电流。作为凸块124a的实例,电流从凸块124a流经包括熔丝120a的导电段114a、通孔164a、导线160c、通孔162b、导线160b、通孔162a、和导线160a,然后流经通孔108a,流经接触焊盘112,到达凸块126。通过将激光束、激光能、激光脉冲、或者其他高能形式直接施加至预定的熔丝120a、120b、或者120c,对本发明的实施例的熔丝120a、120b、或者120c进行编程或者“熔断(blown)”。
例如,图9示出了在利用激光对熔丝120b’之一进行编程之后的图6中示出的中介层100的横截面图。射向熔丝120b’的激光能170使得在薄熔丝120b’中形成断裂172,并阻止电流从相关凸块124b流向凸块126。图10是包括图9中所示出的经过编程的熔丝120b’的导电段114b的俯视图。其中,图10是沿着图9中的C-C线截取而获得的。图11示出了在120处进行编程之前的本发明的实施例的熔丝120的示意图,图12示出了在120’处进行编程之后的本发明的实施例的熔丝120’的示意图。
本发明的实施例包括中介层100、本文所描述的形成中介层100的方法、以及包括中介层100的封装半导体器件136。
本发明的实施例的优点包括提供了新式中介层100。在中介层100的制造工艺流程中,熔丝120a、120b、和120c是很容易实现的。在封装半导体器件之前或者之后,可以对熔丝120a、120b、或者120c进行熔断或者编程。例如,使用激光或者其他高能脉冲能够很容易对熔丝120a、120b、或者120c进行编程。熔丝120a、120b、或者120c具有多种用途,并且为中介层100提供了多条电流路径。
在中介层100的制造领域和封装领域中,容许快速而有效地提高熔断熔丝120a、120b、或者120c的能力,而不会产生附加成本。通过对熔丝120a、120b、或者120c进行编程或者熔断,可以将中介层100和/或使用中介层100封装的集成电路管芯130的无功能的部分或者不需要的部分断开。可以对熔丝120a、120b、或者120c进行编程,并且将熔丝120a、120b、或者120c用于电路修复,以将即将损坏或者已经损坏的电路替换为在衬底102上方或者管芯130上的其他位置形成的备用、冗余的电路或者引线(未在附图中示出)。作为实例,还可以对熔丝120a、120b、或者120c进行编程,以增加中介层100的可用部分的数量。优选地,可以分别对通过通孔108a、108b、和/或108c连接至凸块126的多个熔丝120a、120b、和120c中的仅一个、两个或更多个、或者全部进行编程或者熔断,从而容许为IC设计者和终端用户提供很大的灵活性。
本文所描述的中介层100可以用于封装3DIC和其他类型的半导体封装件。作为其他实例,在一些实施例中,中介层100可以用于穿透中介层堆叠(through-interposerstacking,TIS),并且可以优选利用凸块126(包括C4凸块)和凸块124a、124b、124c(包括微凸块)。在一些应用中,为了解决封装领域所存在的问题,可以将多个通孔108a、108b、和108c以及熔丝120a、120b、和120c连接至设计中特别针对的薄弱区域中的单个凸块126。
根据本发明的一个实施例,一种中介层包括:衬底;设置在衬底上的接触焊盘;以及位于衬底中的连接至接触焊盘的第一通孔;连接至第一通孔的第一熔丝;位于衬底中的连接至接触焊盘的第二通孔;以及连接至第二通孔的第二熔丝。
根据另一个实施例,一种用于封装半导体器件的中介层包括:具有第一侧和与该第一侧相对的第二侧的衬底;在邻近第一侧的衬底中设置的多个通孔,以及在邻近第二侧的衬底中设置的互连结构,该互连结构包括多个熔丝;连接至邻近第一侧的多个通孔中的至少两个的接触焊盘,多个通孔中的至少两个中的每一个连接至多个熔丝之一;以及连接至接触焊盘的凸块。
根据又一个实施例,一种制造用于封装半导体器件的中介层的方法包括:提供衬底;以及在衬底中形成多个通孔;在衬底上方形成再分布层(RDL),在RDL中形成有多个熔丝,每个熔丝连接至多个通孔之一。该方法还包括:将接触焊盘连接至与熔丝相连接的多个通孔中的至少两个;将第一凸块连接至接触焊盘;以及将第二凸块连接至多个熔丝中的每一个。
尽管已经详细地描述了本发明的实施例及其优势,但应该理解,可以在不背离所附权利要求限定的本发明主旨和范围的情况下,在能够做各种不同的改变、替换和更改。例如,本领域技术人员将很容易理解,本文中所描述的许多部件、功能、工艺、和材料可以改变而仍包括在本发明的范围内。而且,本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的公开内容将很容易地理解,根据本发明,可以使用现有的或今后开发的用于执行与本文所述的相应实施例基本上相同的功能或获得基本上相同的结果的工艺、机器、制造,材料组分、装置、方法或步骤。因此,所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。
Claims (19)
1.一种中介层,包括:
衬底;
接触焊盘,被设置在所述衬底上;
第一通孔,位于所述衬底中,具有直接连接至所述接触焊盘的第一端;
第一熔丝,设置在第一导电段的第一连接区域和第二连接区域之间,并且通过所述第一导电段的第二连接区域连接至所述第一通孔的第二端;
第二通孔,位于所述衬底中,具有直接连接至所述接触焊盘的第一端;以及
第二熔丝,设置在第二导电段的第一连接区域和第二连接区域之间,并且通过所述第二导电段的第二连接区域连接至所述第二通孔的第二端;
其中,所述第一熔丝和所述第二熔丝被设置在再分布层(RDL)中,所述再分布层(RDL)和所述接触焊盘分别位于所述衬底的相对两侧上。
2.根据权利要求1所述的中介层,还包括:连接至所述接触焊盘的至少一个第三通孔;以及至少一个第三熔丝,其中,所述至少一个第三熔丝中的每一个都连接至所述至少一个第三通孔之一。
3.根据权利要求1所述的中介层,还包括:连接至所述第一熔丝的第一接合焊盘;以及连接至所述第二熔丝的第二接合焊盘。
4.根据权利要求3所述的中介层,还包括:连接至所述第一接合焊盘的第一凸块;以及连接至所述第二接合焊盘的第二凸块。
5.根据权利要求4所述的中介层,还包括:连接至所述接触焊盘的第三凸块。
6.根据权利要求5所述的中介层,其中,所述第三凸块大于所述第一凸块和所述第二凸块。
7.根据权利要求5所述的中介层,其中,所述第一凸块、所述第二凸块、或者所述第三凸块包含焊料。
8.一种用于封装半导体器件的中介层,包括:
衬底,具有第一侧和与所述第一侧相对的第二侧;
多个通孔,被设置在邻近所述第一侧的所述衬底中;
互连结构,被设置在邻近所述第二侧的所述衬底中,所述互连结构包括多个熔丝,所述多个熔丝中的每个均设置在多个导电段的相应一个的第一连接区域和第二连接区域之间;
接触焊盘,直接连接至邻近所述第一侧的所述多个通孔中的至少两个的第一端,所述多个通孔中的至少两个中的每一个的第二端通过所述多个导电段的相应一个的第二连接区域连接至所述多个熔丝之一;以及
凸块,连接至所述接触焊盘。
9.根据权利要求8所述的中介层,其中,所述衬底不具有集成电路器件。
10.根据权利要求8所述的中介层,其中,所述中介层包括三维集成电路(3DIC)中介层。
11.根据权利要求8所述的中介层,其中,在使用所述中介层封装集成电路之前或者之后,能够利用激光对所述多个熔丝进行编程。
12.根据权利要求8所述的中介层,其中,所述凸块包括第一凸块,还包括:连接至所述互连结构的凸块下金属化(UBM)结构;以及连接至所述凸块下金属化(UBM)结构的多个第二凸块,并且其中,部分所述凸块下金属化(UBM)结构连接至与所述多个通孔中的至少两个相连接的所述多个熔丝。
13.根据权利要求12所述的中介层,其中,所述多个第二凸块能够连接至集成电路管芯。
14.根据权利要求12所述的中介层,其中,所述第一凸块能够连接至衬底、印刷电路板(PCB)、或者集成电路管芯。
15.一种使用根据权利要求13所述的中介层封装的半导体器件,其中,集成电路管芯的多个接触件电连接至所述多个第二凸块。
16.根据权利要求15所述的封装半导体器件,还包括:在所述集成电路管芯下方设置的底部填充材料。
17.根据权利要求15所述的封装半导体器件,还包括:在所述集成电路管芯和所述中介层的上方设置的模塑料。
18.一种制造用于封装半导体器件的中介层的方法,所述方法包括:
提供衬底;
在所述衬底中形成多个通孔;
在所述衬底上方形成再分布层(RDL),在所述再分布层(RDL)中形成有多个熔丝,所述多个熔丝中的每个均设置在多个导电段的相应一个的第一连接区域和第二连接区域之间,将每个熔丝通过所述多个导电段的相应一个的第二连接区域连接至所述多个通孔之一的第二端;
将接触焊盘直接连接至与所述熔丝相连接的所述多个通孔中的至少两个的第一端;
将第一凸块连接至所述接触焊盘;以及
将第二凸块连接至所述多个熔丝中的每一个;
其中,所述再分布层(RDL)和所述接触焊盘分别位于所述衬底的相对两侧上。
19.根据权利要求18所述的方法,还包括:使用在所述衬底设置的至少一条导线、至少一个通孔、或者其组合将每个熔丝连接至所述多个通孔之一。
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CN107818958B (zh) * | 2017-11-20 | 2023-10-13 | 长鑫存储技术有限公司 | 底部封装结构及制作方法 |
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CN113517263A (zh) * | 2021-07-12 | 2021-10-19 | 上海先方半导体有限公司 | 一种堆叠结构及堆叠方法 |
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