CN103078050A - 一种倒装led芯片及其制造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 76
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 65
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 238000001338 self-assembly Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 36
- 229910052737 gold Inorganic materials 0.000 claims description 23
- 229910052759 nickel Inorganic materials 0.000 claims description 18
- 229910052594 sapphire Inorganic materials 0.000 claims description 8
- 239000010980 sapphire Substances 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 abstract description 6
- 238000001556 precipitation Methods 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 21
- 230000008569 process Effects 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 238000000149 argon plasma sintering Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000002745 absorbent Effects 0.000 description 1
- 239000002250 absorbent Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000005070 ripening Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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Abstract
本发明提供一种倒装LED芯片及其制造方法,包括:提供衬底,在衬底上沉积外延层,所述外延层包括N型氮化镓层、多量子阱有源层和P型氮化镓层;刻蚀所述外延层,形成台阶阵列,所述台阶阵列暴露出N型氮化镓层;在所述P型氮化镓层上形成第一金属层;对所述第一金属层进行退火自组装;以第一金属层为掩膜刻蚀所述P型氮化镓层,在所述P型氮化镓层中形成坑洞阵列;在坑洞阵列中沉积第二金属层,所述第一金属层和第二金属层组成金属反射镜层。这样,使多量子阱有源层发出的光在金属反射镜层上散射,而不被LED各层结构形成的波导结构限制,最终射出,提高LED的光析出率。
Description
技术领域
本发明涉及LED制造技术领域,尤其涉及一种倒装LED芯片及其制造方法。
背景技术
在LED制造技术工艺中,传统的正装LED芯片结构,P型GaN掺杂困难导致空穴载流子浓度低下且厚度受到限制,从而导致电流不易扩散。因而通常采用在P型GaN表面制备电流扩散层以使电流均匀扩散。然而电流扩散层也具有缺点,一方面电流扩散层会吸收部分光降低光析出率,如果减薄其厚度又限制电流扩散层在P型GaN层表面实现均匀和可靠的电流扩散的效果,因而,在透光率和电流扩散效果二者之间要给以适当的折衷,然而,折衷设计的结果必定使其功率转换的提高受到了限制。并且,这种结构的电极和引线在发光区同一侧,工作时会挡住部分光线。因此,这种结构制约了LED的工作效率。另一方面,这种结构的PN结热量通过蓝宝石衬底导出,蓝宝石的导热系数很低,对大尺寸的功率型芯片来说导热路径太长,因而LED芯片的热阻较大,工作电流也受到限制。
为了克服正装LED芯片的这些不足,Lumileds公司于1998年发明了倒装LED芯片(Flip chip)结构。倒装LED芯片结构制作方法如下:制备LED芯片;同时制备对应芯片尺寸的散热基板,并在散热基板上制作电极的导电层和引出导电层(超声波金丝球焊点);将LED芯片与散热基板焊接在一起。在这种结构中,在PN结与P电极之间增加了一个金属反射镜层,消除了电极和引线的挡光,使得光从蓝宝石衬底射出。由于光不从电流扩散层出射,能将电流扩散层的厚度设置的更厚,使倒装LED芯片的电流密度均匀分布。同时这种结构还可以将PN结的热量直接通过导电层或金属焊点导给热导系数比蓝宝石高3~5倍的散热基板,散热效果更优。因此这种结构具有电、光、热等方面较优的特性。
现有的金属反射镜层的形成方法是在反射率较高的金属镀到P型GaN的表面,这样,从有源层发出的光,就会在倒装芯片的底部发生反射,减少了光在芯片底部被吸收量,从而提高光析出率。但是这样的结构使部分的光被限制在LED各层结构形成的波导结构中,经过多次反射后,衰减或者被吸收无法射出,影响其光析出率。
发明内容
本发明提供一种提高倒装LED芯片光析出率的方法,所述提高倒装LED芯片光析出率的方法先在P型氮化镓层上形成第一金属层,通过退火工艺使第一金属层自组装,以自组装后的金属层为掩膜刻蚀P型氮化镓,再最后形成凹凸不平的金属反射镜层,使多量子阱有源层发出的光在金属反射镜层上散射,而不被LED各层结构形成的波导结构限制,最终射出,提高LED的光析出率。
本发明提供一种提高倒装LED芯片光析出率的方法,包括:
提供衬底,在衬底上沉积外延层,所述外延层包括N型氮化镓层、多量子阱有源层和P型氮化镓层;
刻蚀所述外延层,形成台阶阵列,所述台阶阵列暴露出N型氮化镓层;
在所述P型氮化镓层上形成第一金属层;
对所述第一金属层进行退火自组装;
以第一金属层为掩膜刻蚀所述P型氮化镓层,在所述P型氮化镓层中形成坑洞阵列;
在坑洞阵列中沉积第二金属层,所述第一金属层和第二金属层组成金属反射镜层。
可选的,所述金属反射镜层由多层金属组成。
可选的,组成所述金属反射镜层的多层金属为Ni/Ag/Ti/Pt/Au、Ni/Al/Ti/Pt/Au、Ni/Ag/Ni/Au或Ni/Al/Ti/Au。
可选的,所述金属反射镜层的厚度为0.1nm~10nm。
可选的,干法刻蚀所述P型氮化镓层,在所述P型氮化镓层中形成坑洞阵列。
可选的,在形成金属反射镜层之后还包括:在所述N型氮化镓层上形成N电极,在金属反射镜层上形成P电极;将N电极和P电极倒装焊接到一散热基板上。
可选的,所述电极的材质为Au、Au/Sn薄膜或Sn焊膏。
可选的,所述衬底为蓝宝石衬底。
本发明还公开上述倒装LED芯片的制造方法制造的倒装LED芯片结构,包括:
衬底;
形成在所述衬底上的外延层,所述外延层包括依次形成的N型氮化镓层、多量子阱有源层和P型氮化镓层,所述P型氮化镓层中形成有坑洞阵列;
金属反射镜层,形成在所述P型氮化镓层上。
可选的,组成金属反射镜层的多层金属为Ni/Ag/Ti/Pt/Au、Ni/Al/Ti/Pt/Au、Ni/Ag/Ni/Au或Ni/Al/Ti/Au。
可选的,所述金属反射镜层的厚度为0.1nm~10nm。
可选的,所述LED芯片还包括:
形成在所述金属反射镜层上的P电极、形成于所述N型氮化镓层上的N电极、与所述N电极和P电极焊接的散热基板。
可选的,所述电极的材质为Au、Au/Sn薄膜或Sn焊膏。
本发明提供一种倒装LED芯片的结构及其制造方法,所述倒装LED芯片的制造方法先形成第一金属层,利用退火工艺自组装第一金属层,利用第一金属层为掩膜刻蚀P型氮化镓层,再形成第二金属层,由第一金属层和第二金属层组成凹凸不平的金属反射镜层,提高光析出率。
附图说明
图1为本发明实施例的倒装LED芯片的制造方法的流程图;
图2A~2G为本发明实施例的倒装LED芯片的制造方法的各步骤的示意图。
具体实施方式
在背景技术中已经提及,现有的金属反射镜层,仍会影响倒装LED的光析出率。本发明提供一种倒装LED芯片的结构及其制造方法,所述倒装LED芯片的制造方法先形成第一金属层,利用退火工艺自组装第一金属层,利用第一金属层为掩膜刻蚀P型氮化镓层,再形成第二金属层,由第一金属层和第二金属层组成凹凸不平的金属反射镜层,提高光析出率。
下面将结合附图对本发明进行更详细的描述,其中表示了本发明的优选实施例,应所述理解本领域技术人员可以修改在此描述的本发明,而仍然实现本发明的有利效果。因此,下列描述应当被理解为对于本领域技术人员的广泛知道,而并不作为对本发明的限制。
为了清楚,不描述实际实施例的全部特征。在下列描述中,不详细描述公知的功能和结构,因为它们会使本发明由于不必要的细节而混乱。应当认为在任何实际实施例的开发中,必须做出大量实施细节以实现开发者的特定目标,例如按照有关系统或有关商业的限制,由一个实施例改变为另一个实施例。另外,应当认为这种开发工作可能是复杂和耗费时间的,但是对于本领域技术人员来说仅仅是常规工作。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书,本发明的优点和特征将更清楚。需说明的是,附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。
请参考图1,其为本发明实施例的倒装LED芯片的制造方法的流程图,所述方法包括如下步骤:
步骤S021,提供衬底,在衬底上沉积外延层,所述外延层包括N型氮化镓层、多量子阱有源层和P型氮化镓层;
步骤S022,刻蚀所述外延层,形成台阶阵列,所述台阶阵列暴露出N型氮化镓层;
步骤S023,在所述P型氮化镓层上形成第一金属层;
步骤S024,对所述第一金属层进行退火自组装;
步骤S025,以第一金属层为掩膜刻蚀所述P型氮化镓层,在所述P型氮化镓层中形成坑洞阵列;
步骤S026,在坑洞阵列中沉积第二金属层,所述第一金属层和第二金属层组成金属反射镜层。
该方法的核心思想在于,先在P型氮化镓层上形成第一金属层,通过退火工艺使第一金属层自组装,以自组装后的金属层为掩膜刻蚀P型氮化镓,再最后形成凹凸不平的金属反射镜层,使有源层发出的光在金属反射镜层上散射,而不被LED各层结构形成的波导结构限制,最终射出,提高LED的光析出率。
参照图2A,执行步骤S021,提供衬底101,在衬底101上沉积外延层131。本实施例中,所述衬底101为蓝宝石衬底,优选的所述蓝宝石衬底表面经过图形化处理。所述外延层131包括N型氮化镓层102、多量子阱有源层103和P型氮化镓层104。
参考图2B,执行步骤S022,刻蚀所述外延层131,形成台阶阵列105,所述台阶阵列105暴露出N型氮化镓层102。
参考图2C,执行步骤S023,在所述P型氮化镓层104上形成第一金属层106。优选的,所述第一金属层106为多层金属组成以兼顾反射镜、电流扩散及散热性能,例如可使用Ni/Ag/Ti/Pt/Au、Ni/Al/Ti/Pt/Au、Ni/Ag/Ni/Au或Ni/Al/Ti/Au等组合。所述第一金属层106的厚度为0.1nm~10nm。可以利用电镀、沉积等方法在台阶阵列105和P型氮化镓层104上形成所述第一金属层106,然后选择性去除台阶阵列105中的第一金属层106,例如,可以先在第一金属层106上形成光阻层,利用光刻工艺选择暴露出台阶阵列105表面的第一金属层,然后利用刻蚀工艺去除N型氮化镓层102表面的第一金属层。
参考图2D,执行步骤S024,对所述第一金属层106进行退火自组装。第一金属层106在退火工艺的作用下结晶,并发生Oswald ripening效应(奥斯瓦尔德熟化效应),小的晶体颗粒消失,大的晶体颗粒长大,从而自组装成不连续的第一金属层,在第一金属层106中形成阵列分布的孔洞106’,部分暴露出P型氮化镓层104。退火温度为200℃~900℃,可以根据第一金属层106的具体材质来选择不同的退火温度。
参考图2E,执行步骤S025,以第一金属层106为掩膜刻蚀所述P型氮化镓层104,在所述P型氮化镓层104中形成坑洞阵列104’。优选的,利用干法刻蚀来刻蚀所述P型氮化镓层104,并且,不暴露出其下的多量子阱有源层103。
参考图2F,执行步骤S026,在坑洞阵列中沉积第二金属层,所述第二金属层为多层金属组成例如可使用Ni/Ag/Ti/Pt/Au、Ni/Al/Ti/Pt/Au、Ni/Ag/Ni/Au或Ni/Al/Ti/Au等组合。所述第一金属层和第二金属层共同组成金属反射镜层107,金属反射镜层的多层金属以兼顾反射镜、电流扩散及散热性能。这样从多量子阱有源层发出的光,经过凹凸不平的金属反射层的散射作用,不会被LED的各层结构形成的波导结构所限制,从衬底端射出,提高了LED器件的光析出率。
当然,在形成金属反射镜层107之后还包括常规的后续倒装LED芯片制造步骤,考图2G,例如之后可以包括在所述N型氮化镓层102上形成N电极的步骤和在金属反射镜层107上形成P电极109步骤,以及将N电极108和P电极109倒装焊接到散热基板110上的步骤和裂片封装的步骤等,本领域技术人员可以根据公知常识将这些步骤加入本发明中。
根据本发明的另一面,还提供一种利用上述实施例所述倒装LED芯片的制造方法制造的LED芯片,参考图2G,包括:衬底101、形成在所述衬底101上的外延层和形成在所述P型氮化镓层上的金属反射镜层。所述外延层包括N型氮化镓层102、多量子阱有源层103和P型氮化镓层104,所述P型氮化镓层104中形成有坑洞阵列,所述金属反射镜层107为凹凸不平的结构。由于金属反射镜层107为凹凸不平的结构,使得多量子阱有源层发出的光在金属反射镜层上散射,而不被LED各层结构形成的波导结构限制,能经过多次反射后最终射出,提高LED的光析出率。
综上所述,本发明提供一种倒装LED芯片的结构及其制造方法,所述提高倒装LED芯片光析出率的方法先在P型氮化镓层上形成第一金属层,通过退火工艺使第一金属层自组装,以自组装后的金属层为掩膜刻蚀P型氮化镓,再最后形成凹凸不平的金属反射镜层,使多量子阱有源层发出的光在金属反射镜层上散射,而不被LED各层结构形成的波导结构限制,最终射出,以提高LED的光析出率。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (9)
1.一种倒装LED芯片的制造方法,包括:
提供衬底,在衬底上沉积外延层,所述外延层包括N型氮化镓层、多量子阱有源层和P型氮化镓层;
刻蚀所述外延层,形成台阶阵列,所述台阶阵列暴露出N型氮化镓层;
在所述P型氮化镓层上形成第一金属层;
对所述第一金属层进行退火自组装;
以第一金属层为掩膜刻蚀所述P型氮化镓层,在所述P型氮化镓层中形成坑洞阵列;
在坑洞阵列中沉积第二金属层,所述第一金属层和第二金属层组成金属反射镜层。
2.如权利要求1所述的倒装LED芯片的制造方法,其特征在于:所述金属反射镜层由多层金属组成。
3.如权利要求2所述的倒装LED芯片的制造方法,其特征在于:组成所述金属反射镜层的多层金属为Ni/Ag/Ti/Pt/Au、Ni/Al/Ti/Pt/Au、Ni/Ag/Ni/Au或Ni/Al/Ti/Au。
4.如权利要求3所述的倒装LED芯片的制造方法,其特征在于:所述金属反射镜层的厚度为0.1nm~10nm。
5.如权利要求1所述的倒装LED芯片的制造方法,其特征在于:干法刻蚀所述P型氮化镓层,在所述P型氮化镓层中形成坑洞阵列。
6.如权利要求1所述的倒装LED芯片的制造方法,其特征在于:所述衬底为蓝宝石衬底。
7.一种利用权利要求1所述的倒装LED芯片的制造方法制造的倒装LED芯片,其特征在于,包括:
衬底;
形成在所述衬底上的外延层,所述外延层包括依次形成的N型氮化镓层、多量子阱有源层和P型氮化镓层,所述P型氮化镓层中形成有坑洞阵列;
金属反射镜层,形成在所述P型氮化镓层上。
8.如权利要求7所述的倒装LED芯片,其特征在于:组成金属反射镜层的多层金属为Ni/Ag/Ti/Pt/Au、Ni/Al/Ti/Pt/Au、Ni/Ag/Ni/Au或Ni/Al/Ti/Au。
9.如权利要求8所述的倒装LED芯片,其特征在于:所述金属反射镜层的厚度为0.1nm~10nm。
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CN108963050A (zh) * | 2018-06-26 | 2018-12-07 | 佛山市国星半导体技术有限公司 | 一种微小间距led芯片及其制作方法 |
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