TWI258876B - Compound semiconductor light-emitting device and production method thereof - Google Patents

Compound semiconductor light-emitting device and production method thereof Download PDF

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Publication number
TWI258876B
TWI258876B TW094109319A TW94109319A TWI258876B TW I258876 B TWI258876 B TW I258876B TW 094109319 A TW094109319 A TW 094109319A TW 94109319 A TW94109319 A TW 94109319A TW I258876 B TWI258876 B TW I258876B
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Taiwan
Prior art keywords
light
conductor layer
layer
compound semiconductor
type
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TW094109319A
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Chinese (zh)
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TW200539483A (en
Inventor
Ryouichi Takeuchi
Wataru Nabekura
Takashi Udagawa
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Showa Denko Kk
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Publication of TW200539483A publication Critical patent/TW200539483A/en
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Publication of TWI258876B publication Critical patent/TWI258876B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

A pn-junction compound semiconductor light-emitting device is provided, which comprises a stacked structure including a light-emitting layer composed of an n-type or a p-type aluminum gallium indium phosphide and a light-permeable substrate for supporting the stacked structure, and the stacked structure and the light-permeable substrate being joined together, wherein the stacked structure includes an n-type or a p-type conductor layer, the conductor layer and the substrate are joined together, and the conductor layer is composed of a group III-V compound semiconductor containing boron.

Description

1258876 九、發明說明： 本申請書主2 004年3月29日提出申請之日本申請書 第2 0 0 4 - 〇 9 5 1 4 5號的優先權，並在此處納入參考。 【發明所屬之技術領域】 本發明係關於一種具有堆疊結構之ρ η接面化合物半 導體發光裝置，尤其是可以得到筒發光強度之ρη接面化合 物半導體發光裝置，其中堆疊結構包含由磷化鋁鎵銦混晶 (AlGalnP)構成之發光層。 【先前技術】 具有由磷化鋁鎵銦混晶（組成式：（A 1 x G a ! _ X ) γ I η ! _ γ P， 0SXS1 )構成，且氣相成長在η型或ρ型砷化鎵（GaAs)單晶 基板上之發光層的發光二極體（以下簡稱L E D s )，可以發射 波長相對於綠光到紅光的光（例如，參見非專利文獻1 )。 尤其，具有由磷化鋁鎵銦混晶（（AlxGaHh.sIno.sP : 〇^Χ^1)(在上述之組成式中，Y = 0.5)構成之發光層在 GaAs 基板的L E D s已被採用。 在具有由（AlxGauhlnuP構成之發光層的LED中， 爲了得到很高的發光強度，裝置操作電流在發光層的寬廣 區域上擴散和將光有效的引出到外部是必須的。因此，通 常會在發光層之上提供電流擴散層和窗層。 窗層可以允許發射自發光層的光傳輸到外部。例如， 具有由磷化鎵（G a P )構成之窗層的l E D已被揭露（參見專利 文獻1 )。 在具有氣相成長在G a A s基板上之堆疊結構的L E D中1258876 IX. INSTRUCTIONS: The priority of Japanese Application No. 2 0 0 - 4 - 1 5 1 4 5, filed on March 29, 2005, is hereby incorporated by reference. [Technical Field] The present invention relates to a p η junction compound semiconductor light-emitting device having a stacked structure, in particular, a pn junction compound semiconductor light-emitting device capable of obtaining a barrel light-emitting intensity, wherein the stacked structure comprises aluminum gallium phosphide A light-emitting layer composed of indium mixed crystals (AlGalnP). [Prior Art] It consists of a mixed crystal of aluminum gallium indium phosphide (composition formula: (A 1 x G a ! _ X ) γ I η ! γ γ P, 0SXS1 ), and the gas phase grows in n-type or p-type arsenic A light-emitting diode (hereinafter abbreviated as LED s) of a light-emitting layer on a gallium (GaAs) single crystal substrate can emit light having a wavelength relative to green light to red light (for example, see Non-Patent Document 1). In particular, LEDs having a luminescent layer composed of an aluminum gallium phosphide-indium mixed crystal ((AlxGaHh.sIno.sP: 〇^Χ^1) (in the above composition formula, Y = 0.5) have been used in GaAs substrates) In an LED having a light-emitting layer composed of (AlxGauhlnuP, in order to obtain a high luminous intensity, it is necessary for the device operating current to diffuse over a wide area of the light-emitting layer and to efficiently extract light to the outside. Therefore, it is usually A current diffusion layer and a window layer are provided over the light-emitting layer. The window layer may allow light emitted from the light-emitting layer to be transmitted to the outside. For example, a ED having a window layer composed of gallium phosphide (G a P ) has been disclosed (see Patent Document 1). In an LED having a stacked structure in which a vapor phase is grown on a Ga a s substrate

J258876 ，因爲G a A s基板對於發光波長是不透光的，所以發躬 光層的光只能從LED的上側引出。因此，將光引出g 的效率無法令人滿意，於是要改善光引出效率。 爲了要解決這個問題，一種L E D的製造方法已招 。在該方法中，在形成於GaAs基板上之堆疊結構上， 相對於發光波長是透明的基板，然後再移除提供氣相 | 堆疊結構之GaAs基板。 藉由結合相對於發光波長是透明的基板之優點， • 上述方法所製造之LED可以允許光從上面、背面和俱 出，於是可以獲得很高的光引出效率。 • 該習知之LED的製造方法包含將相對於發光波長 . 明的基板（如，GaP、硒化鎵（ZnSe)、或碳化矽（SiC))， 在具有發光層之堆疊結構上（例如，參見專利文獻2 另一種被揭露之L E D的製造方法，包含將相對J 波長是透明的GaAs基板，藉由透明導體膜的媒介，女 銦錫（ITO)膜，接合在堆疊結構上（例如，參見專利文 [非專利文獻] Y. Hosokawa，Journal of Crystal Growth(荷蘭）， 年，221期，第 652-656 頁。 [專利文獻1 ] U S P 5，0 0 8，7 1 8專利說明書 [專利文獻2 ] 自發 外部 :提出 形成 丨成長 經由 I面射 :是透 接合 和3) 〉發光 1氧化 獻4) 2 0 0 0 1258876 曰本專利第3 2 3 0 6 3 8號 [專利文獻3 ] 日本未審專利公報（公開）第2 00卜244499號 [專利文獻4 ] 曰本專利第2 5 8 8 8 4 9號 [發明揭露] [本發明要解決的問題] 專利文獻4也有揭露，當相對於發光波長是透明的 GaAs基板，被接合在包含各自由（AlxGauhln^yP構成的 披覆層和電流擴散層之堆疊結構的最上層表面上時，接合 必須在高溫（8 3 0 °C或更高）下藉由加熱執行（參見專利文獻 4，專利說明書中的第[0 0 0 7 ]段）。 專利文獻2也有揭露，當不採用光輻射方式，如yag 雷射，加熱接合時，相對於發光波長是透明的半導體基板 ’很適合藉由加熱到3 0 0 °C至9 0 0 °C，接合在堆疊結構上 (參見專利文獻2，專利說明書中的第[〇 〇 3 5 ]段）。 在這樣的高溫條件下，用以形成堆疊結構且含有容易 氧化的鋁（A 1)之I Π - V族化合物半導體（如，磷化鋁鎵銦混 晶（（A 1 X G a 1 - X ) γ I η卜γ P )或砷化鋁鎵（組成式·· a 1 x G a 丫 A s， 0SX，Y$1，X + Y=l)會很快就氧化。 因此，會在堆疊結構和與其結合之可透光基板（如，G aP 基板）之間的接面區’形成由氧化物或其他物質所構成之高 電阻層。此高電阻層會妨礙裝置操作電流的流動。 在某些堆疊結構中，除了發光層之外，還有提供由磷 -7- ,1258876 化鋁鎵銦混晶（（A 1 x G a ! _ χ ) γ I η ! _ γ p )所構成之層。一般而言， 爲了要給予混合層導體性，會將很容易熱擴散的雜質元素 ，如鋅（Zn)或硒（Sr)摻入層中。 當可透光基板經由高溫加熱與堆疊結構接合時，很容 易熱擴散的雜質元素，如鋅（Ζ η)或硒（S e )，會擴散進入發光 層或其他層中。因此’η型或p型發光層的載子濃度，或 > LED的順向電壓（Vf)會有問題的變化。 專利文獻4揭露含有氧化碘錫膜和氧化鎘錫膜之透明 # 導體氧化物膜。但是，這些氧化物膜恨難和111 - V族化合 物半導體，如磷化鋁鎵銦混晶（（A1 x G a ! _ X ) y I η ! _ y P )，形成可 ' 靠的歐姆接觸。 - 因此，即使當藉由任何上述透明氧化物物的媒介，將 具有良好可透光性的透明基板，如藍寶石（α-Α12 03單晶）、 玻璃、二氧化鈦（T i 0 2 )、或氧化鎂（M g 0 )，接合到堆疊結構 > 時，由於在製成的LED之堆疊結構寬廣區域上之透明基板 的媒介’裝置操作電流很擴散，因此這是有問題的。 ®【發明內容】 本發明係要爲了解決上述關於傳統技術的問題。因此 * ’本發明提供一種pn接面化合物半導體發光裝置及裝置的 、 製造方法，其中裝置具有低電阻，允許裝置操作電流容易 流動，而且對於光引出到外部展現良好的效率。 因此，本發明係要提出下列幾項： (1) 一種pn接面化合物半導體發光裝置，包含含有由η型 或Ρ型磷化鋁鎵銦所構成的發光層之堆疊結構，及用以支 1258876 因爲導體層係由含有硼之未刻意加入雜質元素之未摻 雜III-V族化合物半導體所構成的，所以加λ雜質元素擴 散進入發光層或其他層’而使ρη接面化合物半導體發光裝 置的順向電壓或其他特性改變之現象不會發生’而且還可 以獲得較低的順向電流。 因爲導體層係由含有砷和硼之III-V族化合物半導體 ^ 所構成的，所以可以在導體層上形成展現良好歐姆接觸特 I 性之電極，於是可以獲得較低的順向電流° Φ 因爲導體層係由含有磷和硼之ιπ-ν族化合物半導體 ，或含有砷和硼之ΠΙ-ν族化合物半導體（砷磷化硼）所構成 -的，所以可以得到很寬的能隙，而且發射自發光層的光可 ^ 以被傳輸到可透光基板’而具有很低的傳輸損失’於是可 以獲得很高的發光強度。 因爲導體層係由含有雙晶之含硼ΠΙ-ν族化合物半導 > 體所構成的，所以導體層和基底層之間的晶格差配可以遷 移，於是可以產生具有高結晶性之導體層。因此，可以製 • 造出具有較低電阻’和光引出到外部展現良好的效率之PI1 接面化合物半導體發光裝置。 # 根據ρη接面化合物半導體發光裝置之製造方法，形成 由含硼III-V族化合物半導體所構成之η型或ρ型導體層 ，以提供用以接合堆疊結構和可透光基板之接合層。因此 ，導體層和可透光基板可以在低溫下用很強的黏性物質彼 此相互接合’而不必使用光輪射方式’如Y A G雷射，加熱 1258876 由η型或p型磷化鋁鎵銦混晶（組成式：（AlxGai_x)().5In().5P ’ 0SXS1)所構成的發光層之堆疊結構，及用以支撐堆疊結 構之可透光基板。該堆疊結構包含由含硼I Π _ V族化合物 半導體所構成，且當作與可透光基板的接合層之η導電型 或ρ導電型導體層。可透光基板係被接合到導體層。 堆疊結構具有ρη接面雙異質（DH)接面結構。堆疊結構例 > 包含依續堆疊的下披覆層（如，ρ型鋅（Ζη)摻雜（Al〇.7Ga().3)〇.5In().5P) ’發光層（如，ρ型未摻雜（Al〇. 4 G aQ.du I 5 P)，及上披覆 _ 層（如，η 型硒（Se)摻雜（AlQ.7Ga().3)Q.5In().5P)。 在堆疊結構的導體層上，提供第一極性之歐姆電極， • 而在相對於發光層之導體層的相反側上，在另一種成份層 • 上（如，緩衝層或披覆層），提供相反極性之歐姆電極。 藉由以上之組態，發光層會因順向裝置操作電流在歐 姆電極之間流通而發光。 ^ 虽堆暨結構包含依續堆暨的η型（A 1 X G a 1 - X ) γ I η 1 - γ P所 構成的下披覆層，發光層，由ρ型（AlxGai.xhlru-YP所構 ® 成的上披覆層，和由P型磷化硼所構成的導體層時，P型 歐姆電極（正電極）係被提供在導體層上，而η型歐姆電極 • (負電極）則被提供在下披覆層上，於是製造出ρη接面化合 ^ 物半導體發光裝置。 下面將詳細說明形成本發明要點之導體層和可透光層 〇 導體層係由含硼III-V族化合物半導體所構成的。 對於此處所使用的，"含硼III-V族化合物半導體”係含 -13- 1258876 有當作成份元素硼（B)之III-V族化合物半導體。範例包含 以組成式：BaAlpGaYlni-cx-piPi.sAssf^OsaSl，〇$β<ΐ，〇$γ<ι ’ （Χα + β + γυ，（^δ<1)表示之化合物；及以組成式： Β α A 1 β G a γ I n j α - ρ · γ ρ 卜 δ N s ( 〇 < a S 1，0 < β < 1，0 S γ < 1，0 < α + β + γ < 1 ，（^δ<1)表示之化合物。 當含硼III-V族化合物半導體混晶含有很大的元素變 > 化性時’具有一致組成比例之混晶層就更難形成（參見iwao Teramoto所著，在；199 5年3月30曰由Baihukan出版之 _ "Introduction to Semiconductor Device’’，第 l 版的第 24 頁）。因此，以上面組成式表示之含硼III-V族化合物半導 -體宜包含3種或小於3種的組成元素，以形成具有一致組 . 成比例之期望的混晶層。 尤其，導體層係不含有容易氧化之組成元素（如鋁（A1)) ，而含有硼和磷（P )或砷（A s )當作組成元素之111 - V族化合 > 物半導體層。因爲不含有容易氧化之組成元素（如鋁（A1)) 之導體層具有很高的抗氧化性，所以在製造發光裝置，可 ® 以防止經由導體層的加熱，而由以別的方式形成的氧化物 或其他物質所構成之高電阻層。因此，可以防止由於高電 . 阻層的形成而造成導體性下降。 不含有容易氧化之組成元素（如鋁（A1))，而含有硼和磷 當作組成元素之III-V族化合物半導體（下面也可以將該種 半導體稱爲磷化硼系半導體）的範例，包含磷化硼，以組成 式：BaGaYP(0<aSl，〇^γ<ι)表示之磷化硼鎵，以組成式： BalnuPCCXo^l)表示之磷化硼銦，及以組成式：β Pl_sNs -14- 1258876 (〇$δ<ι)表示之氮磷化硼，這是含有許多v族元素之混晶。 因爲含磷之磷化硼系半導體展現良好的熱阻性，所以 由其所形成的導體層可以展現增強的抗氧化性。 不含有容易氧化之組成元素（如鋁（Α1))，而含有硼和砷 _ 當作組成元素之III-V族化合物半導體（下面也可以將該種 半導體稱爲砷化硼系半導體）的範例，包含以組成式： > 表示之化砷磷化硼。 與由含硼和當作單一 V族元素的磷（P)之III-V族化合 • 物半導體所構成的導體層相較，由該種砷化硼系半導體所 構成的導體層展現較低的電阻。藉由砷化硼系半導體的採 用，可以降低順向電壓。 • 導體層的硼原子濃度（含量）沒有特別的限制，而且濃 度可以根據pn接面化合物半導體發光裝置的使用，發光波 長’或其他因素而作適當地修正。導體層可以爲不含有大 > 量硼當作成份元素之層（如硼摻雜III — V族化合物半導體） 〇 ® 當硼原子濃度小於1 X 1 0 19 c m ·3時，展現充份抗氧化性 之導體層很難確實形成。因此，在下面所敘述之pn接面化 - 合物半導體發光裝置的製造步驟中，導體層和可透光基板 . 的接合’最好是在無氧的惰性氣體環境中執行，如氫氣（H2) 、氮氣（n2)、或氬氣（Ar)。 導體層的導電型最好要和堆疊結構與導體層接觸的成 份層一致（即形成在導體層上之基底層）。 導體層最好具有很低的電阻。尤其，在室溫下，導體 -15-J258876, because the G a A s substrate is opaque to the wavelength of the light, the light from the light-emitting layer can only be extracted from the upper side of the LED. Therefore, the efficiency of extracting light from g is unsatisfactory, so the light extraction efficiency is improved. In order to solve this problem, a manufacturing method of L E D has been recruited. In this method, on a stacked structure formed on a GaAs substrate, a substrate which is transparent with respect to an emission wavelength, and then a GaAs substrate which provides a vapor phase | stacked structure is removed. By combining the advantages of a substrate that is transparent with respect to the wavelength of the light, the LEDs manufactured by the above method allow light to be emitted from the top, the back, and the periphery, so that high light extraction efficiency can be obtained. • The conventional LED manufacturing method comprises a substrate (for example, GaP, gallium selenide (ZnSe), or tantalum carbide (SiC)) with respect to an emission wavelength, on a stacked structure having a light-emitting layer (for example, see Patent Document 2 Another method for manufacturing an exposed LED comprising a GaAs substrate which is transparent with respect to J wavelength, and a female indium tin (ITO) film bonded to a stacked structure by a medium of a transparent conductor film (for example, see Patent [Non-patent literature] Y. Hosokawa, Journal of Crystal Growth (Netherlands), vol. 221, pp. 652-656. [Patent Document 1] USP 5,0 0 8,7 1 8 Patent Specification [Patent Document 2 Spontaneous external: proposed formation 丨 growth through I plane: is permeable joint and 3) 〉 luminescence 1 oxidization contribution 4) 2 0 0 0 1258876 曰 Patent No. 3 2 3 0 6 3 8 [Patent Document 3] Japan not Patent Publication (Publication) No. 2 00 244499 [Patent Document 4] 曰 Patent No. 2 5 8 8 8 4 9 [Invention Disclosure] [Problems to be Solved by the Invention] Patent Document 4 is also disclosed, when The luminescent substrate is a transparent GaAs substrate that is bonded to each other When the uppermost surface of the stacked structure of the cladding layer and the current diffusion layer composed of (AlxGauhln^yP), the bonding must be performed by heating at a high temperature (830 ° C or higher) (see Patent Document 4, Patent) Paragraph [0 0 0 7] in the specification. Patent Document 2 also discloses that when a light radiation method, such as yag laser, is used, the semiconductor substrate which is transparent with respect to the light-emitting wavelength is suitable for heating by heating. Bonded to the stacked structure up to 300 ° C to 900 ° C (see Patent Document 2, paragraph [〇〇 3 5 ] in the patent specification). Under such high temperature conditions, to form a stacked structure And an I Π - V compound semiconductor containing aluminum (A 1 ) which is easily oxidized (for example, aluminum gallium phosphide indium mixed crystal ((A 1 XG a 1 - X ) γ I η γ γ P ) or aluminum gallium arsenide (Constituent formula · · a 1 x G a 丫A s, 0SX, Y$1, X + Y=l) will oxidize very quickly. Therefore, it will be in a stacked structure and a permeable substrate (for example, GaP) The junction region between the substrates] forms a high resistance layer composed of an oxide or other substance. This high resistance layer hinders The flow of the operating current is set. In some stacked structures, in addition to the light-emitting layer, there is also a mixed crystal of aluminum gallium indium (Y 1 x G a ! _ χ ) γ I η provided by phosphorus-7-, 1258876! _ γ p ) The layer formed. In general, in order to impart conductivity to the mixed layer, an impurity element which is easily thermally diffused, such as zinc (Zn) or selenium (Sr), is incorporated into the layer. When the light-permeable substrate is bonded to the stacked structure via high-temperature heating, an impurity element which is easily diffused by heat, such as zinc (?) or selenium (Se), diffuses into the light-emitting layer or other layers. Therefore, there is a problematic change in the carrier concentration of the ?-type or p-type light-emitting layer, or the forward voltage (Vf) of the LED. Patent Document 4 discloses a transparent # conductor oxide film containing a tin oxide oxide film and a cadmium oxide film. However, these oxide films hate difficult and 111-V compound semiconductors, such as aluminum gallium indium phosphide mixed crystals ((A1 x G a ! _ X ) y I η ! _ y P ), forming ohmic contacts that can be relied upon . - Therefore, even when the medium of any of the above transparent oxides is used, a transparent substrate having good light transmittance, such as sapphire (α-Α12 03 single crystal), glass, titanium oxide (T i 0 2 ), or oxidation When magnesium (M g 0 ), bonded to the stacked structure >, the medium 'device operating current of the transparent substrate over a wide area of the fabricated LED stack structure is very diffuse, this is problematic. ® [Summary of the Invention] The present invention is to solve the above problems with respect to the conventional art. Accordingly, the present invention provides a method of fabricating a pn junction compound semiconductor light-emitting device and apparatus, wherein the device has a low resistance, allows the device operating current to flow easily, and exhibits good efficiency for light extraction to the outside. Therefore, the present invention is to propose the following items: (1) A pn junction compound semiconductor light-emitting device comprising a stacked structure comprising a light-emitting layer composed of n-type or germanium-type aluminum gallium indium phosphide, and for supporting 1258876 Since the conductor layer is composed of an undoped III-V compound semiconductor containing boron which is not intentionally added with an impurity element, the λ impurity element is diffused into the light-emitting layer or other layer' to make the pn junction compound semiconductor light-emitting device The phenomenon that the forward voltage or other characteristic changes does not occur' and a lower forward current can be obtained. Since the conductor layer is composed of a III-V compound semiconductor containing arsenic and boron, an electrode exhibiting good ohmic contact characteristics can be formed on the conductor layer, so that a lower forward current can be obtained. The conductor layer is composed of a compound semiconductor containing phosphorus and boron, or a ytterbium-ν compound semiconductor containing arsenic and boron (arsenic arsenide), so that a wide energy gap can be obtained and emission is obtained. The light from the self-luminous layer can be transmitted to the permeable substrate 'with very low transmission loss' so that a high luminous intensity can be obtained. Since the conductor layer is composed of a boron-containing ytterbium-ν compound semiconductor semiconductor containing a double crystal, the lattice difference between the conductor layer and the underlying layer can migrate, so that a conductor layer having high crystallinity can be produced. . Therefore, it is possible to manufacture a PI1 junction compound semiconductor light-emitting device having a lower resistance' and light-extracting to the outside to exhibit good efficiency. # According to the manufacturing method of the pn junction compound semiconductor light-emitting device, an n-type or p-type conductor layer composed of a boron-containing III-V compound semiconductor is formed to provide a bonding layer for bonding the stacked structure and the light-permeable substrate. Therefore, the conductor layer and the permeable substrate can be joined to each other with a strong viscous substance at a low temperature without using a light-rotation method such as YAG laser, heating 1258876 by η-type or p-type phosphide-aluminum-gallium-indium mixed A stacked structure of a light-emitting layer composed of a crystal (composition formula: (AlxGai_x) (). 5In (). 5P ' 0SXS1), and a light-permeable substrate for supporting the stacked structure. The stacked structure includes an n-conducting type or a p-conducting type conductor layer composed of a boron-containing I Π _ V compound semiconductor and serving as a bonding layer with a light-permeable substrate. The light transmissive substrate is bonded to the conductor layer. The stacked structure has a ρη junction double heterojunction (DH) junction structure. Stacked structure example> includes a lower cladding layer that is continuously stacked (eg, p-type zinc (Ζη) doped (Al〇.7Ga().3)〇.5In().5P) 'light-emitting layer (eg, ρ Type undoped (Al〇. 4 G aQ.du I 5 P), and overlying _ layer (eg, η-type selenium (Se) doping (AlQ.7Ga().3) Q.5In(). 5P). On the conductor layer of the stacked structure, an ohmic electrode of a first polarity is provided, • on the opposite side of the conductor layer relative to the luminescent layer, on another component layer (eg, a buffer layer or a cladding layer) Providing an ohmic electrode of opposite polarity. With the above configuration, the luminescent layer emits light due to the circulatory operation current flowing between the ohmic electrodes. ^ Although the stack structure includes the n-type of the continuation heap (A 1 XG a 1 - X ) γ I η 1 - γ P consists of a lower cladding layer, a light-emitting layer, an upper coating layer of p type (AlxGai.xhlru-YP), and a P-type boron phosphide In the case of the conductor layer formed, a P-type ohmic electrode (positive electrode) is provided on the conductor layer, and an n-type ohmic electrode (negative electrode) is provided on the lower cladding layer, thus producing a pn junction junction ^ Semiconductor luminescence The conductor layer and the permeable layer 〇 conductor layer forming the gist of the present invention are composed of a boron-containing III-V compound semiconductor. For the use herein, " boron-containing III-V compound The semiconductor "comprising -13- 1258876 has a III-V compound semiconductor as a component element boron (B). The example consists of a composition: BaAlpGaYlni-cx-piPi.sAssf^OsaSl, 〇$β<ΐ, 〇$γ<; ι ' (Χα + β + γυ, (^δ<1) represents a compound; and is composed of: Β α A 1 β G a γ I nj α - ρ · γ ρ δ δ N s ( 〇 < a S 1,0 < β < 1,0 S γ < 1,0 < α + β + γ < 1 , (^δ <1) represents a compound. When a boron-containing III-V compound semiconductor is mixed Crystals contain large elemental changes> When mixed, 'mixed crystal layers with a uniform composition ratio are more difficult to form (see iwao Teramoto, in; March 30, 199, published by Baihukan _ "Introduction to Semiconductor Device'', page 24 of the first edition. Therefore, the boron-containing III-V compound semi-conductive body represented by the above composition formula Containing three or less than three kinds of constituent elements to form. Proportional to the desired mixed crystal layer having consistent groups. In particular, the conductor layer does not contain a constituent element which is easily oxidized (e.g., aluminum (A1)), and a group of 111-V compound > which contains boron and phosphorus (P) or arsenic (A s ) as constituent elements. Since a conductor layer which does not contain a component element which is easily oxidized (for example, aluminum (A1)) has high oxidation resistance, in the manufacture of a light-emitting device, it can be prevented from being heated by a conductor layer, and otherwise formed. A high resistance layer composed of an oxide or other substance. Therefore, it is possible to prevent the conductor property from deteriorating due to the formation of a high electric resistance layer. An example of a group III-V compound semiconductor containing boron and phosphorus as a constituent element (hereinafter, such a semiconductor may be referred to as a boron phosphide-based semiconductor), which does not contain a component element which is easily oxidized, such as aluminum (A1). Containing boron phosphide, the composition formula: BaGaYP (0<aSl, 〇^γ<ι), phosphide gallium phosphide, composition formula: BalnuPCCXo^l), borophosphide indium, and composition formula: β Pl_sNs -14- 1258876 (〇$δ<ι) represents boron oxynitride, which is a mixed crystal containing many v-group elements. Since the phosphorus-containing phosphide-based semiconductor exhibits good thermal resistance, the conductor layer formed therefrom can exhibit enhanced oxidation resistance. An example of a III-V compound semiconductor containing no easily oxidized constituent elements (such as aluminum (Α1)) and containing boron and arsenic as constituent elements (hereinafter, such a semiconductor may be referred to as a boron arsenide semiconductor) Contains arsenic phosphide represented by the composition formula: >. A conductor layer composed of such a boron arsenide semiconductor exhibits a lower conductor layer than a conductor layer composed of a III-V compound semiconductor containing boron and phosphorus (P) as a single group V element. resistance. By using a boron arsenide semiconductor, the forward voltage can be lowered. • The boron atom concentration (content) of the conductor layer is not particularly limited, and the concentration can be appropriately corrected depending on the use of the pn junction compound semiconductor light-emitting device, the luminescence wavelength, or other factors. The conductor layer may be a layer which does not contain a large amount of boron as a constituent element (for example, a boron-doped III-V compound semiconductor) 〇® exhibits sufficient resistance when the boron atom concentration is less than 1 X 1 0 19 cm ·3 The oxidized conductor layer is difficult to form. Therefore, in the manufacturing steps of the pn junction semiconductor light-emitting device described below, the bonding of the conductor layer and the permeable substrate is preferably performed in an oxygen-free inert gas atmosphere such as hydrogen (H2). ), nitrogen (n2), or argon (Ar). The conductive type of the conductor layer is preferably identical to the constituent layer in which the stacked structure is in contact with the conductor layer (i.e., the base layer formed on the conductor layer). The conductor layer preferably has a very low electrical resistance. Especially at room temperature, conductor -15-

1258876 層宜具有lxl019cnT3或更高之載子濃度，而在室溫Ί 阻率爲5xl(T2n-cm或更低。導體層的厚度宜被調整到 到 5 0 0 0 n m 0 具有如此厚度之低電阻導體層可以事先提供在堆 構中，以當作可以使發射自發光層的光穿透傳輸到外 窗層，當作電流擴散層，或當作類似的層。 在室溫下’導體層的能隙宜大於發光層的能隙。 能隙特性的優點，導體層大致上不會吸收發射自發光 光，而且會將光傳輸到透明基板，於是可以得到良好 引出效率。因此，可以製造出發高強度光之發光裝置 含硼III-V族化合物半導體（導體層）的能隙，可〇 光子能量（=h · υ )跟吸收係數的關係，或根據光子能j 射率（η)和消光係數（k)之乘積（=2 · η · k)的關係決定。 當導體層係由磷化硼系半導體或砷磷化硼（砷化 半導體其中之一）所構成時，可以得到很寬的能隙。 尤其，導體層係由磷化硼所構成的，其在室溫下 得到2.8 e V到5 · 0 e V的寬能隙。例如，在室溫下具有 或更高能隙之磷化硼導體層，可以藉由MOCVD，以2^ 到3 0 n m / m i η的形成速率形成。 當在室溫下導體層具超過5· OeV的能隙時，導儀 發光層或披覆層之間的能帶差會過度增加，此對於降 接面化合物半導體發光裝置的順向電壓或臨限電壓並 例如，當發紅光之ρ η接面化合物半導體發光裝 '之電 5 0 n m i疊結 、部之 藉由 ί層的 :的光 〇 (根據 :跟折 :硼系 :可以 2.8eV m / m i η I層和 低ρ η :不好 ί的發 -16- 1258876 光層，係由以組成式：（A1 χ G a ! - χ ) γ I η ! _ γ P表示且室溫能隙 爲2 · 0 e V的磷化鋁鎵銦所構成時，可以採用由砷磷化硼 (BPuAw: 〇：^δ<1)所構成且室溫能隙爲2.3eV之導體層。 當導體層係由磷化硼系半導體或砷化硼系半導體所構 成時，形成導體層之半導體宜爲沒有刻意摻入雜質之半導 體（即，未摻雜半導體）。 > 與傳統的半導體材料相較，如以組成式：AlxGaYAs (0<x? YS1 , X + Y=l )表示之砷化鎵鋁，和以組成式： # AlxGaYInzP(〇SX，Y，ZS1，X + Y + Z=l)表示之磷化鋁鎵銦，磷 化硼系半導體或砷化硼系半導體展現較小的離子鍵結特性 - 。因此，即使半導體是未摻雜的，也可以得到低電阻和寬 . 能隙。 例如，當採用磷化硼（ΒΡ)—種磷化硼系半導體時，在 未摻雜狀態時，很容易形成具有高達l〇19cm_3到102、ηΓ3 | 載子濃度之導體層。 傳統上，在某些情況下，可以提供刻意摻入雜質元素 • 之摻雜導體層（如鋅（Ζη)摻雜GaP)。在具有此種導體層之發 光裝置中，自導體層擴散的雜質元素（鋅）會改變發光層的 . 載子濃度和導電型。在此情形下’順向電壓（Vf)會偏離期 望的電壓，或是發光的波長會偏離期望的波長。 相較之下，當提供由未摻雜磷化硼半導體或砷化硼半 導體所構成的導體層時，自導體層擴散進入堆疊結構與導 體層接觸之成份層’或進入發光層的雜質元素量可減少’ 於是可以防止由於外部雜質元素的擴散之別的方式而造成 -17- !258876 可透光基板係由對發光波長是透明的材料所構成的。 無論是選擇何種導電型和導體層的材料，可透光基板宜由 玻璃材料形成。 玻璃材料的範例包含二氧化矽玻璃（參見 Shiro Y〇shizawa • 等人在1973年2月25日，由Asakura-shoten出版之第6 版 In〇rganic Industrial Chemistry'，中 Industrial chemistry 丨 basic lecture 5，第丨69頁）；矽酸鹽玻璃，如鈉鈣玻璃（參 見上述之 ’’Inorganic Industrial Chemisitryn 的第 205-206 頁） ® ;硼矽酸鹽玻璃，其中部分氧化矽被氧化硼取代（參見上述 之 ’’Inorganic Industrial Chemistry” 的第 207 頁），及其他的 _ 非晶質玻璃材料。特別範例包含9 6 %之二氧化矽玻璃。 - 尤其，可透光基板宜由具有很小的熱膨脹係數之玻璃 材料所構成的，如硼矽酸鹽玻璃（參見上述之"Inorganic Industrial Chemistry”的第208頁）或玻璃陶瓷。藉由使用這 > 樣的基板，可以緩合可透光基板和接合到可透光基板的堆 疊結構之間的熱應力。因此，即使當發光裝置包含，例如 ^ ，由（AlxGai_x)〇.5lri().5P所構成的發光層時，可以防止由於 熱應力之別的方式所造成之堆疊層的破裂，於是可以獲得 . 良好的熱穩定性。 可透光基板的折射率宜小於含硼III-V族化合物半導 體的折射率。尤其’可透光基板的折射率宜大於或等於1.3 ，並小於2 · 0，最好是介於1 · 5到1 . 8。 形成可透光基板之光學玻璃材料的範例’包含：毚玻 璃（K)、矽酸硼玻璃（BK)、鋇冕玻璃（BaK)、火石玻璃（F)、 -19- 1258876 鋇火石玻璃（BaF)、鑭冕玻璃（LaK)、鑭火石玻璃（LaF)，其 中可透光基板對於可由以組成式：（AlxGauhlm-yP表示 之發光層發射的鈉（Na)d-光線（ 5 8 7 nm)，具有1 .5到1 .8之 折射率（參見上述之’’Inorganic Industrial Chemistry1’的第 214 頁）。 除了玻璃材料之外，可透光基板可以由可穿透由以組 成式：（AlxGauhlm.YP表示的發光層發射的光，且允許 發射自發光層的光傳輸而不會吸收之材料形成。 形成可透光基板之非玻璃材料的範例，包含π - VI族 化合物半導體，如氧化鋅（ZnO)、硫化鋅（ZnS)和硒化鋅 (ZnSe);立方3C型、六方4H型、六方6H型、或15R型 碳化矽（SiC);藍寶石（a-Ah〇3單晶）；氮化鎵（GaN);及氮 化鋁（A1N)。 當可透光基板含有導電物質時，如GaN或ZnSe，可透 光基板的導電型宜與導體層的導電型一致。 [一種pn接面化合物半導體發光裝置的製造方法丨 首先，藉由在晶體基板上，依續堆疊下披覆層，由n 型或P型磷化鋁鎵銦所構成的發光層，上披覆層，由含砸 ΙΠ-ν族化合物半導體所構成的n型或p型導體層，形成堆 疊結構。 晶體基板的範例，包含矽（si)晶體、藍寶石（α_Αΐ2〇3 單晶）、六方或立方碳化矽（Sic)、氮化鎵（GaN)、碑化鎵 (GaAs)，及那些具有由III-V族半導體層所構成的基底層形 成在其上之晶體基板。 -20- 1258876 下披覆層、發光層、和上披覆層可以藉由傳統的氣相 成長方式形成，如mocvd(有機金屬氣相沉積法）。不用說 ，由III-V族半導體，如砷化鎵（GaAs)，所構成的緩衝層可 以先形成在晶體基板上，然後再形成這些成份層。 由含硼III-V族化合物半導體所構成的導體層，係藉 由氣相成長方式形成在上披覆層之上，如鹵素法、氫化物 ^ 法、或MOCVD(有機金屬氣相沉積法）、或分子束磊晶法 (參見 J· Solid State Chem.，133(1997)，第 269-272 頁）。 • 例如，由P型或η型磷化硼（BP)所構成的導體層，可 以藉由使用二乙基砸（分子式.（C2H5)3B)和氯化碟（分子式 • : PH3)當作材料源之常壓（接近常壓）或減壓MOC VD形成。 、 在形成由P型磷化硼（BP)所構成的導體層時，形成溫 度宜爲1 000 °C到1 200°C，而材料源供應比（ν/ΠΙ比；如ph3/ (C2H5)3B)宜爲 10 到 50。 > 在形成由η型磷化硼（BP)所構成的導體層時，形成溫 度宜爲7 0 0 °C到l〇〇〇°C，而V/III比宜大於或等於20 0，最 ®好是大於或等於4 0 0。 除了形成溫度和V/III比之外，藉由形成速率的精密控 • 制，可以形成由在室溫下展現寬能隙之磷化硼系半導體所 ^ 構成的導體層。 尤其，當M0CVD的形成速率被控制在2nm/min到30 n m / m i η時，可以形成由磷化硼所構成’且在室溫下展現 2.8eV或更寬的能隙之導體層。 如下面之說明，藉由增加導體層在形成時起始階段的 -21- 1258876 成長速率，可以形成高結晶性之導體層。 用以形成導體層之含棚ιπ-ν族化合物半導體的其中 之一範例係磷化硼。閃鋅礦晶體型磷化硼之晶格常數爲 0.4 5 4 n m，而閃鋅礦晶體型砷化硼（B A s )之晶格常數爲 0.4 7 7nm。因此，這些晶格常數並沒有與當作發光層或披覆 層之（AlxGa卜χ)γΙη丨-γΡ的晶格常數匹配。 例如’碟化錄（GaP)之晶格吊數爲〇.545nm’而以“化 鎵（GaP)爲基礎，（AlxGai-x)Yln卜γΡ與磷化之間的晶格差 φ 配約爲1 6.7 %。 在由含硼Πΐ-ν族化合物半_體（$口磷化W )所構成白勺 - 導體層，係沉積在具有如此高差配度的披覆層上之情形下 . ，可以藉由增加在成長起始階段的成長速率’製造局結晶 性之期望導體層。The layer 1258876 should have a carrier concentration of lxl019cnT3 or higher, and the resistivity at room temperature is 5xl (T2n-cm or lower. The thickness of the conductor layer should be adjusted to 50000 nm 0 with such a low thickness) The resistive conductor layer may be provided in advance in the stack as a means for transmitting light emitted from the light-emitting layer to the outer window layer, as a current diffusion layer, or as a similar layer. The energy gap should be larger than the energy gap of the light-emitting layer. The advantage of the energy gap property is that the conductor layer does not substantially absorb the emitted self-luminous light, and the light is transmitted to the transparent substrate, so that good extraction efficiency can be obtained. The high-intensity light-emitting device contains the energy gap of a boron III-V compound semiconductor (conductor layer), the relationship between the photon energy (=h · υ) and the absorption coefficient, or the photon energy (η) and extinction. The relationship between the product of the coefficient (k) (=2 · η · k) is determined. When the conductor layer is composed of a boron phosphide semiconductor or arsenic phosphide (one of the arsenic semiconductors), a wide range can be obtained. In particular, the conductor layer is phosphatized Boron consists of a wide energy gap of 2.8 e V to 5 · 0 e V at room temperature. For example, a boron phosphide conductor layer having a higher energy gap at room temperature can be MOCVD ^ The formation rate of 30 nm / mi η is formed. When the conductor layer has an energy gap of more than 5.0 OeV at room temperature, the energy band difference between the light-emitting layer or the cladding layer of the light guide is excessively increased. The forward voltage or the threshold voltage of the compound semiconductor light-emitting device of the junction-connected surface and, for example, when the red light of the π η junction compound semiconductor light-emitting device is electrically connected to the 50 nmi layer, the light of the layer is 〇 (according to: heel: boron system: can be 2.8eV m / mi η I layer and low ρ η: bad ί hair -16 - 1258876 light layer, by composition: (A1 χ G a ! - χ γ I η ! γ γ P, which is composed of arsenic phosphide (BPuAw: 〇: ^δ <1), and is composed of aluminum gallium phosphide indium having a room temperature gap of 2 · 0 e V and A conductor layer having a room gap of 2.3 eV. When the conductor layer is composed of a boron phosphide semiconductor or a boron arsenide semiconductor, the semiconductor forming the conductor layer is preferably not intentionally incorporated. Impurity semiconductor (ie, undoped semiconductor). > Compared with conventional semiconductor materials, such as aluminum gallium arsenide represented by the composition formula: AlxGaYAs (0<x? YS1, X + Y=l) Composition: # AlxGaYInzP(〇SX, Y, ZS1, X + Y + Z=l) indicates that the aluminum gallium indium phosphide, the boron phosphide semiconductor or the boron arsenide semiconductor exhibits small ion bonding characteristics. Therefore, even if the semiconductor is undoped, a low resistance and a wide energy gap can be obtained. For example, when a boron phosphide (bismuth)-boride boron-based semiconductor is used, a conductor layer having a carrier concentration of up to 10 〇 19 cm_3 to 102 and η Γ 3 | is easily formed in an undoped state. Conventionally, in some cases, a doped conductor layer (e.g., zinc (?n) doped GaP) which intentionally incorporates an impurity element can be provided. In a light-emitting device having such a conductor layer, an impurity element (zinc) diffused from the conductor layer changes the carrier concentration and conductivity type of the light-emitting layer. In this case, the forward voltage (Vf) deviates from the desired voltage, or the wavelength of the luminescence deviates from the desired wavelength. In contrast, when a conductor layer composed of an undoped boron phosphide semiconductor or a boron arsenide semiconductor is provided, the amount of impurity elements diffused from the conductor layer into the constituent layer of the stacked structure in contact with the conductor layer or into the light-emitting layer It can be reduced 'thus to prevent the diffusion of external impurity elements. -17-!258876 The permeable substrate is made of a material that is transparent to the emission wavelength. The permeable substrate is preferably formed of a glass material regardless of the conductivity type and the material of the conductor layer. Examples of glass materials include cerium oxide glass (see Shiro Y〇shizawa • et al., February 25, 1973, published by Asakura-shoten, 6th edition, In〇rganic Industrial Chemistry', in Industrial Chemistry 丨 basic lecture 5, P.69); bismuth silicate glass, such as soda lime glass (see above, ''Inorganic Industrial Chemisitryn, pp. 205-206) ® ; borosilicate glass, in which part of yttrium oxide is replaced by oxidized boron (see above) ''Inorganic Industrial Chemistry' on page 207), and other _ amorphous glass materials. The special case contains 9 6 % of bismuth dioxide glass. - In particular, the permeable substrate should have a small coefficient of thermal expansion. The glass material is composed of, for example, borosilicate glass (see page 208 of "Inorganic Industrial Chemistry" above) or glass ceramic. By using this > substrate, the thermal stress between the permeable substrate and the stacked structure bonded to the permeable substrate can be moderated. Therefore, even when the light-emitting device includes, for example, a light-emitting layer composed of (AlxGai_x) 5.5lri().5P, cracking of the stacked layer due to other methods of thermal stress can be prevented, and thus can be obtained. Good thermal stability. The refractive index of the light transmissive substrate is preferably smaller than the refractive index of the boron-containing III-V compound semiconductor. In particular, the refractive index of the light transmissive substrate is preferably greater than or equal to 1.3 and less than 2 · 0, preferably from 1.5 to 1.8. Examples of optical glass materials that form a permeable substrate include: bismuth glass (K), borosilicate glass (BK), bismuth glass (BaK), flint glass (F), -19- 1258876, flint glass (BaF) ), bismuth glass (LaK), and stellite glass (LaF), wherein the permeable substrate is for sodium (Na)d-ray (5 8 7 nm) which can be emitted by the luminescent layer represented by the composition: (AlxGauhlm-yP) , having a refractive index of 1.5 to 1.8 (see page 214 of 'Inorganic Industrial Chemistry 1' above). In addition to the glass material, the permeable substrate can be made of a permeable composition: (AlxGauhlm) .YP represents the light emitted by the light-emitting layer and allows the light emitted from the light-emitting layer to be transmitted without being absorbed. An example of a non-glass material forming a light-permeable substrate, comprising a π-VI compound semiconductor such as zinc oxide (ZnO), zinc sulfide (ZnS) and zinc selenide (ZnSe); cubic 3C, hexagonal 4H, hexagonal 6H, or 15R tantalum carbide (SiC); sapphire (a-Ah〇3 single crystal); nitrogen Gallium (GaN); and aluminum nitride (A1N). When the permeable substrate contains a conductive material, GaN or ZnSe, the conductivity type of the light transmissive substrate is preferably the same as the conductivity type of the conductor layer. [A method of manufacturing a pn junction compound semiconductor light-emitting device. First, by stacking the underlying layer on the crystal substrate, A light-emitting layer composed of n-type or P-type aluminum gallium indium phosphide, an overlying layer, and an n-type or p-type conductor layer composed of a ytterbium-ν compound semiconductor to form a stacked structure. , including bismuth (si) crystal, sapphire (α_Αΐ2〇3 single crystal), hexagonal or cubic niobium carbide (Sic), gallium nitride (GaN), intaglio gallium (GaAs), and those having a III-V semiconductor layer The underlying layer is formed on the crystal substrate formed thereon. -20- 1258876 The underlying cladding layer, the luminescent layer, and the overlying cladding layer can be formed by a conventional vapor phase growth method, such as mocvd (organic metal vapor deposition method) Needless to say, a buffer layer composed of a III-V semiconductor such as gallium arsenide (GaAs) may be formed on the crystal substrate first, and then these constituent layers are formed. From a boron-containing III-V compound semiconductor The conductor layer formed by the gas phase The method is formed on the upper cladding layer, such as a halogen method, a hydride method, or a MOCVD (organic metal vapor deposition method), or a molecular beam epitaxy method (see J. Solid State Chem., 133 (1997), P. 269-272) • For example, a conductor layer composed of P-type or n-type boron phosphide (BP) can be obtained by using diethyl hydrazine (molecular formula (C2H5) 3B) and a chlorinated disk (molecular formula). • : PH3) Formed as a source of material at atmospheric pressure (near atmospheric pressure) or reduced pressure MOC VD. When a conductor layer composed of P-type boron phosphide (BP) is formed, the formation temperature is preferably from 1 000 ° C to 1 200 ° C, and the material source supply ratio (ν / ΠΙ ratio; such as ph3 / (C2H5) 3B) should be 10 to 50. > When forming a conductor layer composed of n-type boron phosphide (BP), the formation temperature is preferably from 700 ° C to 10 ° C, and the V/III ratio is preferably greater than or equal to 20 0, most ® is better than or equal to 4 0 0. In addition to the formation temperature and the V/III ratio, a conductor layer composed of a phosphide-based semiconductor exhibiting a wide energy gap at room temperature can be formed by precise control of the formation rate. In particular, when the formation rate of MOCVD is controlled to 2 nm/min to 30 n m / m i η, a conductor layer composed of boron phosphide and exhibiting an energy gap of 2.8 eV or more at room temperature can be formed. As described below, a highly crystalline conductor layer can be formed by increasing the growth rate of the conductor layer at the initial stage of formation from -21 to 1258876. One example of a shed-type ππ-ν compound semiconductor used to form a conductor layer is boron phosphide. The sphalerite crystal type boron phosphide has a lattice constant of 0.4 5 4 n m, and the sphalerite crystal type boron arsenide (B A s ) has a lattice constant of 0.47 7 nm. Therefore, these lattice constants do not match the lattice constant of (AlxGa) γΙη丨-γΡ which is a light-emitting layer or a cladding layer. For example, the crystal lattice number of the disc recording (GaP) is 545.545nm' and the lattice difference φ between the (AlxGai-x) Yln Bu γ Ρ and the phosphating is about 1 based on the gallium (GaP). 6.7%. In the case of a conductor layer composed of a boron-containing ytterbium-ν compound semi-body ($ phosphating W), deposited on a coating layer having such a high degree of difference, can be borrowed The desired conductor layer is made by increasing the growth rate at the initial stage of growth.

例如，當由未摻雜磷化硼所構成之導體層係在70 0°c到 > 95 0°C溫度下形成在層上時，例如，由未摻雜（Al〇.5Ga().5)().5In().5P 所構成的披覆層，在成長起始階段的成長速率宜爲 泰 20nm/min 到 30nm/min 。 如在此處所使用的，成長速率係將導體層的層厚度除 . 以得到該厚度所需之時間而推算到的値。 . 上述的增加成長速率係被特別採用，直到層厚度到達 1 Onm到2 5nm。接著，在成長速率減少到小於20nm/min下 ，繼續晶體成長，直到得到期望的厚度，於是形成導體層 〇 當導體層係在超過3 0 n m / m i n的成長速率下成長，直到 -22- Ί258876 六方4H型、六方6H型、或15R型碳化矽（SiC);藍寶石 (α-Α1203單晶）；氮化鎵（GaN);及氮化鋁（A1N)。當採用由 此種單晶所構成的基板時，導體層和可透光基板可以彼此 相互接合，使得位在其間之晶格差配可以儘可能減小。藉 由接合特徵的優點，可以減少在接合接合層和可透光基板 時，施加在發光層上的應力。 ^ 例如，磷化硼（晶格常數= 0.4 5 4nm)的（1 10)晶面之晶面 間距爲0.3 20nm，而纖鋅礦型晶體氮化鎵之a軸晶格常數 • 爲〇 . 3 1 9nm。因此，當由磷化硼所構成的導體層被接合到 由氮化鎵（00 0 1 )晶面所構成的可透光基板時，將導體層和 * 基板放在適當的位置加熱，例如4 5 0 °c，使得形成接合層 . 之磷化硼的（Π0)晶面和形成可透光基板之GaN的a軸位在 相同方向。 當使用由玻璃材料所構成的可透光基板時，經陽極接 > 合方式，可以將導體層和可透光基板彼此相互接合。 當導體層和可透光基板經由陽極接合方式彼此相互接 ® 合時，應用到當作可透光基板之玻璃板的負（-)電壓宜爲 100V到1 2 00V。當應用電壓增加時，接合可以更容易執行 ‘ 。但是，接合產品的良率會減少。因此，應用電壓宜爲2 0 0 V 到7 0 0 V，最好是3 0 0 V到5 0 0 V。 對於經由陽極接合方式之接合，導體層和可透光基板 宜在加熱層和基板時彼此相互接合在一起。加熱有利於接 合。 加熱溫度宜爲2 0 0 °c到7 0 〇 r。當在更高的加熱溫度接 -24- 1258876 合時，應用到導體層和可透光基板的電壓可要求更低。 在經由陽極接合方式彼此相互接合導體層和可透光基 板之情形下，可透光基板宜由含有鹼性成份之玻璃材料所 構成。這樣的玻璃材料範例包含矽酸硼玻璃，如鈉鈣玻王离 〇 在它們當中，含有硼當作成份之矽酸硼玻璃，對於也For example, when a conductor layer composed of undoped phosphide is formed on a layer at a temperature of 70 ° C to > 95 ° C, for example, by undoped (Al 〇 . 5 Ga ( ). 5) The coating layer composed of ().5In().5P should have a growth rate of 20 nm/min to 30 nm/min at the initial stage of growth. As used herein, the growth rate is obtained by dividing the layer thickness of the conductor layer by the time required to obtain the thickness. The above increased growth rate is particularly employed until the layer thickness reaches 1 Onm to 25 nm. Then, after the growth rate is reduced to less than 20 nm/min, the crystal growth is continued until the desired thickness is obtained, thereby forming a conductor layer, and the conductor layer grows at a growth rate exceeding 30 nm/min until -22-Ί258876 Hexagonal 4H type, hexagonal 6H type, or 15R type tantalum carbide (SiC); sapphire (α-Α1203 single crystal); gallium nitride (GaN); and aluminum nitride (A1N). When a substrate composed of such a single crystal is used, the conductor layer and the light-permeable substrate can be bonded to each other such that the lattice difference therebetween can be minimized. By virtue of the bonding features, the stress applied to the luminescent layer when bonding the bonding layer and the permeable substrate can be reduced. ^ For example, the interplanar spacing of the (1 10) crystal plane of boron phosphide (lattice constant = 0.4 5 4 nm) is 0.3 20 nm, and the a-axis lattice constant of the wurtzite crystal GaN is 〇. 3 1 9nm. Therefore, when a conductor layer composed of boron phosphide is bonded to a light-permeable substrate composed of a gallium nitride (00 0 1 ) crystal face, the conductor layer and the * substrate are heated at appropriate positions, for example, 4 50 ° C, so that the (Π0) crystal plane of the phosphide forming the bonding layer and the a-axis of the GaN forming the light-permeable substrate are in the same direction. When a light-permeable substrate composed of a glass material is used, the conductor layer and the light-permeable substrate can be bonded to each other via an anode connection. When the conductor layer and the permeable substrate are bonded to each other via anodic bonding, the negative (-) voltage applied to the glass plate serving as the permeable substrate is preferably 100V to 1 2 00V. When the applied voltage is increased, the joint can be performed more easily. However, the yield of the bonded product will decrease. Therefore, the applied voltage should be from 2 0 0 V to 700 V, preferably from 300 V to 500 V. For bonding via anodic bonding, the conductor layer and the permeable substrate are preferably bonded to each other when the layer and the substrate are heated. Heating facilitates bonding. The heating temperature should be from 2 0 ° ° to 7 0 〇 r. When applied at a higher heating temperature of -24 to 1258876, the voltage applied to the conductor layer and the permeable substrate may be lower. In the case where the conductor layer and the light-permeable substrate are bonded to each other via anodic bonding, the light-permeable substrate is preferably composed of a glass material containing an alkaline component. Examples of such glass materials include borosilicate glass, such as sodium sulphate, which is contained in them, and borosilicate glass containing boron as a component.

- 含有硼當作成份元素之III-V族化合物半導體層，可以提 I 供良好的黏著性。由玻璃材料所構成的基板厚度宜爲 • 0 · 1 m m 到 1 . 0 m m。 或者，也可以藉由含有導電氧化物粉末之導電液體（糊 •狀物或膠狀物）的使用，彼此相互接合導體層和可透光基板 〇 在某一種特定模式中，導體層和可透光基板係藉由含 有銦錫合成氧化物之導電膠的使用，經由溶膠凝膠法彼此 g 相互接合。 當化合物半導體裝置的導體層具有能允許發射自發光 ® 層的光完全傳輸之寬能隙時，可以在導體層或可透光基板 的接合表面上，形成可以將發射自發光層的光反射之金屬 . 材料塗佈膜，然後可以藉由導電糊狀物的使用，接合導體 層和可透光基板。 例如，金屬材料的塗佈膜，如屬於包含鉑（Pt)、銥（Ir) 和铑（Rh)之鉑族（參見在1971年4月15日，由Hirokawa-shoten 出版之弟 5 版 ’’Duffy Inorganic Chemistry’’，第 249 頁）’銀（Ag)、鉻（Cr)等6種金屬的任何金屬，係被形成在 -25- .1258876 導體層之上。導體層的金屬膜塗佈表面之配置係要相反於 可透光基板（如玻璃基板），並且用導電糊狀物接合到可透 光基板。藉由導電層或可透光基板的接合表面上之發光金 屬膜的形成’可以製造用以發高強度光之覆置pn接面化合 物半導體發光裝置。 在導體層之上’形成第一極性之歐姆電極，而在相對 > 於發光層之導體層的相反側上，將相反極性之歐姆電極提 供在堆疊結構的另一成份層上（如緩衝層或披覆層）。歐姆 # 電極可以藉由任何習知的方法形成，如濺鍍或氣相沉積。- A III-V compound semiconductor layer containing boron as a constituent element can provide good adhesion. The thickness of the substrate composed of glass material is preferably from 0. 1 m m to 1.0 m m. Alternatively, the conductor layer and the permeable substrate may be bonded to each other by a conductive liquid (paste or gel) containing a conductive oxide powder, in a certain mode, the conductor layer and the permeable layer The optical substrate is bonded to each other by a sol-gel method by using a conductive paste containing an indium tin synthetic oxide. When the conductor layer of the compound semiconductor device has a wide energy gap capable of allowing complete transmission of light emitted from the luminescent layer, the light emitted from the luminescent layer can be reflected on the bonding surface of the conductor layer or the permeable substrate. Metal. The material is coated with a film, which can then be bonded to the conductor layer and the permeable substrate by the use of a conductive paste. For example, a coating film of a metal material, such as a platinum group containing platinum (Pt), iridium (Ir), and rhodium (Rh) (see, on April 15, 1971, published by Hirokawa-shoten, version 5'' Duffy Inorganic Chemistry'', p. 249) Any metal of six metals, such as silver (Ag) and chromium (Cr), is formed on the conductor layer of -25-.1258876. The metal film coating surface of the conductor layer is disposed opposite to the light permeable substrate (e.g., glass substrate) and bonded to the light permeable substrate with a conductive paste. The pn junction compound semiconductor light-emitting device for emitting high-intensity light can be manufactured by the formation of the light-emitting metal film on the bonding surface of the conductive layer or the light-permeable substrate. An ohmic electrode of a first polarity is formed over the conductor layer, and an ohmic electrode of opposite polarity is provided on another component layer of the stacked structure (such as a buffer layer) on the opposite side of the conductor layer opposite to the light-emitting layer Or covering layer). The ohmic # electrode can be formed by any conventional method such as sputtering or vapor deposition.

例如，當堆疊結構包含依續堆疊之由η型（AlxGauxHIm-YPFor example, when the stacked structure contains η-type (AlxGauxHIm-YP)

* 所構成的下披覆層，發光層，由p型（AlxGa^xhlm-YP所 . 構成的上披覆層，和由p型磷化硼所構成的導體層時，P 型歐姆電極（正電極）係被提供在導體層上，而η型歐姆電 極（負電極）則被提供在相對於發光層之導體層的相反側上 | 之另一成份層上；即，在下披覆層上。 例如，在由磷化硼系半導體或砷化硼系半導體所構成 ® 的η型導體層上，可以由金（Au)合金，如金（Au)_鍺（Ge) ’ 形成η型歐姆電極。 . 例如，在由磷化硼系半導體或砷化硼系半導體所構成 的Ρ型導體層上，可以由傳統所採用的鎳（Ni)(參見德國 (西德）專利第1 1 624 8 6號）、鎳合金，金（Au)-鋅（Zn)合金、 金（Au)-鈹（Be)合金、或類似的合金。 當形成具有多重層結構之歐姆電極時，最上層宜由金 (Au)或鋁（A1)形成，以利於焊接。在形成具有三層結構之 -26- .1258876 歐姆電極的情形下’提供在底層和最上層之間的中間層係 由過渡金屬（如，鈦（Ti)或鉬（Mo))或鉛（Pt)形成的。 如上所述’經由在導體層和可透光基板接合之後，歐 姆電極的形成，可以製造出pil接面化合物半導體發光裝置 • 。在本發明中’在導體層和可透光基板接合之後，用於堆 疊結構之氣相成長的晶體基板最好要移除。藉由晶體基板 | 的移除，可以製造出對於光引出到外部展現很高效率之pn 接面化合物半導體發光裝置。 • 尤其’當晶體基板係具有窄能隙且會吸收發射自發光 層的光之GaAs基板時，藉由移除晶體基板，可以製造展現 - 高發光強度之Pn接面化合物半導體發光裝置。 • 晶體基板可以經由傳統的蝕刻技術移除。尤其，G a A s 晶體基板可以含有氨水和過氧化氫水溶液之液體混合物， 經由濕蝕刻移除。 > 相較之下，例如，當晶體基板係由允許發射自發光層 的光傳輸之材料所構成的磷化鎵（GaP)基板時，不用刻意移 ^ 除晶體基板，就可以製造展現高發光強度之pn接面化合物 半導體發光裝置。 , 例如，因爲磷化鎵晶體基板具有導電性，所以第一極 性之歐姆電極係提供在磷化鎵晶體基板的背面，而相反極 性之歐姆電極則提供在堆疊結構成份層之上（如，導體層） ，因此可以製造展現高發光強度之Pn接面化合物半導體發 光裝置。 下面將參考一種pn接面化合物半導體發光裝置之製 -27- 1258876 造方法的範例，更詳細的說明本發明Pn接面化合物 發光裝置之製造方法。在該方法中，堆疊結構係形 將發射自η型發光層的光吸收之晶體基板上（如GaA ，然後根據該堆疊結構，製造對於光引出到外部展 的效率之pn接面化合物半導體發光裝置。 (1 )藉由Μ 0 C V D法，在晶體基板上，例如，鋅摻: ^ GaAs晶體基板，依續堆疊由Ρ型（AlxGauU.sIno.i 成的下披覆層，由（AlxGanh.sIno.sP所構成的發光 • 由η型（AlxGauh.sIno.sP所構成的上披覆層’於是 異質（DH)接面發光部分（（J· Korean Association of • Growth)，2001，Voll. 11，No. 5，p.207-210)。 ^ 無需多言，p型GaAs緩衝層可以先形成在P型* The underlying cladding layer, the light-emitting layer, the p-type ohmic electrode (p-type ohmic electrode, and the upper cladding layer composed of p-type (AlxGa^xhlm-YP) and the conductor layer composed of p-type phosphide The electrode) is provided on the conductor layer, and the n-type ohmic electrode (negative electrode) is provided on the other component layer on the opposite side of the conductor layer with respect to the light-emitting layer; that is, on the lower cladding layer. For example, on an n-type conductor layer composed of a boron phosphide-based semiconductor or a boron arsenide-based semiconductor, an n-type ohmic electrode can be formed of a gold (Au) alloy such as gold (Au)_germanium (Ge). For example, on a ruthenium-type conductor layer composed of a boron phosphide-based semiconductor or a boron arsenide-based semiconductor, nickel (Ni) which is conventionally used can be used (see German (West German) Patent No. 1 1 624 8 6). ), nickel alloy, gold (Au)-zinc (Zn) alloy, gold (Au)-bismuth (Be) alloy, or similar alloy. When forming an ohmic electrode with multiple layers, the uppermost layer should be made of gold (Au Or aluminum (A1) is formed to facilitate soldering. Provided in the case of forming a -26-.1258876 ohm electrode having a three-layer structure The intermediate layer between the layer and the uppermost layer is formed of a transition metal such as titanium (Ti) or molybdenum (Mo) or lead (Pt). As described above, after bonding between the conductor layer and the permeable substrate, With the formation of the ohmic electrode, a pil junction compound semiconductor light-emitting device can be manufactured. In the present invention, after the conductor layer and the light-permeable substrate are bonded, the vapor-grown crystal substrate for the stacked structure is preferably removed. By removing the crystal substrate|, it is possible to manufacture a pn junction compound semiconductor light-emitting device that exhibits high efficiency for light extraction to the outside. • Especially when the crystal substrate has a narrow energy gap and absorbs light emitted from the light-emitting layer In the case of a GaAs substrate, a Pn junction compound semiconductor light-emitting device exhibiting high light intensity can be manufactured by removing the crystal substrate. • The crystal substrate can be removed by a conventional etching technique. In particular, the G a A s crystal substrate can contain A liquid mixture of aqueous ammonia and aqueous hydrogen peroxide is removed via wet etching. > In contrast, for example, when the crystal substrate is light-transmitted from the light-emitting layer When a gallium phosphide (GaP) substrate is formed of a material, a pn junction compound semiconductor light-emitting device exhibiting high luminous intensity can be manufactured without intentionally removing the crystal substrate. For example, since the gallium phosphide crystal substrate has conductivity Therefore, the first polarity ohmic electrode is provided on the back surface of the gallium phosphide crystal substrate, and the opposite polarity ohmic electrode is provided on the stacked structural component layer (for example, the conductor layer), so that Pn exhibiting high luminous intensity can be manufactured. The compound semiconductor light-emitting device of the present invention will be described in more detail with reference to an example of a method for fabricating a pn junction compound semiconductor light-emitting device, -27 to 1258876, to explain in more detail the method for producing the light-emitting device of the Pn junction compound of the present invention. In the method, the stacked structure is formed on a crystal substrate that is emitted from the light absorption of the n-type light-emitting layer (such as GaA, and then according to the stacked structure, a pn junction compound semiconductor light-emitting device that is efficient for light extraction to the external display is fabricated. (1) By Μ 0 CVD method, on a crystal substrate, for example, a zinc-doped: ^ GaAs crystal substrate, a stack of underlying layers (AlxGauU.sIno.i), by (AlxGanh.sIno) The luminescence of .sP • The η-type (the upper cladding layer composed of AlxGauh.sIno.sP) is then the heterogeneous (DH) junction illuminating part (J. Korean Association of • Growth), 2001, Voll. No. 5, p. 207-210). ^ Needless to say, the p-type GaAs buffer layer can be formed first in the P type.

GaAs晶體基板上。 (2) 接著，在雙異質（D Η)接面發光部分的上披覆層 | 藉由Μ Ο C V D法，氣相成長由η型未摻雜磷化硼所 導體層，於是形成包含雙異質（DH)接面發光部分和 •之堆疊結構。 (3) 然後，經由陽極接合方式，彼此相互接合成爲 . 構最上表面的導體層和由低熔點玻璃所構成的無色 板。 (4) 藉由蝕刻，自堆疊結構移除用以形成堆疊結構' 基板。 之後，經由下列程序形成歐姆電極，以製造發 半導體 成在會 s基板） 現很高 雜Ρ型 ;Ρ所構 層，和 形成雙 Crystal 鏡摻雜 之上， 構成的 導體層 堆疊結 透明基 ^ GaAs 光裝置 -28-On a GaAs crystal substrate. (2) Next, on the double heterogeneous (D Η) junction surface of the light-emitting portion | by Μ CVD method, vapor phase growth of the n-type undoped phosphide conductor layer, thus forming a double heterogeneity (DH) The junction light-emitting portion and the stacking structure. (3) Then, via the anodic bonding method, the conductor layer of the uppermost surface and the colorless plate composed of the low-melting glass are bonded to each other. (4) removed from the stacked structure by etching to form a stacked structure 'substrate. Thereafter, an ohmic electrode is formed through the following procedure to fabricate a semiconductor to be a s substrate; a very high impurity type; a germanium layer, and a double crystal mirror doping, and the conductor layer is stacked to form a transparent base. GaAs optical device-28-

1258876 (5 )將p型歐姆電極直接形成在 層的表面上’而該表面係藉由移 (6) 之後，藉由蝕刻移除下披覆 對應要形成η型歐姆電極之區域 的η型磷化硼層。 (7) 在該曝露的導體層之上，直 製造ρη接面化合物半導體發光裝 如上所述，藉由移除GaAs基 歐姆電極，而在相對於發光層之 一歐姆電極，可以製造光可以經 射之pn接面化合物半導體發光| 合物半導體發光裝置，可以製造 例如，所謂將發射自發光層 出的覆置型發光裝置，可經由下 型歐姆電極和p型歐姆電極，兩 ，並使可透光基板的面朝上（朝夕 金屬防撞墊電極，使η型和p型 連接到電路基板。 或者，藉由將ρη接面化合物 幹上，而可透光基板側面對柄幹 電極分別焊接到對應的外部電極 裝置。在此情形下，當在柄幹上 可透光基板，發射自發光層的光 )型GaAs緩衝層或下披覆 :GaAs基板所曝露的表面 層、發光層、和上披覆層 的部分，於是曝露出上述 接形成η型歐姆電極，以 e置。 :板，並在導體層上形成一 導體層的相反側上形成另 由可透光基板側的平面發 I置。藉由採用ρη接面化 覆晶型發光裝置。 ，經由可透光基板之光引 列程序製造。使提供的η 電極都面對電路基板配置 f )。在各歐姆電極上形成 歐姆電極經由金屬防撞墊 半導體發光裝置放置在柄 ，然後將η型和p型歐姆 ，也可以製造類似的發光 提供反射鏡，以反射經由 時’可以完全利用發射自 -29- 1258876 發光層的光，而製造出高亮度的發光裝置，如LED燈和光 源。 [範例] <範例1 > 下面將藉由範例1，詳細說明本發明，其中由未摻雜η 型砷磷化硼所構成的導體層和由玻璃材料所構成的可透光 ^ 基板彼此相互接合，以形成ρη接面化合物半導體發光裝置 〇 Φ 第1圖爲具有ρη接面雙異質（DH)接面結構，且形成在 晶體基板上之堆疊結構Π範例的橫截面圖。 。首先，經由下列程序，形成構成Ρ η接面化合物半導體 . 發光裝置1 0(以下將該元件稱爲LED晶粒）之堆疊結構1 1 〇 堆疊結構1 1係在鋅（Zn)摻雜p型砷化鎵（GaAs)單晶基 _ 板10 0的（100)晶面上，依序堆疊下列各層所形成的：鋅摻 雜 p型 G a A S緩衝層1 0 1、由鋅摻雜磷化鋁鎵銦混晶 麵^ ((A1 〇.7。Ga〇.3 0)0.5。In。.5。P)所構成的下披覆層 1〇2、由 (Alo.MGaowksoIno.soP所構成的未摻雜發光層1〇3、 ^ 及由（Alo.ToGao.^o.wIno.wP所構成的硒（Se)摻雜η型上披 胃 jf 1 04(# M J. Korean Association of Crystal Growth, 11(5) (2001)， P.207-210) 01258876 (5) The p-type ohmic electrode is directly formed on the surface of the layer' and the surface is removed by etching (6), and the n-type phosphorus corresponding to the region where the n-type ohmic electrode is to be formed is removed by etching. Boron layer. (7) On the exposed conductor layer, the directly fabricated pn junction compound semiconductor light-emitting device is as described above, and by removing the GaAs-based ohmic electrode, the light can be made with respect to one of the ohmic electrodes of the light-emitting layer. a pn junction compound semiconductor light-emitting device that emits a semiconductor light-emitting device, for example, a so-called light-emitting device that emits a self-luminous layer, which can be passed through a lower-type ohmic electrode and a p-type ohmic electrode. The surface of the optical substrate faces upward (the metal anti-collision pad electrode is connected to the circuit substrate by n-type and p-type. Or, by drying the pn junction compound, the side surface of the transparent substrate is soldered to the stem electrode respectively Corresponding external electrode device. In this case, when the substrate is permeable to light on the handle, the light-emitting GaAs buffer layer or the underlying layer is emitted from the light-emitting layer: the surface layer, the light-emitting layer, and the upper surface of the GaAs substrate are exposed. The portion of the cladding layer is exposed to the above-mentioned n-type ohmic electrode to be placed at e. The plate is formed on the opposite side of the conductor layer to form a conductor layer on the opposite side of the light-permeable substrate side. The flip-chip light-emitting device is formed by using a pn junction. , manufactured by a light indexing procedure of a light transmissive substrate. The supplied η electrodes are all facing the circuit substrate configuration f). Forming an ohmic electrode on each ohmic electrode via a metal bumper semiconductor light-emitting device placed on the handle, and then n-type and p-type ohms, it is also possible to manufacture a similar illumination to provide a mirror for reflection through the 'full utilization of the emission from - 29- 1258876 Light from the luminescent layer to produce high-brightness illuminators such as LED lights and light sources. [Example] <Example 1> The present invention will be described in detail below by way of Example 1, in which a conductor layer composed of undoped n-type arsenic phosphide and a light-transmitting substrate composed of a glass material are mutually Joining each other to form a pn junction compound semiconductor light-emitting device 〇Φ Fig. 1 is a cross-sectional view showing an example of a stacked structure having a pη junction double heterojunction (DH) junction structure and formed on a crystal substrate. . First, a stack structure of a light-emitting device 10 (hereinafter referred to as an LED die) is formed through the following procedure. The stacked structure 1 1 is in a zinc (Zn) doped p type. On the (100) crystal plane of the gallium arsenide (GaAs) single crystal substrate _ plate 10, the following layers are sequentially stacked: zinc-doped p-type Ga a AS buffer layer 1 0 1 , phosphating by zinc doping Aluminum gallium indium mixed crystal surface ^ ((A1 〇.7.Ga〇.3 0) 0.5. In..5. P) composed of the lower cladding layer 〇2, composed of (Alo.MGaowksoIno.soP Undoped luminescent layer 1〇3, ^ and selenium (Se) doped with (Alo.ToGao.^o.wIno.wP) n-type upper stomach jf 1 04(# M J. Korean Association of Crystal Growth , 11(5) (2001), P.207-210) 0

層1 0 1到1 0 4係藉由傳統的減壓M 0 c V D法’在7 2 0 °C 下，氣相成長在基板loo上。 在上披覆層1 〇 4之上’沉積未摻雜11型砷磷化硼 -30- 1258876 (BASq.()8P().92)層，以形成導體層1〇5。 藉由使用三乙基硼（分子式：（c 2 Η 5) 3 B )當作硼（B )來源 、氫化砷氣體（分子式：AsH3)當作砷（As)來源、及氫化磷 (分子式：PH3)當作磷（P)來源之常壓（接近常壓）有機金屬化 學氣相沉積法（MOCVD)，形成由未摻雜 η型砷磷化硼 (BAso.qsPq·92)所構成的導體層105。導體層1〇5的厚度被調 整至8 5 0 n m ° 下面將詳細說明形成導體層1 0 5之方法。 採用形成具有室溫能隙約4.3eV之磷化硼（BP)相同的 條件。換言之，未摻雜η型砷磷化硼（B A S 〇 . 〇 8 P 0 . 9 2 )的晶體 成長，起始條件爲：V/III((AsH3 + PH3)/((C2H5)3B)濃度比） 爲8 00，成長溫度爲700°C，而成長速率爲25nm/min。 未摻雜η型砷磷化硼（B A s 〇, 〇 8 P 〇. 9 2 )的晶體成長，係在 25nm/min的成長速率下進行8分鐘。當層厚度到達2〇〇nm 時’將成長速率下降到15nm/min，並且在下降的成長速率 下繼續晶體成長。 最後，當導體層1 〇 5的厚度到達8 5 0 n m時，結束晶體 成長。 如此形成的導體層1 0 5發現具有3 · 5 e V之室溫能隙。 在室溫下之載子濃度和電阻率分別爲lxl〇2()cm-3和2xl〇·2 Ω · c m。 導體層105具有平坦的表面，經由減少導體層105在 形成時的起始階段成長速率，可以形成平坦的表面。 在導體層1 0 5和上披覆層1 〇 4之間的接面介面附近區 -31- 1258876 披覆層102的表面。在曝露的下披覆層102之整個表面上 ’藉由傳統的真空蒸鍍或電子束沉積法，依續沉積金（Au)-鈹（Be)合金膜、鎳（Ni)膜、和金（An)膜。 以習知的微影製程技術爲基礎，藉由選擇性製作圖案 ’如第2圖所示，p型歐姆電極1 0 7也可以當作焊接墊電 極，用以在下披覆層1 0 2之上表面的角落部分提供導線連 、 接。 i 藉由蝕刻移除下披覆層102、發光層103、和上披覆層 # 1 〇 4對應要形成n型歐姆電極1 0 8之區域的部分，於是曝 露導體層105的表面（具有可透光基板106之接面介面的相 反面）。 _ 藉由習知的微影製程技術和選擇性圖案製作，在經由 蝕刻所曝露的導體層105之表面上，形成由金-鍺（Au-Ge) 真空蒸鍍膜所構成的η型歐姆電極1 〇 8。 | 切割堆疊結構1 1，於是製造出各自具有上視圖爲方形 (3 0 0 μιηχ 3 0 0 μΓη)之ρη接面化合物半導體發光裝置（LED晶 ❿粒）1 〇。 第4圖爲包含範例1的LED晶粒之發光裝置範例的橫 β 截面圖。 提供已製作出圖案之導線電路l〇9a和109b的支架109 〇 暫時固定LED晶粒1 0，使得可透光基板1 06面朝上， 及P型和η型歐姆電極107和108分別面對導線電路i〇9b 和1 0 9 a。然後位置保持固定，藉由金屬防撞墊1 1 0的調整 -33- 1258876 ’分別將p型和n型歐姆電極1 〇 7和1 Ο 8電性連接到導線 電路1 0 9 b和1 〇 9 a，因此將L E D晶粒1 0放置在支架1 0 9上 〇 接著’用無色透明的環氧樹脂1丨1封裝如此放置的LED 晶粒1 〇 ’於是製造出發光裝置1 2。 對於用環氧樹脂1 1 1封裝LED晶粒1 0方面，環氧樹 > 脂1 1 1成形，使得當作LED晶粒1 0的發光面之可透光基 板1 〇 6的上表面和側表面，被具有半圓形橫截面之半球狀 # 透鏡所圍繞，使得半球的頂點位在LED 1 0中心軸上。 當使順向元件操作電流（2 0 m A )，藉由提供支架1 0 9上 之導線電路1 0 9 a和1 〇 9 b，流過p型和η型歐姆電極1 0 7 和1〇8之間時，LED晶粒10發中心波長約爲610nm的紅 橙光。 導體層1 0 5係由具有寬能隙和低電阻之砷磷化硼所形 > 成的，而可透光基板1 0 6則被提供在L E D晶粒1 0中。因 此’除了 P型歐姆電極1 〇 7的投影區域以外，在發光層1 0 3 Φ 的實際整個表面都可以看到發光。 可以表示除了上述的投影區域以外之發射自發光層 ^ 1 03的光之光發射近場圖案，其實際上具有非常均勻的強 度。 藉由典型的積分球量測，各晶粒的發光亮度（發光強度） 爲320 m cd。再者，藉由直接提供在低電阻導體層105上之 η型歐姆電極1 〇 8的優點，順向電壓（v f)低達2.3 V，因此 在ΙΟμΑ的逆向電流下，可以獲得超過8V的高逆向電壓。 -34- 1258876 如上所述’根據本發明之LED晶粒1 Ο，展現很低的順 向電流和電阻，促進裝置操作電流流動，及對於光引出到 外部展現很高的效率。因此，該LED晶粒可以發高強度的 光。 經由採用此種LED晶粒，可以提供可發高強度的光之 發光裝置。 ^ <範例2> LED晶粒20不同於範例1的LED晶粒，其中未摻雜N # 型磷化硼層係被提供當作導體層2 0 5。 下面將藉由範例2，詳細說明本發明。和範例1相同 之成份構件以相同的參考數字表示。 第5圖爲包含厚度2的L E D晶粒2 0之L E D燈2 2的橫 截面圖。 以類似於範例1之方法，在單晶基板1 00上，形成除 > 了導體層2 0 5以外之堆疊結構21的成份層101到104。 接著，在上披覆層104之上，形成當作導體層205之 ^未摻雜η型磷化硼（BP)層。 藉由使用三乙基硼（分子式：（C2H5)3B)當作硼（B)來源 . 及氫化磷（分子式：PH3)當作磷（P)來源之常壓（接近常壓） 有機金屬化學氣相沉積法（MOCVD)，在800 °c下，形成由 未摻雜η型磷化硼（BP)所構成的導體層2 0 5。導體層205 的厚度被調整至7 5 0nm。 如此形成的導體層2 0 5分別具有8 X 1 0 19 c irT3之載子濃 度和6χ1(Γ2Ω·(：πι之電阻率。 -35- 1258876 藉由使用傳統的橢圓儀量測導體層2 Ο 5的折射率和消 光係數，根據折射率和消光係數所得到的計算結果，導體 層2 2 5的室溫能隙約爲4.8eV。因此，該能隙可以確定發射 自發光層103的光可以穿透。 以類似於範例1之方法，藉由陽極接合方式，將成爲 堆疊結構2 1最上層表面的導體層2 0 5，接合到由矽酸硼玻 ^ 璃板所構成的可透光基板1 0 6。 在接合基板106之後，移除GaAs晶體基板100，以曝 # 露出下披覆層102的表面。 在下披覆層1 02之如此曝露的表面上，在和示於第2 圖之範例相同的位置，提供具有Au-Ge/Ni/Au三層結構之 P型歐姆電極107。 藉由蝕刻移除下披覆層1 〇 2、發光層1 0 3、和上披覆層 1 〇 4對應要形成η型歐姆電極1 〇 8之區域的部分，於是曝 | 露導體層205的表面（具有可透光基板1〇6之接面介面的相 反面）。 • 藉由習知的微影製程技術和選擇性圖案製作，在導體 層205之表面上，形成由金-鈹（Au-Be)真空蒸鑛膜所構成 > 的η型歐姆電極108。 切割堆疊結構2 1，於是製造出各自具有上視圖爲方形 (400μηιχ400μηι)之 LED 晶粒 20° 提供具有銀（Ag)膜1 12塗佈的表面之支架109。如第5 圖所示，將LED晶粒20放置在支架1〇9的Ag膜1 12之上 ，使得可透光基板1 06被當作下層（即’與支架1 〇9接觸）。 -36- .1258876 接著，個別製作P型和11型歐姆電極1 0 7和1 0 8的 線，以分別電性連接到導線電路（未圖示於第5圖）。用 氧樹脂封裝如此形成的LED晶粒20，於是製造出發光裝 22 〇 當使順向裝置操作電流（2 〇 m A )流過p型和η型歐姆 極1 0 7和1 0 8之間時，順向電壓低達2.3 e V，而在1 Ο μ A 逆向電流下，可以獲得8V的高逆向電壓，此表示具有良 的整流特性。 當使順向裝置操作電流（2 0 m A )流過時，L E D晶粒 發中心波長約爲6 1 Onm的紅橙光。藉由典型的積分球量 ，LED燈22的發光亮度（發光強度）約爲3 4 0mcd。 上述之結果表示，藉由根據本發明之L E D晶粒2 0 採用，可以提供高發光強度之LED燈22。 根據本發明之pn接面化合物半導體發光裝置，導體 係由含硼III-V族化合物半導體所構成的。因此，在pn 面化合物半導體發光裝置中，導體層和可透光基板以具 高黏著性彼此相互接合。在導體層之上，可以可靠地形 歐姆電極。 因此’本發明可以提供一種pn接面化合物半導體發 裝置’其具有很低的電阻，允許裝置操作電流很容易流 ，及對於光引出到外部展現很好的效率。 因爲導體層之室濫能隙大於發光層的能隙，所以發 自發光層的光可以穿透到可透光基板，而具有很低的傳 損失’因此可以得到很高的發光強度。 導 環 置 電 的 好 2 0 測 的 層 接 有 成 光 動 射 輸 -37- .1258876 發光裝置，尤其是用在顯示零組件或電子裝置’如光通# 裝置之高亮度LED。 【圖式簡單說明】 第1圖爲範例1之堆疊結構範例的橫截面圖。 第2圖爲範例1之pn接面化合物半導體發光裝置的結 構範例橫截面圖。 第3圖爲範例1之pn接面化合物半導體發光裝置的結 構範例上視圖。 第4圖爲含有範例1之LED晶粒的發光裝置範例橫截 面圖。 第5圖爲含有範例2之LED晶粒的燈泡範例橫截面圖 【主要元件符號說明】The layers 1 0 1 to 1 0 4 are grown on the substrate loo by a conventional decompression M 0 c V D method at 72 ° C. An undoped type 11 arsenic phosphide boron-30- 1258876 (BASq. (8P ().92) layer was deposited on top of the upper cladding layer 1 〇 4 to form a conductor layer 1〇5. By using triethylboron (molecular formula: (c 2 Η 5) 3 B ) as boron (B) source, hydrogen arsenic gas (molecular formula: AsH3) as arsenic (As) source, and hydrogen hydride (molecular formula: PH3) As a source of phosphorus (P), atmospheric pressure (near atmospheric pressure) organometallic chemical vapor deposition (MOCVD), forming a conductor layer composed of undoped n-type arsenic phosphide (BAso.qsPq·92) 105. The thickness of the conductor layer 1〇5 is adjusted to 850 nm. The method of forming the conductor layer 105 will be described in detail below. The same conditions were employed to form boron phosphide (BP) having a room temperature gap of about 4.3 eV. In other words, crystal growth of undoped n-type arsenic phosphide (BAS 〇. 〇8 P 0 . 9 2 ), starting condition: V/III ((AsH3 + PH3) / ((C2H5) 3B) concentration ratio ) is 800, the growth temperature is 700 ° C, and the growth rate is 25 nm / min. The crystal growth of undoped n-type arsenic phosphide (B A s 〇, 〇 8 P 〇. 9 2 ) was carried out for 8 minutes at a growth rate of 25 nm/min. When the layer thickness reaches 2 〇〇 nm, the growth rate is lowered to 15 nm/min, and crystal growth is continued at a decreasing growth rate. Finally, when the thickness of the conductor layer 1 〇 5 reaches 850 nm, the crystal growth is ended. The conductor layer 105 thus formed was found to have a room temperature gap of 3 · 5 e V . The carrier concentration and resistivity at room temperature were lxl 〇 2 () cm -3 and 2 x l 〇 · 2 Ω · c m , respectively. The conductor layer 105 has a flat surface, and a flat surface can be formed by reducing the growth rate of the conductor layer 105 at the initial stage of formation. The surface of the layer 102 is coated in the vicinity of the junction interface between the conductor layer 105 and the upper cladding layer 1 〇 4 -31 - 1258876. On the entire surface of the exposed lower cladding layer 102, gold (Au)-bismuth (Be) alloy film, nickel (Ni) film, and gold are successively deposited by conventional vacuum evaporation or electron beam deposition. An) film. Based on the conventional lithography process technology, by selectively patterning as shown in Fig. 2, the p-type ohmic electrode 107 can also be used as a solder pad electrode for the underlying cladding layer 1 0 2 The corners of the upper surface provide wire connections and connections. i removing the lower cladding layer 102, the light-emitting layer 103, and the upper cladding layer #1 〇4 by etching to correspond to a portion of the region where the n-type ohmic electrode 108 is to be formed, thereby exposing the surface of the conductor layer 105 (having The opposite side of the interface of the transparent substrate 106). Forming an n-type ohmic electrode 1 composed of a gold-germanium (Au-Ge) vacuum evaporation film on the surface of the conductor layer 105 exposed by etching by a conventional lithography process technique and selective patterning 〇 8. The stacked structure 1 was cut, and then a pn junction compound semiconductor light-emitting device (LED crystal grain) 1 各自 each having a square view (300 μm χ 300 μΓη) was fabricated. Fig. 4 is a transverse β cross-sectional view showing an example of a light-emitting device including the LED die of Example 1. The holder 109 for providing the patterned lead circuits l〇9a and 109b temporarily fixes the LED die 10 such that the light transmissive substrate 106 faces upward, and the P-type and n-type ohmic electrodes 107 and 108 respectively face Wire circuits i〇9b and 1 0 9 a. Then the position remains fixed, and the p-type and n-type ohmic electrodes 1 〇7 and 1 Ο 8 are electrically connected to the wire circuits 1 0 9 b and 1 分别 respectively by the adjustment of the metal crash pad 1 10 -33 - 1258876 ' 9 a, therefore, the LED die 10 is placed on the holder 1 0 9 and then the LED die 1 〇 'so placed in a colorless transparent epoxy resin 1 丨 1 is used to fabricate the light-emitting device 12 . In the case of encapsulating the LED die 10 with the epoxy resin 11 1 , the epoxy tree > grease 11 1 is formed so that the upper surface of the light-permeable substrate 1 〇 6 which serves as the light-emitting surface of the LED die 10 and The side surface is surrounded by a hemispherical #-lens having a semi-circular cross-section such that the apex of the hemisphere is on the central axis of the LED 10. When the forward element operating current (20 m A) is passed, the p-type and n-type ohmic electrodes 1 0 7 and 1 流 are supplied by providing the lead circuits 1 0 9 a and 1 〇 9 b on the holder 1 0 9 . Between 8 and 8, the LED die 10 emits red-orange light having a center wavelength of about 610 nm. The conductor layer 105 is formed of arsenic phosphide having a wide energy gap and low resistance, and the light transmissive substrate 106 is provided in the L E D crystal 10 . Therefore, except for the projection area of the P-type ohmic electrode 1 〇 7, light emission can be seen on the entire entire surface of the light-emitting layer 1 0 3 Φ. It is possible to indicate a light-emitting near-field pattern of light emitted from the light-emitting layer ^1 03 other than the above-described projection area, which actually has a very uniform intensity. The luminance (light-emitting intensity) of each crystal grain was 320 m cd by a typical integrating sphere measurement. Furthermore, by directly providing the advantage of the n-type ohmic electrode 1 〇8 on the low-resistance conductor layer 105, the forward voltage (vf) is as low as 2.3 V, so that a high voltage exceeding 8 V can be obtained under the reverse current of ΙΟμΑ. Reverse voltage. -34- 1258876 As described above, the LED die 1 according to the present invention exhibits a low forward current and resistance, promotes the operation current flow of the device, and exhibits high efficiency for light extraction to the outside. Therefore, the LED dies can emit high intensity light. By using such an LED die, it is possible to provide a light-emitting device that can emit high-intensity light. ^ <Example 2> The LED die 20 is different from the LED die of Example 1, in which an undoped N # type boron phosphide layer is provided as the conductor layer 205. The present invention will be described in detail below by way of Example 2. The same components as in Example 1 are denoted by the same reference numerals. Fig. 5 is a cross-sectional view of the L E D lamp 2 2 including the L E D crystal grain 20 of thickness 2. The composition layers 101 to 104 of the stacked structure 21 excluding the conductor layer 205 were formed on the single crystal substrate 100 in a manner similar to that of the example 1. Next, on the upper cladding layer 104, an undoped n-type boron phosphide (BP) layer as the conductor layer 205 is formed. By using triethylboron (molecular formula: (C2H5)3B) as the source of boron (B). And hydrogen hydride (molecular formula: PH3) as the source of phosphorus (P) at atmospheric pressure (near atmospheric pressure) organometallic chemical gas A phase deposition method (MOCVD), at 800 ° C, forms a conductor layer 205 composed of undoped n-type phosphide (BP). The thickness of the conductor layer 205 was adjusted to 750 nm. The conductor layers 205 thus formed have a carrier concentration of 8 X 1 0 19 c irT3 and a capacitance of 6 χ 1 (Γ2 Ω·(: πι. -35-1258876 by measuring the conductor layer 2 by using a conventional ellipsometer) The refractive index and extinction coefficient of 5, according to the calculation results obtained by the refractive index and the extinction coefficient, the room temperature gap of the conductor layer 2 25 is about 4.8 eV. Therefore, the energy gap can determine the light emitted from the light-emitting layer 103. In a manner similar to that of the example 1, the conductor layer 205 which becomes the uppermost surface of the stacked structure 2 1 is bonded to the permeable substrate composed of the borosilicate glass plate by anodic bonding. 1 0 6. After bonding the substrate 106, the GaAs crystal substrate 100 is removed to expose the surface of the lower cladding layer 102. On the surface of the lower cladding layer 102 thus exposed, and shown in FIG. In the same example, a P-type ohmic electrode 107 having a three-layer structure of Au-Ge/Ni/Au is provided. The lower cladding layer 1 is removed by etching, the light-emitting layer 1 0 3, and the upper cladding layer 1 are removed. 4 corresponds to the portion of the region where the n-type ohmic electrode 1 〇 8 is to be formed, and thus the surface of the exposed conductive layer 205 (having the opposite side of the interface of the permeable substrate 1 〇 6) • Formed by gold-铍 (Au- on the surface of the conductor layer 205 by conventional lithography process technology and selective patterning) Be) The n-type ohmic electrode 108 of the vacuum vaporized film is formed. The stacked structure 2 is cut, and then an LED die having a top view of a square shape (400 μηι 400 μηι) is produced 20°. A film having a silver (Ag) is provided. The coated surface holder 109. As shown in Fig. 5, the LED die 20 is placed over the Ag film 112 of the holder 1〇9 so that the permeable substrate 106 is regarded as the lower layer (i.e., the holder 1 〇9 contact) -36- .1258876 Next, the P-type and 11-type ohmic electrodes 1 0 7 and 1 0 8 are individually fabricated to be electrically connected to the lead circuit (not shown in Fig. 5). The thus formed LED dies 20 are encapsulated with an oxygen resin, thereby producing an illuminating device 22, which causes a forward device operating current (2 〇 m A ) to flow between the p-type and n-type ohmic poles 10 7 and 1 0 8 When the forward voltage is as low as 2.3 e V, and at a reverse current of 1 Ο μ A , a high reverse voltage of 8 V can be obtained. Good rectification characteristics. When the forward device operating current (20 m A ) flows, the LED dies emit red orange light with a center wavelength of about 6 1 Onm. The illuminance of the LED lamp 22 is achieved by a typical integrating sphere. The luminance (light-emitting intensity) is about 340 mcd. The above results show that the LED lamp 22 of high luminous intensity can be provided by the use of the LED die 20 according to the present invention. According to the pn junction compound semiconductor light-emitting device of the present invention, the conductor is composed of a boron-containing III-V compound semiconductor. Therefore, in the pn-surface compound semiconductor light-emitting device, the conductor layer and the light-permeable substrate are bonded to each other with high adhesion. Above the conductor layer, the ohmic electrode can be reliably formed. Therefore, the present invention can provide a pn junction compound semiconductor device which has a very low resistance, allows the device operation current to flow easily, and exhibits excellent efficiency for light extraction to the outside. Since the chamber energy gap of the conductor layer is larger than the energy gap of the light-emitting layer, light emitted from the light-emitting layer can penetrate to the light-permeable substrate with a low transmission loss, so that a high luminous intensity can be obtained. The good temperature of the guide ring is connected to the illuminating device -37-.1258876 illuminating device, especially for high-brightness LEDs used to display components or electronic devices such as the optical device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing an example of a stacked structure of Example 1. Fig. 2 is a cross-sectional view showing a configuration example of a pn junction compound semiconductor light-emitting device of Example 1. Fig. 3 is a top view showing an example of the structure of a pn junction compound semiconductor light-emitting device of Example 1. Fig. 4 is a cross-sectional view showing an example of a light-emitting device including the LED die of Example 1. Figure 5 is a cross-sectional view of a bulb containing the LED die of Example 2 [Explanation of main component symbols]

10 LED晶粒 11 堆疊結構 1 2 發光元件 20 led晶粒 2 1 堆疊結構 22 LED燈 100 單晶基板 10 1 緩衝層 1 02 下披覆層 1 03 發光層 1 04 上披覆層 -40- 125887610 LED die 11 Stack structure 1 2 Light-emitting component 20 LED die 2 1 Stack structure 22 LED light 100 Single crystal substrate 10 1 Buffer layer 1 02 Lower cladding layer 1 03 Light-emitting layer 1 04 Upper cladding layer -40- 1258876

1 05 導體層 1 06 可透光基板 1 07 P型歐姆電極 1 08 η型歐姆電極 1 09 支架 1 09a，109b 導線電路 110 金屬防撞墊 111 環氧樹脂 112 Ag膜 205 導體層1 05 Conductor layer 1 06 Transmissive substrate 1 07 P-type ohmic electrode 1 08 η-type ohmic electrode 1 09 Bracket 1 09a, 109b Conductor circuit 110 Metal crash pad 111 Epoxy resin 112 Ag film 205 Conductor layer

-41-41

Claims (1)

IJ58876 第941 093 1 9號「化合物半導ί ϋ裝置及其製法」專利案 (2006年2月6日修正） 十、申請專利範圍： 1. 一種ρη接面化合物半導體發光裝置，包含含有由η型 或Ρ型磷化鋁鎵銦所構成的發光層之堆疊結構，及用以 支撐堆疊結構之可透光基板，該堆疊結構和可透光性基 板係接合在一起的，其中堆疊結構包含η型或ρ型導體 層，導體層係和基板接合在一起，而且導體層係由含有 硼之III-V族化合物半導體所構成。 2 ·如申請專利範圍第1項之ρ η接面化合物半導體發光裝 置，其中導體層在室溫下的能隙大於發光層的能隙。 3 ·如申請專利範圍第1項之ρη接面化合物半導體發光裝 置，其中導體層係由含有硼之未刻意加入雜質元素之未 摻雜III-V族化合物半導體所構成。 4 ·如申請專利範圍第1到第3項中任一項之ρ η接面化合 物半導體發光裝置，其中導體層係由含有砷和硼之111 _ V族化合物半導體所構成。 5 .如申請專利範圍第1到第3項中任一項之ρη接面化合 物半導體發光裝置，其中導體層係由含有磷和硼之ζην 族化 合物半 導體所 構成。 6 ·如申請專利範圍第5項之ρη接面化合物半導體發光裝 置，其中導體層係由磷化硼所構成。 7 ·如申請專利範圍第1到第3項中任一項之ρη接面化合 物半導體發光裝置，其中導體層係由含有雙晶之含硼 1258876 111 - V族化合物半導體所構成。 8 .如申請專利範圍第7項之pn接面化合物半導體發光裝 置，其中雙晶的每一個單晶都有含硼ΠΙ-V族化合物半 導體的（1 11)晶面做爲雙晶面。 9· 一種pn接面化合物半導體發光裝置的製造方法，包含 下列步驟： * 在晶體基板上，藉由依序堆疊下披覆層，由η型或 Ρ型磷化鋁鎵銦所構成的發光層、上披覆層、和由含硼 III-V族化合物半導體所構成的η型或ρ型導體層，形 成堆疊結構之步驟，及將導體層接合到可透光基板之步 . 驟。 . 10.如申請專利範圍第9項之pn接面化合物半導體發光裝 胃的製造方法，其中在將導體層接合到可透光基板之後 ，移除晶體基板。 1 1 ·如I Φ請專利範圍第9項之pn接面化合物半導體發光裝置 的氣:七方法，其中藉由以2〇nm/min到30nm/min的成長 速率之晶體成長，形成導體層，直到導體層的厚度到達 lOnm ©I 25nm爲止，然後再以小於20nm/min的成長速 、 率之晶體成長，直到導體層具有期望厚度。 -2-IJ58876 No. 941 093 1 9 "Compound semi-conducting device and its preparation method" patent (amended on February 6, 2006) X. Patent application scope: 1. A pn-joint compound semiconductor light-emitting device comprising η a stacked structure of a light-emitting layer composed of a type or bismuth type aluminum gallium phosphide, and a light-permeable substrate for supporting the stacked structure, the stacked structure and the light-transmitting substrate are bonded together, wherein the stacked structure comprises η The p-type or p-type conductor layer, the conductor layer and the substrate are bonded together, and the conductor layer is composed of a III-V compound semiconductor containing boron. 2. The pn junction compound semiconductor light-emitting device of claim 1, wherein the energy gap of the conductor layer at room temperature is greater than the energy gap of the light-emitting layer. 3. The pn junction compound semiconductor light-emitting device according to claim 1, wherein the conductor layer is composed of an undoped group III-V compound semiconductor containing boron which is not intentionally added with an impurity element. The π junction junction semiconductor light-emitting device according to any one of claims 1 to 3, wherein the conductor layer is composed of a 111 _V compound semiconductor containing arsenic and boron. The pn junction semiconductor light-emitting device according to any one of claims 1 to 3, wherein the conductor layer is composed of a ζη family compound semiconductor containing phosphorus and boron. 6. The pn junction compound semiconductor light-emitting device of claim 5, wherein the conductor layer is composed of boron phosphide. The pn junction semiconductor light-emitting device according to any one of claims 1 to 3, wherein the conductor layer is composed of a boron-containing 1258876 111-V compound semiconductor containing a double crystal. 8. The pn junction compound semiconductor light-emitting device according to claim 7, wherein each of the single crystals of the twin crystal has a (11) crystal plane containing a boron-germanium-V compound semiconductor as a twin plane. 9. A method of fabricating a pn junction compound semiconductor light-emitting device, comprising the steps of: * illuminating a light-emitting layer composed of n-type or germanium-type aluminum gallium indium phosphide on a crystal substrate by sequentially stacking a lower cladding layer; An upper cladding layer, and an n-type or p-type conductor layer composed of a boron-containing III-V compound semiconductor, a step of forming a stacked structure, and a step of bonding the conductor layer to the light-permeable substrate. 10. The method of fabricating a pn junction compound semiconductor light-emitting device according to claim 9, wherein the crystal substrate is removed after bonding the conductor layer to the light-permeable substrate. 1 1 · I Φ Please refer to the gas of the pn junction compound semiconductor light-emitting device of the ninth patent range: a method in which a conductor layer is formed by crystal growth at a growth rate of 2 〇 nm/min to 30 nm/min, Until the thickness of the conductor layer reaches lOnm ©I 25 nm, then the crystal growth at a growth rate of less than 20 nm/min is continued until the conductor layer has a desired thickness. -2-
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