CN103066032A - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

Info

Publication number
CN103066032A
CN103066032A CN2012100658411A CN201210065841A CN103066032A CN 103066032 A CN103066032 A CN 103066032A CN 2012100658411 A CN2012100658411 A CN 2012100658411A CN 201210065841 A CN201210065841 A CN 201210065841A CN 103066032 A CN103066032 A CN 103066032A
Authority
CN
China
Prior art keywords
package parts
openings
horizontal size
opening
packaging part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012100658411A
Other languages
English (en)
Other versions
CN103066032B (zh
Inventor
陈孟泽
林俊成
蔡钰芃
林修任
郑明达
刘重希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103066032A publication Critical patent/CN103066032A/zh
Application granted granted Critical
Publication of CN103066032B publication Critical patent/CN103066032B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/12Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16113Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/814Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06572Auxiliary carrier between devices, the carrier having an electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1431Logic devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1432Central processing unit [CPU]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1434Memory
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

一种器件包括:封装部件,具有顶面上方的导电部件,以及聚合物区域,模制在第一封装部件的顶面上方。多个开口从聚合物区域的顶面延伸到聚合物区域中,其中,导电部件中的每一个通过多个开口中的一个露出。多个开口包括:第一开口,具有第一水平尺寸;以及第二开口,具有第二水平尺寸,第一水平尺寸不同于第二水平尺寸。本发明还提供了封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本发明一般地涉及半导体领域,更具体地来说,涉及封装件及其形成方法。
背景技术
在传统的叠层封装(package-on-package,POP)工艺中,其中,将接合第一器件管芯的顶部封装件接合至底部封装件。底部封装件还可以具有封装在其中的器件管芯。通过采用PoP工艺,可以增加封装的集成级别。
由于顶部封装件和底部封装件的每一个都包括具有不同热膨胀系数(CTE)的不同材料,所以在形成顶部封装件和底部封装件之后,可以在顶部封装件和底部封装件的任一个或两个中发生翘曲。翘曲可以为正翘曲,其中,封装件的中心部分大于边缘部分。相反,翘曲可以为负翘曲,其中,翘曲的中心部分低于边缘部分。在接合顶部封装件和底部封装件之后,作为翘曲结果可以发生虚焊(cold joint),并且一些连接可能失败。当顶部封装件的翘曲与底部封装件的翘曲与不匹配时,情况恶化。例如,当顶部封装件具有正翘曲且底部封装件具有负翘曲时或者顶部封装件具有负翘曲且底部封装件具有正翘曲时,增加了虚焊发生的机会。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种器件,包括:第一封装部件,包括顶面上方的导电部件;聚合物区域,模制在所述第一封装部件的所述顶面上方;以及多个开口,从所述聚合物区域的顶面延伸到所述聚合物区域中,其中,通过所述多个开口的每一个露出所述导电部件的一个,以及其中,所述多个开口包括:第一开口,具有第一水平尺寸;和第二开口,具有第二水平尺寸,所述第一水平尺寸不同于所述第二水平尺寸。
在该器件中,所述第一水平尺寸大于所述第二水平尺寸,以及其中,所述第一开口比所述第二开口更接近所述第一封装部件的中心。
在该器件中,所述第一水平尺寸小于所述第二水平尺寸,以及其中,所述第一开口比所述第二开口更接近所述第一封装部件的中心。
在该器件中,所述第一水平尺寸在所述第二水平尺寸的大约50%至大约90%之间。
该器件还包括:器件管芯,接合至所述第一封装部件并模制在所述聚合物区域中。
该器件还包括:第二封装部件,通过多个包含焊料的连接件接合至所述第一封装部件,其中,每一个包含焊料的连接件都包括延伸到所述多个开口中的一个的部分。
在该器件中,在从所述第一封装部件的中心延伸到所述第一封装部件的边缘的方向上,所述多个开口的水平尺寸逐渐增加或减小。
根据本发明的另一方面,提供了一种器件,包括:封装件,包括:第一封装部件,包括所述第一封装部件的顶面上方的导电部件;器件管芯,接合至所述第一封装部件的顶面;模塑料,模制在所述第一封装部件的顶面上方,其中,所述器件管芯模制在所述模塑料中;以及多个开口,位于所述模塑料中,其中,所述导电部件的每一个通过所述多个开口的一个露出,以及其中,所述多个开口具有彼此不同的至少两个水平尺寸;以及第二封装部件,位于所述封装件的上方并通过多个焊料区域接合至所述导电部件,其中,所述多个焊料区域的部分延伸到所述多个开口中。
在该器件中,与所述多个开口中更接近所述封装件的边缘和角部的外侧开口相比,所述多个开口中更接近所述封装件的中心的内侧开口具有更大的尺寸。
在该器件中,所述封装件和所述第二封装部件具有负翘曲。
在该器件中,与所述多个开口中更接近所述封装件的边缘和角部的外侧开口相比,所述多个开口中更接近所述封装件的中心的内侧开口具有更小的尺寸。
在该器件中,所述封装件和所述第二封装部件具有正翘曲。
在该器件中,所述封装件包括多个环形区域,通过所述多个环形区域的外侧区域围绕所述多个环形区域的内侧区域,以及其中,所述多个环形区域中的同一区域中的多个开口的部分具有相同的水平尺寸,以及其中,所述多个环形区域中的不同区域中的多个开口部分具有不同的水平尺寸。
在该器件中,所述至少两个水平尺寸包括第一水平尺寸和第二水平尺寸,所述第一水平尺寸小于所述第二水平尺寸的大约90%。
根据本发明的又一方面,提供了一种方法,包括:评估第一封装部件和封装件,以确定包括所述第一封装部件和所述封装件的组合封装件的翘曲状态,其中,所述翘曲状态包括正翘曲和负翘曲,以及其中,所述封装件包括:器件管芯和第二封装部件,其中,所述器件管芯接合至所述第二封装部件的顶面;和聚合物区域,模制在所述第二封装部件的顶面上方,其中,所述器件管芯模制在所述聚合物区域中;以及在所述聚合物区域中形成多个开口以露出所述第二封装部件的顶面上方的导电部件,其中,形成所述多个开口的步骤包括:响应于所述正翘曲,使所述多个开口中更接近所述封装件的中心的内侧开口比所述多个开口的外侧开口具有更小的水平尺寸;以及响应于所述负翘曲,使所述多个开口中更接近所述封装件的中心的内侧开口比所述多个开口的外侧开口具有更大的水平尺寸。
该方法包括:响应于作为评估步骤结果的在所述第一封装部件和所述封装件之间没有翘曲,形成具有基本上相等的水平尺寸的多个开口。
该方法还包括:通过包含焊料的区域将所述第一封装部件接合至所述封装件,其中,所述包含焊料的区域延伸到所述多个开口中。
在该方法中,所述聚合物区域包括模塑料,以及其中,所述模塑料的顶面不低于所述器件管芯的顶面。
在该方法中,形成所述多个开口的步骤包括:将所述封装件划分为多个环状区域,所述多个环形区域的外侧区域围绕所述多个环形区域的内侧区域,以及其中,将所述多个环形区域的同一区域中的多个开口形成为具有相同的水平尺寸,并且其中,将所述多个环形区域的不同区域中的多个开口形成为具有不同的水平尺寸。
在该方法中,所述多个开口中的内侧开口和外侧开口包括较小的开口和较大的开口,以及其中,所述多个开口中的较小开口具有第一水平尺寸,所述第一水平尺寸小于所述多个开口的较大开口的大约90%。
附图说明
为了更完整地理解本实施例及其优点,现在结合附图进行以下描述作为参考,其中:
图1至图6是根据各个实施例的制造封装件过程中的中间阶段的截面图和俯视图。
具体实施方式
以下详细讨论本发明的实施例的制造和使用。然而,应该理解,本发明提供了许多可以在各种具体环境下实现的可应用发明概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
根据各个实施例提供了封装件及其制造方法。示出了形成封装件的中间阶段。讨论了实施例的变型例。在各个附图和说明性实施例中,类似的标号用于表示类似元件。
参照图1,提供封装部件10。在实施例中,封装部件10包括插入板(interposer)。在可选实施例中,封装部件10包括封装基板。封装部件10可以包括由半导体材料形成的基板11,诸如硅、硅锗、碳化硅、砷化镓或其他通用的半导体材料。可选地,基板11由介电材料形成。基板11还可以为层压基板,该层压基板包括层压电介质膜。封装部件10被配置为将第一表面10A上的连接件12电连接至第二表面10B上的导电部件16,其中,表面10A和10B是封装部件10的相对表面。在一些实施例中,连接件12可以包括诸如焊球、金属柱、凸块底部金属化层的导电部件。可选地,连接件12包括金属柱和相邻焊料区域。例如,导电部件16可以为金属焊盘。封装部件10其中可以包括金属线/通孔14,并且还可以包括形成在基板11中的通孔。
封装部件20通过连接件12接合至封装部件10。封装部件20可以为管芯,因此可选地,在本文中将在以后称为管芯20,但是该封装部件还可以为另一种类型的封装部件(诸如封装件)。管芯20可以为其中包括集成电路器件(诸如晶体管、电容器、电感器、电阻器(未示出)等)的器件管芯。此外,管芯20可以为包括核心电路的逻辑管芯,并且可以为例如中央计算单元(CPU)管芯、图形管芯或存储管芯。管芯20与连接件12的接合可以为焊接接合或直接金属与金属接合(诸如铜与铜接合)。底部填充物18可以散布在管芯20和封装部件10之间的间隙中。
参照图2,聚合物24被涂覆在管芯20和封装部件10上方。在示例性实施例中,聚合物24包括模塑料,因此在下文称为模塑料24,尽管该聚合物还可以由诸如模制底部填充物(MUF)、环氧树脂等的其他材料形成。模塑料24可以与管芯20的顶面和边缘接触,并且可以与封装部件10的顶面接触。模塑料24可以利用例如压缩模制或转印模制而模制到管芯20和封装部件10上。模塑料24的顶面24A可以高于管芯20的顶面20A,并且管芯20可以完全密封到模塑料24中。任选地,可以实施研磨以去除模塑料24的多个部分(在管芯20的顶面20A上方的部分),因此露出顶面20A,并且该顶面20A与模塑料24的顶面24A平齐。
在图3中,连接件26形成在导电部件16上方,并且可以通过诸如金属线/通孔14的连接而电连接至连接件12。连接件26和管芯20可以位于封装部件10的相对面上方。连接件26可以为焊球,其被放置在导电部件16上方。对焊球26实施回流。由此形成也被称为封装部件的底部封装件30。底部封装件30包括边缘30A和处于边缘30A中间的中心30B。中心30B还可以为封装部件10的中心。
图4A示出了模塑料24中的开口32的形成。可以通过钻孔、蚀刻等形成开口32。通过开口32露出封装部件10的顶面上的导电部件34。导电部件34可以为金属焊盘,并且可以电连接至连接件12和/或连接件26。开口32包括内侧开口32A和外侧开口32B,其中,外侧开口32B比内侧开口32A更加远离封装件30的中心30B(其还可以为封装部件10的中心)。开口32具有相互不同的多个水平尺寸(诸如D1和D2),其中,水平尺寸D1为外侧开口32B的尺寸,而水平尺寸D2为内侧开口32A的尺寸。在一些实施例中,水平尺寸D1小于水平尺寸D2,例如,小于D2的大约90%或80%。水平尺寸D1还可以在大约50%的尺寸D2和大约90%的尺寸D2之间。在可选实施例中,水平尺寸D2小于水平尺寸D1,并且可以小于尺寸D1的90%或80%,或者可以在尺寸D1的大约50%和大约90%之间。
图4B示出了根据示例性实施例的封装件30的俯视图。在俯视图中,封装件30包括多个环形区域,它们被示意性示为相邻虚线环之间的区域。多个环形区域的内侧区域被多个环形区域的外侧区域包围。在一些实施例中,开口32的水平尺寸与它们属于的环形区域相关。例如,多个环形区域中的同一区域中的开口32可以具有相同的水平尺寸,并且多个环形区域中的不同区域中的开口32可具有不同(或相同)的水平尺寸。可选地,开口32可以认为与包围中心30B的多个环对准。从接近封装件30的边缘30A和/或角部30C的外侧环到接近中心30B的内侧环,水平尺寸被表示为D1、D2...Dn,其中,D1为最外侧环中的开口32的水平尺寸,以及Dn是最内侧环中的开口32的水平尺寸。根据开口32的数量以及封装件30中开口32的不同水平尺寸的总数,整数n可以等于3、4、5或者任何大于5的整数。
注意,尽管开口32的俯视图形状为圆形,因此水平尺寸D1至Dn为直径,但开口32可以具有其他俯视图形状,诸如正方形、长方形、六边形、八边形等,并且水平尺寸D1至Dn可以为开口32的最大水平尺寸。此外,在开口32的侧壁倾斜的实施例中,只要使用相同标准测量所有水平尺寸,开口32的顶部尺寸或底部尺寸(如图4A所示)可以用于比较的目的。
在一些实施例中,接近边缘30A和角部30C的外侧环形区域中开口32的水平尺寸Dn...D2、D1小于接近中心30B的内侧环形区域中开口32的水平尺寸,并且每一个外侧环形区域的水平尺寸都可以等于或小于内侧环形区域中开口32的水平尺寸。例如,可以具有关系Dn>...>D2>D1,但是相邻环形区域中的开口32的水平尺寸可以彼此相等。可选地,外侧环形区域中的每个开口32的水平尺寸可以等于或大于内侧环形区域中开口32的水平尺寸。例如,可以具有关系Dn<...<D2<D1,但是相邻环形区域中的开口32的水平尺寸可以彼此相等。
图5和图6示出了封装部件130与封装部件30的接合。示出了封装部件130的截面图。在一个实施例中,封装部件130还可以为封装件,该封装部件可以包括封装部件110和接合在封装部件110上方的管芯120,并且在管芯120上形成模塑料124。管芯120可以为器件管芯,并且封装部件110可以为插入板、封装基板等。在可选实施例中,封装部件130可以为器件管芯。封装部件130可以在底面具有连接件126。连接件126还可以为其中包括焊料的各种形式,并且可以为焊球、金属柱和其上的焊料罩(solder cap)等。
图5和图6还示出了封装部件30和130的接合,其中,连接件126(其位置被设计为与开口32(图4A)的位置对准)接合至封装30中的导电部件34。图5示出了封装部件30和130具有负翘曲,这意味着中心间隔S1小于边缘间隔S2。中心间隔S1为接近封装部件30和130的中心的封装部件30和130的部分之间的间隔,而边缘间隔S2为接近封装部件30和130的边缘的封装部件30和130的部分之间的间隔。注意,尽管图5示出了封装部件130具有负翘曲且封装部件30基本上为平直的,但它们可以为其他情况,其中,封装部件30和130的每一个都可以具有正翘曲、负翘曲或者可以基本上平坦的。在整个描述中,不管对应的封装部件30和130的翘曲如何,只要间隔S1小于间隔S2,封装部件30和130的组合都可以指具有负翘曲。
在图5中,如果所有开口32(被连接件126填充,也参照图4A)都具有相同尺寸,则更可能在外侧开口32处发生虚焊。在实施例中,如果针对接合的封装部件30和130发生负翘曲,则内侧开口32的尺寸被设计为大于外侧开口32的尺寸。因此,内侧开口32可以容纳更多的焊料,并且对于封装部件30和130来说更容易具有比外侧间隔(诸如S2)小的内侧间隔(诸如S1)。因此,封装部件130的内部可以接近封装部件30,并且减小了在外侧开口32中发生虚焊的机会。
图6示出了封装部件30和130的接合,其中,封装部件30和130具有正翘曲,这意味着中心间隔S1大于边缘间隔S2。注意,尽管图6示出了封装部件130具有正翘曲且封装部件30基本上为平直的,但可以存在其他情况,其中,封装部件30和130的每一个都可以具有正翘曲、负翘曲或者基本上平坦。在整个描述中,不管对应封装部件30和130的翘曲状态如何,只要中心间隔S1大于边缘间隔S2,封装部件30和130的组合都可以指具有正翘曲。
在图6中,如果所有开口32(被连接件126填充,也参照图4A)具有相同尺寸,则更加可能在内侧开口32处发生虚焊。在实施例中,如果将针对接合的封装部件30和130发生正翘曲,则内侧开口32的尺寸被设计为小于外侧开口32的尺寸。因此,外侧开口32可以容纳更多的焊料,并且对于封装部件30和130来说与诸如S1的内侧间隔相比更容易具有更小的外侧间隔(诸如S2)。因此,封装部件130的外部可以接近封装部件30,并且减小了在内侧开口32中发生虚焊的机会。
在一个实施例中,在封装件30(图4)中形成开口32之前,可以进行评估以确定接合的封装部件30和130的翘曲状态。在评估中,评估封装件30和130的轮廓以确定接合之后的封装部件30和130具有正翘曲还是负翘曲。还可以通过接合样本封装部件30和130的实验来进行评估。如果将产生负翘曲,则内侧开口32的水平尺寸被设计为大于外侧开口32的水平尺寸。相反,如果将产生正翘曲,则内侧开口32的水平尺寸被设计为小于外侧开口32的水平尺寸。然而,如果对于接合的封装件30和封装部件130没有发生翘曲,则穿过整个封装件30的开口32可以具有基本相同的尺寸。没有翘曲的情况可以包括封装件30和封装部件130不具有翘曲的情况或者封装件30和封装部件130在相同方向上翘曲并具有基本相同的曲率。通过调整底部封装件30中开口32的尺寸,可以减小虚焊的可能性。
根据实施例,一种器件包括:封装部件,在顶面上具有导电部件;以及聚合物区域,模制在第一封装部件的顶面上方。多个开口从聚合物区域的顶面延伸到聚合物区域中,其中,通过多个开口的每一个暴露导电部件的每一个。多个开口包括:第一开口,具有第一水平尺寸;第二开口,具有不同于第一水平尺寸的第二水平尺寸。
根据其他实施例,一种器件包括封装件,封装件包括:第一封装部件,在第一封装部件的顶面上方包括导电部件;器件管芯,接合至第一封装部件的顶面;以及模塑料,模制在第一封装部件的顶面上方,其中,器件管芯模制在模塑料中。封装件还包括模塑料中的多个开口。导电部件的每一个通过多个开口的每一个露出。多个开口具有彼此不同的至少两个水平尺寸。第二封装部件位于封装件的上方并通过多个焊料区域接合至导电部件,多个焊料区域的多个部分延伸到多个开口中。
根据又一些实施例,一种包括:评估第一封装部件和封装件,以确定包括所述第一封装部件和封装件的组合封装件的翘曲状态,其中,翘曲状态包括正翘曲和负翘曲。封装件包括:器件管芯和第二封装部件,其中,器件管芯接合至第二封装部件的顶面;和聚合物区域,模制在第二封装部件的顶面上方,其中,器件管芯模制在聚合物区域中。该方法还包括:在聚合物区域中形成多个开口以露出第二封装部件的顶面上方的导电部件。形成多个开口的步骤包括:响应于正翘曲,使多个开口中更接近封装件的中心的内侧开口比多个开口的外侧开口具有更小的水平尺寸;以及响应于负翘曲,使多个开口中更接近封装件的中心的内侧开口比多个开口的外侧开口具有更大的水平尺寸。
尽管详细描述了实施例及其优点,但应该理解,在不背离由所附权利要求限定的实施例的主旨和范围的情况下,可以进行各种改变、替换和变化。此外,本申请的范围不限于说明书中描述的工艺、机器、制造、物质组成、装置、方法和步骤的特定实施例。本领域的技术人员应该容易地从发明中理解,可以根据本发明利用现有或稍后开发的实施与本文所描述对应实施例基本相同的功能或实现基本相同的结果的工艺、机器、制造、物质组成、装置、方法和步骤。因此,所附权利要求用于在它们的范围内包括这些工艺、机器、制造、物质组成、装置、方法和步骤。此外,每个权利要求都构成独立的实施例,并且各个权利要求和实施例的组合都在本发明的范围之内。

Claims (10)

1.一种器件,包括:
第一封装部件,包括顶面上方的导电部件;
聚合物区域,模制在所述第一封装部件的所述顶面上方;以及
多个开口,从所述聚合物区域的顶面延伸到所述聚合物区域中,其中,通过所述多个开口的每一个露出所述导电部件的一个,以及其中,所述多个开口包括:
第一开口,具有第一水平尺寸;和
第二开口,具有第二水平尺寸,所述第一水平尺寸不同于所述第二水平尺寸。
2.根据权利要求1所述的器件,其中,所述第一水平尺寸大于所述第二水平尺寸,以及其中,所述第一开口比所述第二开口更接近所述第一封装部件的中心。
3.根据权利要求1所述的器件,其中,所述第一水平尺寸小于所述第二水平尺寸,以及其中,所述第一开口比所述第二开口更接近所述第一封装部件的中心。
4.根据权利要求1所述的器件,其中,所述第一水平尺寸在所述第二水平尺寸的大约50%至大约90%之间。
5.根据权利要求1所述的器件,还包括:器件管芯,接合至所述第一封装部件并模制在所述聚合物区域中。
6.根据权利要求1所述的器件,还包括:第二封装部件,通过多个包含焊料的连接件接合至所述第一封装部件,其中,每一个包含焊料的连接件都包括延伸到所述多个开口中的一个的部分。
7.根据权利要求1所述的器件,其中,在从所述第一封装部件的中心延伸到所述第一封装部件的边缘的方向上,所述多个开口的水平尺寸逐渐增加或减小。
8.一种器件,包括:
封装件,包括:
第一封装部件,包括所述第一封装部件的顶面上方的导电部件;
器件管芯,接合至所述第一封装部件的顶面;
模塑料,模制在所述第一封装部件的顶面上方,其中,所述器件管芯模制在所述模塑料中;以及
多个开口,位于所述模塑料中,其中,所述导电部件的每一个通过所述多个开口的一个露出,以及其中,所述多个开口具有彼此不同的至少两个水平尺寸;以及
第二封装部件,位于所述封装件的上方并通过多个焊料区域接合至所述导电部件,其中,所述多个焊料区域的部分延伸到所述多个开口中。
9.根据权利要求8所述的器件,其中,与所述多个开口中更接近所述封装件的边缘和角部的外侧开口相比,所述多个开口中更接近所述封装件的中心的内侧开口具有更大的尺寸。
10.一种方法,包括:
评估第一封装部件和封装件,以确定包括所述第一封装部件和所述封装件的组合封装件的翘曲状态,其中,所述翘曲状态包括正翘曲和负翘曲,以及其中,所述封装件包括:
器件管芯和第二封装部件,其中,所述器件管芯接合至所述第二封装部件的顶面;和
聚合物区域,模制在所述第二封装部件的顶面上方,其中,所述器件管芯模制在所述聚合物区域中;以及
在所述聚合物区域中形成多个开口以露出所述第二封装部件的顶面上方的导电部件,其中,形成所述多个开口的步骤包括:
响应于所述正翘曲,使所述多个开口中更接近所述封装件的中心的内侧开口比所述多个开口的外侧开口具有更小的水平尺寸;以及
响应于所述负翘曲,使所述多个开口中更接近所述封装件的中心的内侧开口比所述多个开口的外侧开口具有更大的水平尺寸。
CN201210065841.1A 2011-10-24 2012-03-13 封装件及其形成方法 Active CN103066032B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/280,157 US9030022B2 (en) 2011-10-24 2011-10-24 Packages and methods for forming the same
US13/280,157 2011-10-24

Publications (2)

Publication Number Publication Date
CN103066032A true CN103066032A (zh) 2013-04-24
CN103066032B CN103066032B (zh) 2016-02-10

Family

ID=48108596

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210065841.1A Active CN103066032B (zh) 2011-10-24 2012-03-13 封装件及其形成方法

Country Status (3)

Country Link
US (2) US9030022B2 (zh)
KR (1) KR101494494B1 (zh)
CN (1) CN103066032B (zh)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8912651B2 (en) 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9842798B2 (en) * 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US9576888B2 (en) * 2013-03-12 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Package on-package joint structure with molding open bumps
KR20140119522A (ko) * 2013-04-01 2014-10-10 삼성전자주식회사 패키지-온-패키지 구조를 갖는 반도체 패키지
US9691745B2 (en) 2013-06-26 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure for forming a package on package (PoP) structure and method for forming the same
US9252076B2 (en) * 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9633869B2 (en) 2013-08-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with interposers and methods for forming the same
KR20150096949A (ko) * 2014-02-17 2015-08-26 삼성전자주식회사 반도체 패키지 및 그의 형성방법
KR20160019252A (ko) 2014-08-11 2016-02-19 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법
US10032704B2 (en) 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
TWI651824B (zh) * 2017-04-07 2019-02-21 台灣積體電路製造股份有限公司 半導體結構及方法
US11304290B2 (en) 2017-04-07 2022-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures and methods
WO2019116457A1 (ja) * 2017-12-13 2019-06-20 三菱電機株式会社 半導体装置及び電力変換装置
KR102454214B1 (ko) 2018-08-02 2022-10-12 삼성전자주식회사 반도체 패키지
DE102019202718B4 (de) * 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dünnes Dual-Folienpackage und Verfahren zum Herstellen desselben
DE102019202715A1 (de) 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Folienbasiertes package mit distanzausgleich
DE102019202721B4 (de) 2019-02-28 2021-03-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 3d-flexfolien-package
JP2021090030A (ja) * 2019-12-06 2021-06-10 富士電機株式会社 半導体装置及び半導体装置の製造方法
US11515224B2 (en) 2020-01-17 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with enlarged through-vias in encapsulant

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1532931A (zh) * 2003-03-24 2004-09-29 精工爱普生株式会社 半导体装置及制法、半导体封装、电子设备及制法、电子仪器
JP2007281129A (ja) * 2006-04-05 2007-10-25 Toshiba Corp 積層型半導体装置
CN102157476A (zh) * 2010-03-04 2011-08-17 日月光半导体制造股份有限公司 具有单侧基板设计的半导体封装及其制造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101685652B1 (ko) * 2009-12-17 2016-12-13 삼성전자주식회사 반도체 패키지들, 그들의 적층 구조와 그 제조 방법들
US8508954B2 (en) * 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1532931A (zh) * 2003-03-24 2004-09-29 精工爱普生株式会社 半导体装置及制法、半导体封装、电子设备及制法、电子仪器
JP2007281129A (ja) * 2006-04-05 2007-10-25 Toshiba Corp 積層型半導体装置
CN102157476A (zh) * 2010-03-04 2011-08-17 日月光半导体制造股份有限公司 具有单侧基板设计的半导体封装及其制造方法

Also Published As

Publication number Publication date
KR20130045138A (ko) 2013-05-03
US9627369B2 (en) 2017-04-18
US20130099385A1 (en) 2013-04-25
US20150243642A1 (en) 2015-08-27
US9030022B2 (en) 2015-05-12
KR101494494B1 (ko) 2015-02-17
CN103066032B (zh) 2016-02-10

Similar Documents

Publication Publication Date Title
CN103066032B (zh) 封装件及其形成方法
US10629579B2 (en) Package-on-package with cavity in interposer
US9627355B2 (en) Package-on-package structure having polymer-based material for warpage control
US20210098318A1 (en) Dam for three-dimensional integrated circuit
TWI364820B (en) Chip structure
KR101476883B1 (ko) 3차원 패키징을 위한 응력 보상층
CA2713151C (en) Semiconductor stack assembly having reduced thermal spreading resistance and methods of making same
US9343437B2 (en) Semiconductor package devices
CN104867908A (zh) 倒装芯片堆叠封装
US9041180B2 (en) Semiconductor package and method of manufacturing the semiconductor package
US20180175004A1 (en) Three dimensional integrated circuit package and method for manufacturing thereof
CN104037142A (zh) 封装对准结构及其形成方法
US20130256915A1 (en) Packaging substrate, semiconductor package and fabrication method thereof
US11776866B2 (en) Semiconductor module heatspreading lid having integrated separators for multiple chips
CN103730447A (zh) 不具有组装通孔的堆叠封装结构
US20150054150A1 (en) Semiconductor package and fabrication method thereof
CN108074895B (zh) 堆叠封装结构及其制造方法
KR101573311B1 (ko) 반도체 장치 및 이의 제조 방법
US11189557B2 (en) Hybrid package
US20220173074A1 (en) Chip Package and Method of Forming Chip Packages

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant