CN103035748A - 锗硅BiCMOS工艺中的齐纳二极管及制造方法 - Google Patents

锗硅BiCMOS工艺中的齐纳二极管及制造方法 Download PDF

Info

Publication number
CN103035748A
CN103035748A CN201210004113XA CN201210004113A CN103035748A CN 103035748 A CN103035748 A CN 103035748A CN 201210004113X A CN201210004113X A CN 201210004113XA CN 201210004113 A CN201210004113 A CN 201210004113A CN 103035748 A CN103035748 A CN 103035748A
Authority
CN
China
Prior art keywords
district
active area
region
type
deep trap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201210004113XA
Other languages
English (en)
Other versions
CN103035748B (zh
Inventor
刘冬华
胡君
段文婷
钱文生
石晶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CN201210004113.XA priority Critical patent/CN103035748B/zh
Priority to US13/734,464 priority patent/US8829650B2/en
Publication of CN103035748A publication Critical patent/CN103035748A/zh
Application granted granted Critical
Publication of CN103035748B publication Critical patent/CN103035748B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66098—Breakdown diodes
    • H01L29/66106—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

本发明公开了一种锗硅BiCMOS工艺中的齐纳二极管，N区由形成于有源区中并被N型深阱包覆；在有源区两侧的浅槽场氧底部形成有赝埋层，N区通过N型深阱和赝埋层相连接。N区的电极通过形成于赝埋层顶部的浅槽场氧中的深孔接触引出。P区由形成于有源区中的一P型离子注入区组成，P区位于N区的顶部并和N区相接触且P区的掺杂浓度大于所述N区的掺杂浓度；P区的电极通过形成于有源区顶部的金属接触引出。本发明还公开了一种锗硅BiCMOS工艺中的齐纳二极管的制造方法。本发明能与锗硅BiCMOS工艺完全集成，能为锗硅BiCMOS的电路设计提供一种稳压器件。

Description

锗硅BiCMOS工艺中的齐纳二极管及制造方法
技术领域
本发明涉及半导体集成电路制造领域，特别是涉及一种锗硅BiCMOS(Bipolar CMOS)工艺中的齐纳二极管，本发明还涉及一种锗硅BiCMOS工艺中的齐纳二极管的制造方法。
背景技术
由于现代通信对高频带下高性能、低噪声和低成本的RF组件的需求，传统的硅(Si)材料器件无法满足性能规格、输出功率和线性度新的要求，功率锗硅(SiGe)异质结双极型晶体管(HBT)则在更高、更宽的频段的功放中发挥重要作用。与砷化镓器件相比，虽然在频率上还处劣势，但SiGe HBT凭着更好的热导率和良好的衬底机械性能，较好地解决了功放的散热问题，SiGe HBT还具有更好的线性度、更高集成度；SiGe HBT仍然属于硅基技术，和CMOS工艺有良好的兼容性，SiGe BiCMOS工艺为功放与逻辑控制电路的集成提供极大的便利，也降低了工艺成本。
稳压管也是一种晶体二极管，它是利用PN结的击穿区具有稳定电压的特性来工作的。稳压管在稳压设备和一些电子电路中获得广泛的应用。把这种类型的二极管称为稳压管，以区别用在整流、检波和其他单向导电场合的二极管。稳压二极管的特点就是击穿后，其两端的电压基本保持不变。这样，当把稳压管接入电路以后，若由于电源电压发生波动，或其它原因造成电路中各点电压变动时，负载两端的电压将基本保持不变。稳压管反向击穿后，电流虽然在很大范围内变化，但稳压管两端的电压变化很小。利用这一特性，稳压管在电路中能起稳压作用。因为这种特性，稳压管主要被作为稳压器或电压基准元件使用。其伏安特性见稳压二极管可以串联起来以便在较高的电压上使用，通过串联就可获得更多的稳定电压。
发明内容
本发明所要解决的技术问题是提供一种锗硅BiCMOS工艺中的齐纳二极管，能与锗硅BiCMOS工艺完全集成，能为锗硅BiCMOS的电路设计提供一种稳压器件。本发明还提供了一种锗硅BiCMOS工艺中的齐纳二极管的制造方法。
为解决上述技术问题，本发明提供的锗硅BiCMOS工艺中的齐纳二极管，形成于硅衬底上，有源区由浅槽场氧隔离，齐纳二极管包括：
一N型深阱，形成于所述有源区中，所述N型深阱的深度大于所述浅槽场氧底部的深度、且所述N型深阱横向延伸进入所述有源区两侧的浅槽场氧底部。
N区，由形成于所述有源区中的一N型离子注入区组成，所述N区的横向尺寸小于等于所述有源区的横向尺寸、且所述N区被所述N型深阱包覆。
赝埋层，由形成于所述有源区两侧的浅槽场氧底部的N型离子注入区组成，所述赝埋层和所述N型深阱在所述浅槽场氧底部相接触，所述N区通过所述N型深阱和所述赝埋层相连接，在所述赝埋层顶部的所述浅槽场氧中形成有深孔接触，该深孔接触引出所述N区的电极。
P区，由形成于所述有源区中的一P型离子注入区组成，所述P区位于所述N区的顶部并和所述N区相接触，所述P区的掺杂浓度大于所述N区的掺杂浓度；在所述有源区顶部形成有金属接触，该金属接触和所述P区接触并引出所述P区的电极。
进一步的改进是，所述N区的工艺条件和锗硅HBT三极管的集电区的工艺条件相同。
进一步的改进是，所述P区的工艺条件和PMOS晶体管的源漏注入区的工艺条件相同。
为解决上述技术问题，本发明提供的锗硅BiCMOS工艺中的齐纳二极管的制造方法包括如下步骤：
步骤一、在硅衬底上形成浅沟槽和有源区。
步骤二、在所述有源区周侧的所述浅沟槽的底部的进行N型离子注入形成赝埋层。
步骤三、在所述浅沟槽中填入氧化硅形成浅槽场氧；在所述硅衬底的正面进行离子注入工艺形成N型深阱，所述N型深阱位于所述有源区中，所述N型深阱的深度大于所述浅槽场氧底部的深度、且所述N型深阱横向延伸进入所述有源区两侧的浅槽场氧底部；所述赝埋层和所述N型深阱在所述浅槽场氧底部相接触。
步骤四、在所述有源区中进行N型离子注入形成N区；所述N区的横向尺寸小于等于所述有源区的横向尺寸、且所述N区被所述N型深阱包覆，所述N区通过所述N型深阱和所述赝埋层相连接。
步骤五、在所述有源区中进行P型离子注入形成P区，所述P区位于所述N区的顶部并和所述N区相接触，所述P区的掺杂浓度大于所述N区的掺杂浓度。
步骤六、在所述赝埋层顶部的浅槽场氧中形成深孔接触引出所述N区的电极；在所述有源区顶部形成和所述P区接触的金属接触并引出所述P区的电极。
进一步的改进是，步骤二中所述赝埋层离子注入的注入剂量为1e14cm-2～1e16cm-2、注入能量为2KeV～50KeV、注入杂质为磷。
进一步的改进是，步骤四中所述N区的N型离子注入工艺采用锗硅HBT三极管的集电区的离子注入工艺，该工艺的条件为：注入杂质为磷、注入剂量为2e12cm-2～5e14cm-2、注入能量为30KeV～350KeV。
进一步的改进是，步骤五中所述P区的P型离子注入的工艺条件和PMOS晶体管的源漏注入的工艺条件相同。
进一步的改进是，步骤三中所述N型深阱的离子注入的注入剂量为2e12cm-2～1e14cm-2、注入能量为1500KeV～2000KeV、注入杂质为磷。
本发明齐纳二极管的N区能和锗硅HBT三极管的集电区的工艺条件相同、P区能和PMOS晶体管的源漏注入区的工艺条件相同，从而使本发明齐纳二极管能与锗硅BiCMOS工艺完全集成，能为锗硅BiCMOS的电路设计提供一种稳压器件。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是本发明实施例锗硅BiCMOS工艺中的齐纳二极管的结构示意图；
图2A-图2F是本发明实施例锗硅BiCMOS工艺中的齐纳二极管的制造方法中各步骤的器件结构示意图。
具体实施方式
如图1所示，是本发明实施例锗硅BiCMOS工艺中的齐纳二极管的结构示意图。本发明实施例锗硅BiCMOS工艺中的齐纳二极管形成于P型硅衬底101上，有源区由浅槽场氧201隔离。齐纳二极管包括：
一N型深阱202，形成于所述有源区中，所述N型深阱202的深度大于所述浅槽场氧201底部的深度、且所述N型深阱202横向延伸进入所述有源区两侧的浅槽场氧201底部。
N区301，由形成于所述有源区中的一N型离子注入区组成。所述N区301的工艺条件和锗硅HBT三极管的集电区的工艺条件相同。所述N区301的横向尺寸小于等于所述有源区的横向尺寸、且所述N区301被所述N型深阱202包覆。
赝埋层107，由形成于所述有源区两侧的浅槽场氧201底部的N型离子注入区组成，所述赝埋层107和所述N型深阱202在所述浅槽场氧201底部相接触，所述N区301通过所述N型深阱202实现和所述赝埋层107的连接，在所述赝埋层107顶部的所述浅槽场氧201中形成有深孔接触701，该深孔接触701引出所述N区301的电极。
P区601，由形成于所述有源区中的一P型离子注入区组成。所述P区601的工艺条件和PMOS晶体管的源漏注入区的工艺条件相同。所述P区601位于所述N区301的顶部并和所述N区301相接触，所述P区601的掺杂浓度大于所述N区301的掺杂浓度；在所述有源区顶部形成有金属接触702，该金属接触702和所述P区601接触并引出所述P区601的电极。在所述器件的顶部形成有顶层金属703，该顶层金属703实现器件的互连。
如图2A至图2F所示，是本发明实施例锗硅BiCMOS工艺中的齐纳二极管的制造方法中各步骤的器件结构示意图。本发明实施例锗硅BiCMOS工艺中的齐纳二极管的制造方法包括如下步骤：
步骤一、如图2A所示，采用光刻刻蚀工艺在P型硅衬底101上形成浅沟槽和有源区。刻蚀时所述有源区上方用硬质掩模层做保护，所述硬质掩模层包括氧化层102、氮化层103和氧化层104。
如图2A所示，形成所述浅沟槽之后，淀积一层氧化物并刻蚀，在所述浅沟槽的内侧面形成氧化物侧壁105，所述浅沟槽的底部表面还保留一层氧化物106.
步骤二、如图2A所示，在所述有源区周侧的所述浅沟槽的底部的进行N型离子注入形成赝埋层107。所述赝埋层107的N型离子注入工艺条件为：注入杂质为磷，注入剂量1e14cm-2～1e16cm-2，注入能量为2KeV～50KeV。
步骤三、如图2B所示，在所述浅沟槽中填入氧化硅形成浅槽场氧201。
如图2B所示，进行N型离子注入形成N型深阱202，所述N型深阱202的离子注入的注入剂量为2e12cm-2～1e14cm-2、注入能量为1500KeV～2000KeV、注入杂质为磷。形成后，所述N型深阱202的深度大于所述浅槽场氧201底部的深度、且所述N型深阱202横向延伸进入所述有源区两侧的浅槽场氧201底部。所述赝埋层107和所述N型深阱202在所述浅槽场氧201底部相接触。
步骤四、如图2C所示，在所述有源区中进行N型离子注入形成N区301，所述N区301的横向尺寸小于等于所述有源区的横向尺寸、且所述N区301被所述N型深阱202包覆。所述N区301通过所述N型深阱202实现和所述赝埋层107的连接。所述N区301的N型离子注入工艺采用锗硅HBT三极管的集电区的离子注入工艺，该工艺的条件为：注入杂质为磷、注入剂量为2e12cm-2～5e14cm-2、注入能量为30KeV～350KeV。
本发明实施例方法能和锗硅BiCMOS工艺中锗硅HBT器件以及CMOS器件一起形成即集成在同一硅衬底101。此时在形成本发明实施例齐纳二极管的区域还包括如下步骤：
如图2D所示，在所述硅衬底101的正面淀积氧化物介质层401，该氧化物介质层401用于在锗硅HBT器件的形成区域形成基区窗口；在所述硅衬底101的正面淀积锗硅外延层402，锗硅外延层402用于在锗硅HBT器件的基区。
如图2E所示，在所述硅衬底101的正面淀积另一氧化物介质层501，该另一氧化物介质层501用于在锗硅HBT器件的形成区域形成发射区窗口；在所述硅衬底101的正面淀积发射极多晶硅层502，发射极多晶硅层502用于在锗硅HBT器件的发射区。
如图2F所示，最后将所述硅衬底101的本发明实施例齐纳二极管的区域的所述氧化物介质层401、所述锗硅外延层402、所述另一氧化物介质层501和所述发射极多晶硅层502都去除。
步骤五、如图2F所示，在所述有源区中进行P型离子注入形成P区601，所述P区601位于所述N区301的顶部并和所述N区301相接触，所述P区601的掺杂浓度大于所述N区301的掺杂浓度。所述P区601的P型离子注入的工艺条件和PMOS晶体管的源漏注入的工艺条件相同。
步骤六、如图1所示，在所述赝埋层107顶部的浅槽场氧201中形成深孔接触701引出所述N区301的电极；在所述有源区顶部形成和所述P区601接触的金属接触702并引出所述P区601的电极。最后，在所述器件的顶部形成有顶层金属703，该顶层金属703实现器件的互连。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (8)

1.一种锗硅BiCMOS工艺中的齐纳二极管，形成于硅衬底上，有源区由浅槽场氧隔离，其特征在于：齐纳二极管包括：
一N型深阱，形成于所述有源区中，所述N型深阱的深度大于所述浅槽场氧底部的深度、且所述N型深阱横向延伸进入所述有源区两侧的浅槽场氧底部；
N区，由形成于所述有源区中的一N型离子注入区组成，所述N区的横向尺寸小于等于所述有源区的横向尺寸、且所述N区被所述N型深阱包覆；
赝埋层，由形成于所述有源区两侧的浅槽场氧底部的N型离子注入区组成，所述赝埋层和所述N型深阱在所述浅槽场氧底部相接触，所述N区通过所述N型深阱和所述赝埋层相连接，在所述赝埋层顶部的所述浅槽场氧中形成有深孔接触，该深孔接触引出所述N区的电极；
P区，由形成于所述有源区中的一P型离子注入区组成，所述P区位于所述N区的顶部并和所述N区相接触，所述P区的掺杂浓度大于所述N区的掺杂浓度；在所述有源区顶部形成有金属接触，该金属接触和所述P区接触并引出所述P区的电极。
2.如权利要求1所述的锗硅BiCMOS工艺中的齐纳二极管，其特征在于：所述N区的工艺条件和锗硅HBT三极管的集电区的工艺条件相同。
3.如权利要求1所述的锗硅BiCMOS工艺中的齐纳二极管，其特征在于：所述P区的工艺条件和PMOS晶体管的源漏注入区的工艺条件相同。
4.一种锗硅BiCMOS工艺中的齐纳二极管的制造方法，其特征在于，包括如下步骤：
步骤一、在硅衬底上形成浅沟槽和有源区；
步骤二、在所述有源区周侧的所述浅沟槽的底部的进行N型离子注入形成赝埋层；
步骤三、在所述浅沟槽中填入氧化硅形成浅槽场氧；在所述硅衬底的正面进行离子注入工艺形成N型深阱，所述N型深阱位于所述有源区中，所述N型深阱的深度大于所述浅槽场氧底部的深度、且所述N型深阱横向延伸进入所述有源区两侧的浅槽场氧底部；所述赝埋层和所述N型深阱在所述浅槽场氧底部相接触；
步骤四、在所述有源区中进行N型离子注入形成N区；所述N区的横向尺寸小于等于所述有源区的横向尺寸、且所述N区被所述N型深阱包覆，所述N区通过所述N型深阱和所述赝埋层相连接；
步骤五、在所述有源区中进行P型离子注入形成P区，所述P区位于所述N区的顶部并和所述N区相接触，所述P区的掺杂浓度大于所述N区的掺杂浓度；
步骤六、在所述赝埋层顶部的浅槽场氧中形成深孔接触引出所述N区的电极；在所述有源区顶部形成和所述P区接触的金属接触并引出所述P区的电极。
5.如权利要求4所述方法，其特征在于：步骤二中所述赝埋层离子注入的注入剂量为1e14cm-2～1e16cm-2、注入能量为2KeV～50KeV、注入杂质为磷。
6.如权利要求4所述方法，其特征在于：步骤四中所述N区的N型离子注入工艺采用锗硅HBT三极管的集电区的离子注入工艺，该工艺的条件为：注入杂质为磷、注入剂量为2e12cm-2～5e14cm-2、注入能量为30KeV～350KeV。
7.如权利要求4所述方法，其特征在于：步骤五中所述P区的P型离子注入的工艺条件和PMOS晶体管的源漏注入的工艺条件相同。
8.如权利要求4所述方法，其特征在于：步骤三中所述N型深阱的离子注入的注入剂量为2e12cm-2 ～1e14cm-2、注入能量为1500KeV～2000KeV、注入杂质为磷。
CN201210004113.XA 2012-01-06 2012-01-06 锗硅BiCMOS工艺中的齐纳二极管及制造方法 Active CN103035748B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201210004113.XA CN103035748B (zh) 2012-01-06 2012-01-06 锗硅BiCMOS工艺中的齐纳二极管及制造方法
US13/734,464 US8829650B2 (en) 2012-01-06 2013-01-04 Zener diode in a SiGe BiCMOS process and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210004113.XA CN103035748B (zh) 2012-01-06 2012-01-06 锗硅BiCMOS工艺中的齐纳二极管及制造方法

Publications (2)

Publication Number Publication Date
CN103035748A true CN103035748A (zh) 2013-04-10
CN103035748B CN103035748B (zh) 2015-08-19

Family

ID=48022446

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210004113.XA Active CN103035748B (zh) 2012-01-06 2012-01-06 锗硅BiCMOS工艺中的齐纳二极管及制造方法

Country Status (2)

Country Link
US (1) US8829650B2 (zh)
CN (1) CN103035748B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105576014A (zh) * 2015-12-22 2016-05-11 上海华虹宏力半导体制造有限公司 肖特基二极管及其制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1703561A2 (en) * 2005-03-15 2006-09-20 Delphi Technologies, Inc. Protection device for handling energy transients
CN101226933A (zh) * 2007-01-18 2008-07-23 上海维恩佳得数码科技有限公司 一种半导体稳压器件
CN101431073A (zh) * 2008-06-24 2009-05-13 上海贝岭股份有限公司 一种齐纳管集成电路结构及其制造方法
CN102082148A (zh) * 2009-11-26 2011-06-01 上海华虹Nec电子有限公司 Esd保护电路及其制造方法
US20110156202A1 (en) * 2009-12-31 2011-06-30 Chiu Tzuyin Parasitic Vertical PNP Bipolar Transistor in BICMOS Process

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376775B (zh) * 2010-08-26 2014-04-16 上海华虹宏力半导体制造有限公司 BiCMOS工艺中的寄生PIN器件及制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1703561A2 (en) * 2005-03-15 2006-09-20 Delphi Technologies, Inc. Protection device for handling energy transients
CN101226933A (zh) * 2007-01-18 2008-07-23 上海维恩佳得数码科技有限公司 一种半导体稳压器件
CN101431073A (zh) * 2008-06-24 2009-05-13 上海贝岭股份有限公司 一种齐纳管集成电路结构及其制造方法
CN102082148A (zh) * 2009-11-26 2011-06-01 上海华虹Nec电子有限公司 Esd保护电路及其制造方法
US20110156202A1 (en) * 2009-12-31 2011-06-30 Chiu Tzuyin Parasitic Vertical PNP Bipolar Transistor in BICMOS Process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105576014A (zh) * 2015-12-22 2016-05-11 上海华虹宏力半导体制造有限公司 肖特基二极管及其制造方法

Also Published As

Publication number Publication date
US20130175581A1 (en) 2013-07-11
CN103035748B (zh) 2015-08-19
US8829650B2 (en) 2014-09-09

Similar Documents

Publication Publication Date Title
US8748238B2 (en) Ultra high voltage SiGe HBT and manufacturing method thereof
JP2006279046A (ja) バイポーラトランジスタおよびバイポーラトランジスタの製造方法
CN102412274B (zh) 锗硅hbt工艺中垂直寄生型pnp器件及制造方法
CN103035690B (zh) 击穿电压为7-10v锗硅异质结双极晶体管及其制备方法
CN103035748B (zh) 锗硅BiCMOS工艺中的齐纳二极管及制造方法
CN102931220A (zh) 锗硅异质结双极型三极管功率器件及制造方法
CN102386218B (zh) BiCMOS工艺中的垂直寄生型PNP器件及其制造方法
CN103377918A (zh) Npn异质结双极晶体管及其制造方法
CN103137676A (zh) 一种锗硅异质结双极晶体管及其制造方法
CN102544082B (zh) 锗硅异质结npn三极管器件及制造方法
US8785977B2 (en) High speed SiGe HBT and manufacturing method thereof
CN102412286B (zh) 一种高速锗硅hbt器件结构及其制造方法
CN103035688B (zh) 一种锗硅hbt器件及其制造方法
CN102386183B (zh) BiCMOS工艺中的寄生PIN器件组合结构及制造方法
CN103050519B (zh) 锗硅hbt器件及制造方法
CN110047920B (zh) 一种横向结型栅双极晶体管及其制作方法
CN103050518B (zh) 锗硅异质结双极型晶体管及其制造方法
CN103035749B (zh) 锗硅BiCMOS中的横向齐纳二极管结构及其实现方法
CN102403343B (zh) BiCMOS工艺中的垂直寄生型PNP器件及制造方法
CN103137677B (zh) 锗硅hbt工艺中的寄生横向型pnp三极管及制造方法
CN102412313B (zh) 一种采用SiGe HBT工艺的MOS可变电容及其制作方法
CN102412311B (zh) BiCMOS工艺中的PN结变容器及制造方法
CN203415583U (zh) 一种高压npn器件
TWI559529B (zh) 半導體元件及其製造方法
CN113725290A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20140107

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI

TA01 Transfer of patent application right

Effective date of registration: 20140107

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Applicant before: Shanghai Huahong NEC Electronics Co., Ltd.

C14 Grant of patent or utility model
GR01 Patent grant