CN103137676A - 一种锗硅异质结双极晶体管及其制造方法 - Google Patents

一种锗硅异质结双极晶体管及其制造方法 Download PDF

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CN103137676A
CN103137676A CN2011103770601A CN201110377060A CN103137676A CN 103137676 A CN103137676 A CN 103137676A CN 2011103770601 A CN2011103770601 A CN 2011103770601A CN 201110377060 A CN201110377060 A CN 201110377060A CN 103137676 A CN103137676 A CN 103137676A
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bipolar transistor
heterojunction bipolar
collector region
silicon
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CN103137676B (zh
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胡君
石晶
钱文生
刘冬华
段文婷
陈帆
邱慈云
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Abstract

本发明公开了一种锗硅异质结双极晶体管,包括:P型衬底中形成有匹配层,膺埋层和集电区形成于匹配层上方,场氧区形成于膺埋层和部分集电区的上方,膺埋层和场氧区位于集电区两侧;氧化硅层形成于场氧区上方,多晶硅层形成于氧化硅层上方,基区形成于集电区和多晶硅层上方;氧化硅介质层形成于基区上方,氮化硅介质层形成于氧化硅介质层上方,发射区形成于基区和氮化硅介质层上方,隔离侧墙形成于氧化硅介质层、氮化硅介质层和发射区的两侧;膺埋层通过深接触孔引出,深接触孔中具有钛层或氮化钛层,填有金属钨。本发明还公开了一种锗硅异质结双极晶体管的制造方法。本发明的锗硅异质结双极晶体管能提高器件的击穿电压。

Description

一种锗硅异质结双极晶体管及其制造方法
技术领域
本发明涉及半导体制造领域,特别是涉及一种锗硅异质结双极晶体管。本发明还涉及一种锗硅异质结双极晶体管的制造方法。
背景技术
现代通信对高频带下高性能、低噪声和低成本的RF(射频)组件的需求,传统的Si(硅)材料器件无法满足性能规格、输出功率和线性度新的要求,功率SiGe HBT(硅锗异质结双极晶体管)在更高、更宽的频段的功放中发挥重要作用。与砷化镓器件相比,虽然在频率上还处劣势,但SiGe HBT凭着更好的热导率和良好的衬底机械性能,较好地解决了功放的散热问题,SiGe HBT还具有更好的线性度、更高集成度;SiGe HBT仍然属于硅基技术和CMOS工艺有良好的兼容性,SiGe BiCMOS工艺为功放与逻辑控制电路的集成提供极大的便利,也降低了工艺成本。
国际上目前已经广泛采用SiGe HBT作为高频大功率功放器件应用于无线通讯产品,如手机中的功率放大器和低噪声放大器等。为了提高射频功率放大器的输出功率,在器件正常工作范围内通过提高工作电流和提高工作电压都是有效的方式。对于用于锗硅HBT,高耐压器件可使电路在相同功率下获得较小电流,从而降低功耗,因而需求广泛。因此在如何保持器件的特征频率的同时进一步提高SiGe HBT耐压越来越成为锗硅HBT器件的研究热点。
发明内容
本发明要解决的技术问题是提供一种锗硅异质结双极晶体管能提高器件的击穿电压。为此,本发明还提供了一种锗硅异质结双极晶体管的制造方法
为解决上述技术问题,本发明的锗硅异质结双极晶体管,包括:
P型衬底中形成有匹配层,膺埋层和集电区形成于匹配层上方,场氧区形成于膺埋层和部分集电区的上方,膺埋层和场氧区位于集电区两侧;氧化硅层形成于场氧区上方,多晶硅层形成于氧化硅层上方,基区形成于集电区和多晶硅层上方;氧化硅介质层形成于基区上方,氮化硅介质层形成于氧化硅介质层上方,发射区形成于基区和氮化硅介质层上方,隔离侧墙形成于氧化硅介质层、氮化硅介质层和发射区的两侧;膺埋层通过深接触孔引出,深接触孔中具有钛层或氮化钛层,填有金属钨。
所述膺埋层具有磷杂质。
所述匹配层具有与所述集电区相反类型的杂质。
所述集电区具有磷或砷杂质。
所述氧化硅层厚度为100埃至500埃。
所述多晶硅层厚度为200埃至1500埃。
所述发射区具有砷或磷杂质。
所述基区具有掺硼的锗硅杂质。
所述基区底部的宽度大于等于集电区顶部的宽度。
所述发射区底部的宽度小于集电区顶部的宽度。
所述深接触孔中钛层厚度为100埃至500埃,氮化钛层厚度为50埃至500埃。
本发明的锗硅异质结双极晶体管制造方法,包括:
(1)在P型衬底上刻蚀沟槽;
(2)在沟槽底部注入形成膺埋层;
(3)在沟槽中填入氧化硅形成场氧区,进行化学机械抛光,在膺埋层和有源区下方注入形成匹配层;
(4)光刻、注入P型杂、热推进形成集电区;
(5)淀积氧化硅层,淀积多晶硅层,光刻、刻蚀打开基区窗口;
(6)生长掺硼的锗硅外延;
(7)刻蚀形成基区;
(8)淀积氧化硅介质层,淀积氮化硅介质层,光刻、刻蚀打开发射区窗口;
(9)淀积在位N型掺杂的多晶硅,注入N型杂质,光刻、刻蚀形成发射区;
(10)制作隔离侧墙;
(11)刻蚀深接触孔,深接触孔内淀积钛层或氮化钛层,填入金属钨,进行化学机械抛光,引出膺埋层。
其中,实施步骤(2)时,注入磷杂质,剂量为1e14cm-2至1e16cm-2,能量为2KeV至50KeV。
其中,实施步骤(4)时,注入杂质为砷或磷。
其中,实施步骤(5)时,淀积氧化硅层厚度为100埃至500埃,淀积多晶硅层厚度为200埃至1500埃。
其中,实施步骤(9)时,注入N型杂质为砷或磷,剂量大于1e15cm-2
其中,实施步骤(11)时,采用PVD(物理气相沉积)或CVD(化学气相沉积)方式,淀积钛层厚度为100埃至500埃,淀积氮化钛层厚度为50埃至500埃。
本发明的锗硅异质结双极晶体管不需要改变集电区的厚度和掺杂浓度,通过增加赝埋层和匹配层来提高器件的击穿电压。该器件弃用常规器件中均匀的NBL,在SiGe HBT有源区两侧的场氧区下面制作赝埋层,赝埋层作N型重掺杂,在场氧区刻深孔接触,直接连接赝埋层引出集电区,不再需要使用有源区来实现埋层的电极引出,极大地缩减了器件尺寸和面积。在器件两侧赝埋层之间的集电区和部分场氧下区域作轻掺杂,通过提高集电区/基区(BC结)之间的结击穿电压来提高器件的击穿电压BVCEO。
本发明的锗硅异质结双极晶体管改变了传统HBT BC结的一维耗尽区模式,改变为两维分布,既有向衬底方向的纵向展宽,又有向赝埋层方向的横向延伸,匹配层的加入使得场氧下轻掺杂区域在BC结击穿前全部耗尽,起到分压作用,能提高器件的击穿电压。本发明采用场氧区的深接触孔引出赝埋层作为集电极,避免了常规器件采用N-sinker(N型埋层)所造成的器件面积过大的问题,同时还减小了集电极的寄生电阻。
附图说明
下面结合附图与具体实施方式对本发明作进一步详细的说明:
图1是本发明锗硅异质结双极晶体管的示意图。
图2是本发明锗硅异质结双极晶体管耗尽区分布示意图一,显示反向偏压较小时器件的耗尽区分布。
图3是本发明锗硅异质结双极晶体管耗尽区分布示意图二,显示反向偏压较大时器件的耗尽区分布。、
图4是本发明锗硅异质结双极晶体管制造方法的流程图。
图5是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(1)后形成的器件。
图6是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(2)后形成的器件。
图7是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(3)后形成的器件。
图8是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(4)后形成的器件。
图9是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(5)后形成的器件。
图10是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(6)后形成的器件。
图11是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(7)后形成的器件。
图12是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(8)后形成的器件。
图13是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(9)后形成的器件。
图14是本发明锗硅异质结双极晶体管制造方法示意图一,显示实施步骤(10)后形成的器件。
附图标记说明
101是P型衬底            102是场氧区
103是赝埋层             104是匹配层
105是集电区             106是氧化硅层
107是多晶硅层           108是基区
109是氧化硅介质层       110是氮化硅介质层
111是发射区             112隔离侧墙.
113是深接触孔           114是有源区
115是锗硅外延。
具体实施方式
如图1所示,本发明的锗硅异质结双极晶体管,包括:
P型衬底101中形成有匹配层104,膺埋层103和集电区105形成于匹配层104上方,场氧区102形成于膺埋层103和部分集电区105的上方,膺埋层103和场氧区102位于集电区105两侧;氧化硅层106形成于场氧区102上方,多晶硅层107形成于氧化硅层106上方,基区108形成于集电区105、场氧区102和多晶硅层107上方;氧化硅介质层109形成于基区108上方,氮化硅介质层110形成于氧化硅介质层109上方,发射区111形成于基区108和氮化硅介质层110上方,隔离侧墙112形成于氧化硅介质层109、氮化硅介质层110和发射区111的两侧;膺埋层103通过深接触孔113引出,深接触孔113中具有钛层或氮化钛层,填有金属钨。
本发明采用在常规SiGe HBT增加赝埋层103和匹配层104,增加了器件的击穿电压,并使得器件的击穿不再单纯由纵向BC结的耗尽区决定,而是依靠横向耗尽区分压。如图2所示,当反向偏压较小时,CB结和匹配层104位置都出现耗尽区。如图3所示,随着反向电压的加大,横向耗尽区会在BC结击穿前夹断。由于反向偏压大部分落在横向耗尽区,所以器件的击穿电压将大大高于BC结的击穿电压,本发明能在不改变集电区的深度和掺杂浓度提高BVCEO。
如图4所示,本发明的锗硅异质结双极晶体管制造方法,包括:
(1)如图5所示,在P型衬底101上刻蚀沟槽;
(2)如图6所示,在沟槽底部注入形成膺埋层103;
(3)如图7所示,在沟槽中填入氧化硅形成场氧区102,进行化学机械抛光,在膺埋层103和有源区114下方注入形成匹配层104;
(4)如图8所示,光刻、注入P型杂、热推进形成集电区105;
(5)如图9所示,淀积氧化硅层106,淀积多晶硅层107,光刻、刻蚀打开基区108窗口;
(6)如图10所示,生长掺硼的锗硅外延115;
(7)如图11所示,刻蚀形成基区108;
(8)如图12所示,淀积氧化硅介质层109,淀积氮化硅介质层110,光刻、刻蚀打开发射区111窗口;
(9)如图13所示,淀积在位N型掺杂的多晶硅,注入N型杂质,光刻、刻蚀形成发射区111;
(10)如图14所示,制作隔离侧墙112;
(11)刻蚀深接触孔113,深接触孔113内淀积钛层或氮化钛层,填入金属钨,进行化学机械抛光,引出膺埋层103,形成如图1所示器件。
以上通过具体实施方式和实施例对本发明进行了详细的说明,但这些并非构成对本发明的限制。在不脱离本发明原理的情况下,本领域的技术人员还可做出许多变形和改进,这些也应视为本发明的保护范围。

Claims (17)

1.一种锗硅异质结双极晶体管,其特征是,包括:P型衬底中形成有匹配层,膺埋层和集电区形成于匹配层上方,场氧区形成于膺埋层和部分集电区的上方,膺埋层和场氧区位于集电区两侧;氧化硅层形成于场氧区上方,多晶硅层形成于氧化硅层上方,基区形成于集电区和多晶硅层上方;氧化硅介质层形成于基区上方,氮化硅介质层形成于氧化硅介质层上方,发射区形成于基区和氮化硅介质层上方,隔离侧墙形成于氧化硅介质层、氮化硅介质层和发射区的两侧;膺埋层通过深接触孔引出,深接触孔中具有钛层或氮化钛层,填有金属钨。
2.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述膺埋层具有磷杂质。
3.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述匹配层具有与所述集电区相反类型的杂质。
4.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述集电区具有磷或砷杂质。
5.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述氧化硅层厚度为100埃至500埃。
6.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述多晶硅层厚度为200埃至1500埃。
7.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述发射区具有砷或磷杂质。
8.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述基区具有掺硼的锗硅杂质。
9.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述基区底部的宽度大于等于集电区顶部的宽度。
10.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述发射区底部的宽度小于集电区顶部的宽度。
11.如权利要求1所述的锗硅异质结双极晶体管,其特征是:所述深接触孔中钛层厚度为100埃至500埃,氮化钛层厚度为50埃至500埃。
12.一种锗硅异质结双极晶体管的制造方法,其特征是,包括:
(1)在P型衬底上刻蚀沟槽;
(2)在沟槽底部注入形成膺埋层;
(3)在沟槽中填入氧化硅形成场氧区,进行化学机械抛光,在膺埋层和有源区下方注入形成匹配层;
(4)光刻、注入P型杂、热推进形成集电区;
(5)淀积氧化硅层,淀积多晶硅层,光刻、刻蚀打开基区窗口;
(6)生长掺硼的锗硅外延;
(7)刻蚀形成基区;
(8)淀积氧化硅介质层,淀积氮化硅介质层,光刻、刻蚀打开发射区窗口;
(9)淀积在位N型掺杂的多晶硅,注入N型杂质,光刻、刻蚀形成发射区;
(10)制作隔离侧墙;
(11)刻蚀深接触孔,深接触孔内淀积钛层或氮化钛层,填入金属钨,进行化学机械抛光,引出膺埋层。
13.如权利要求12所述的制造方法,其特征是:实施步骤(2)时,注入磷杂质,剂量为1e14cm-2至1e16cm-2,能量为2KeV至50KeV。
14.如权利要求12所述的制造方法,其特征是:实施步骤(4)时,注入杂质为砷或磷。
15.如权利要求12所述的制造方法,其特征是:实施步骤(5)时,淀积氧化硅层厚度为100埃至500埃,淀积多晶硅层厚度为200埃至1500埃。
16.如权利要求12所述的制造方法,其特征是:实施步骤(9)时,注入N型杂质为砷或磷,剂量大于1e15cm-2
17.如权利要求12所述的制造方法,其特征是:实施步骤(11)时,采用物理气相沉积或化学气相沉积方式,淀积钛层厚度为100埃至500埃,淀积氮化钛层厚度为50埃至500埃。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428402A (zh) * 2014-09-12 2016-03-23 恩智浦有限公司 双极晶体管
WO2021063233A1 (zh) * 2019-09-30 2021-04-08 厦门市三安集成电路有限公司 外延结构和晶体管

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035690B (zh) * 2012-06-08 2015-06-03 上海华虹宏力半导体制造有限公司 击穿电压为7-10v锗硅异质结双极晶体管及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070134854A1 (en) * 2005-12-13 2007-06-14 Chartered Semiconductor Manufacturing, Ltd Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process
CN102104062A (zh) * 2009-12-21 2011-06-22 上海华虹Nec电子有限公司 双极晶体管
CN102117827A (zh) * 2009-12-31 2011-07-06 上海华虹Nec电子有限公司 BiCMOS工艺中的寄生垂直型PNP器件
CN102231379A (zh) * 2009-12-21 2011-11-02 上海华虹Nec电子有限公司 SiGe异质结双极晶体管多指结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070134854A1 (en) * 2005-12-13 2007-06-14 Chartered Semiconductor Manufacturing, Ltd Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process
CN102104062A (zh) * 2009-12-21 2011-06-22 上海华虹Nec电子有限公司 双极晶体管
CN102231379A (zh) * 2009-12-21 2011-11-02 上海华虹Nec电子有限公司 SiGe异质结双极晶体管多指结构
CN102117827A (zh) * 2009-12-31 2011-07-06 上海华虹Nec电子有限公司 BiCMOS工艺中的寄生垂直型PNP器件

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105428402A (zh) * 2014-09-12 2016-03-23 恩智浦有限公司 双极晶体管
CN105428402B (zh) * 2014-09-12 2018-06-29 恩智浦有限公司 双极晶体管
WO2021063233A1 (zh) * 2019-09-30 2021-04-08 厦门市三安集成电路有限公司 外延结构和晶体管
US11955518B2 (en) 2019-09-30 2024-04-09 Xiamen Sanan Integrated Circuit Co., Ltd. Epitaxial structure and transistor including the same

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