CN103022027A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN103022027A
CN103022027A CN2012100701159A CN201210070115A CN103022027A CN 103022027 A CN103022027 A CN 103022027A CN 2012100701159 A CN2012100701159 A CN 2012100701159A CN 201210070115 A CN201210070115 A CN 201210070115A CN 103022027 A CN103022027 A CN 103022027A
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semiconductor device
gate
resistance
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diode
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义平隆之
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Toshiba Corp
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Abstract

本发明提供一种半导体装置，其具备：晶体管，在栅电极与源电极之间插入有电阻；以及二极管，相对于所述电阻串联地插入于所述栅电极与所述源电极之间。

Description

半导体装置
相关申请的交叉参考
本申请基于并要求2011年9月20日提交的日本专利申请No.2011-204366的优先权利益，其所有内容通过参考而援入于此。
技术领域
实施方式涉及下拉用的电阻连接于栅电极的MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor：金属氧化物半导体场效应晶体管)。
背景技术
通常，MOSFET的驱动电路以MOSFET的异常振荡的防止、栅极-源极间(G-S间)电容的放电以及栅电极的下拉为目的而在栅极-源极间插入电阻RGS的情况很多。然而，在裸芯片的状态下在MOSFET的栅极-源极间外部连接有电阻RGS的情况下，在栅极的接合线断开即未连接于外部的情况下，无法起到下拉的目的。
此时，担心当MOSFET因误动作而导通时，包含MOSFET的电路整体会被破坏。因此，提出了将连接MOSFET的栅极-源极间的电阻RGS内置于半导体芯片中、以及利用形成于半导体芯片上的薄膜电阻体对MOSFET的栅极-源极间进行连接。
发明内容
本发明的实施方式提供一种在不对栅极绝缘膜的漏电流试验给予影响的情况下在栅极-源极间插入了电阻的半导体装置。
实施方式的半导体装置具备：晶体管，在栅电极与源电极之间插入有电阻；以及二极管，相对于所述电阻串联地插入于所述栅电极与所述源电极之间。
根据本发明的实施方式，能提供一种在不对栅极绝缘膜的漏电流试验给予影响的情况下在栅极-源极间插入了电阻的半导体装置。
附图说明
图1A和1B是实施方式的半导体装置的构成图。
图2是实施方式的半导体装置的等效电路图。
图3是比较例的半导体装置的等效电路图。
图4是比较例的半导体装置的特性图。
图5和图6是其他实施方式的半导体装置的等效电路图。
具体实施方式
以下，参照附图，对实施方式详细地进行说明。
(实施方式)
图1是实施方式的半导体装置1的构成图。图1A是半导体装置1的俯视图，图1B是图1A的线段X-X的剖视图。以下，参照图1，对半导体装置1的构成进行说明。
如图1A所示那样，实施方式的半导体装置1的大部分为FET区域A，在一角形成有栅电极区域B。在FET区域A，形成有多个MOSFET101。在多个MOSFET101的上部，形成有成为源电极S的金属层14。在栅电极区域B，形成有成为栅电极G的金属层15。
如图1B所示那样，实施方式的半导体装置1具备n+型的硅基板11、n-型的外延层12、氧化硅膜13、多个MOSFET101、成为源电极S的金属层14、成为栅电极G的金属层15、成为漏电极D的金属层16、电阻102、二极管103以及连接电阻102和二极管103的金属层17。
外延层12形成于硅基板11上。氧化硅膜13形成于外延层12上。多个MOSFET101形成于FET区域A的外延层12。金属层16形成于硅基板11背面。
电阻102由p型的多晶硅(Poly-Si)形成。电阻102的一端连接于成为源电极S的金属层14，另一端连接于金属层17。二极管103由p型的多晶硅(Poly-Si)部103a和n型的多晶硅(Poly-Si)部103b形成。二极管103的p型的多晶硅部103a连接于成为栅电极G的金属层15。二极管103的n型的多晶硅部103b连接于金属层17。
图2是实施方式的半导体装置1的等效电路图。如图2所示那样，在半导体装置1内具有栅电极G、漏电极D、源电极S，形成有利用对栅电极G的电压施加而被控制开/关的MOSFET101，且形成有串联插入于MOSFET101的栅电极G以及源电极S间(以下仅称为栅极-源极间)的电阻102以及二极管103。以MOSFET101的异常振荡的防止、栅极-源极间电容的放电以及栅电极G的下拉为目的而将电阻102插入于栅极-源极间。电阻102的电阻值例如为100kΩ。
二极管103以从栅电极G向源电极S的方向成为正向(电流流动的方向)的方式，相对于电阻102串联地插入于栅极-源极间。这样，通过将二极管103插入于栅极-源极间，从而能成为电流在从栅电极G向源电极S的方向(以下称为正向)流动且电流不在从源电极S向栅电极G的方向(以下称为反向)流动的构成。
在计测对栅极-源极间施加电压(例如5MV/cm)的栅极冲击试验后的漏电流IGSS时，以反偏的方式、即以使电流在从源电极S向栅电极G的方向流动的方式施加电压。由于二极管103不在反向上流动电流，所以能精度良好地计测栅极绝缘膜的漏电流IGSS(实际上，虽然会产生微小的漏电流，但其值为1nA左右，是不会对IGSS的计测给予影响的等级)。
另一方面，由于电流在正向上流动，所以通过将源电极S接地(GND)，从而插入于栅极-源极间的电阻102能发挥MOSFET101的异常振荡的防止、栅极-源极间电容的放电以及栅电极G的下拉的功能。另外，虽然在图2中，二极管103插入于栅电极G与电阻102之间，但也可以将二极管103插入于电阻102与源电极S之间。
(比较例)
图3是比较例的半导体装置1A的等效电路图。图3所示的半导体装置1A中二极管未插入于栅极-源极间这一点，与参照图2说明的半导体装置1不同。关于其他构成，与参照图2说明的半导体装置1相同，因此，对于相同的构成，标注相同的附图标记并省略重复的说明。
如图3所示那样，比较例的半导体装置1A中二极管未插入于栅极-源极间。因此，在栅极冲击试验后的漏电流IGSS的测定时电流I会经由电阻102流过栅电极G与源电极S之间。
图4是表示在将电阻102插入于栅极-源极间的情况下向栅极-源极间的施加电压VGS与流过电阻102的电流IR的关系的图。在图4中，横轴表示向栅极-源极间的施加电压VGS，纵轴表示电流值IR。图4所示的结果是在温度为25℃、向源极-漏极间的施加电压VDS为0V的条件下测定的。图4的RGS表示电阻102的电阻值(Ω)。
如图4所示那样，为了减小流过电阻102的电流值IR，需要提高电阻102的电阻值、或减低施加于栅极-源极间的电压VGS。然而，在提高电阻102的电阻值的情况下，当过于提高电阻102的电阻值时，会使电流难以流过电阻102。因此，担心会无法使电阻102作为栅极的下拉而发挥功能。
此外，即使在使施加于栅极-源极间的电压VGS变低的情况下，例如使电阻102的电阻值为100kΩ，为了使流过电阻102的电流值IR成为与漏电流IGSS的阈值相同的100nA，也需要使施加于栅极-源极间的电压VGS为10mV。
虽然即使在使施加于栅极-源极间的电压VGS为10mV的情况下，也会产生栅极绝缘膜的漏电流IGSS，但为了将施加于栅极-源极间的施加的电压VGS保持在10mV，就需要对电压高精度地进行控制。此外，为了精度良好地测定栅极绝缘膜的漏电流IGSS，需要向栅极-源极间长时间地外加电压VGS，这是不实用的。
另一方面，在图2中说明过的实施方式的半导体装置1将二极管103与电阻102串联地插入于栅极-源极间。对在栅极-源极间施加电压(例如5MV/cm)的栅极冲击试验后的漏电流IGSS进行计测时，以反偏的方式、即在从源电极S向栅电极G的方向上施加电压。由于二极管103不在反向上流动电流，所以通过反偏地施加电压，能精度良好地计测栅极绝缘膜的漏电流IGSS。
另一方面，由于电流在正向上流动，所以通过将源电极S接地(GND)，从而插入于栅极-源极间的电阻RGS能发挥MOSFET101的异常振荡的防止、栅极-源极间电容的放电以及栅电极G的下拉的功能。
另外，也可以如图5所示的半导体装置2那样使插入于栅极-源极间的二极管103为齐纳二极管104。此外，也可以如图6所示的半导体装置3那样，将ESD(静电放电)保护用的齐纳二极管105与齐纳二极管104并联地插入到栅极-源极间。在这种情况下，ESD保护用的齐纳二极管105由于与齐纳二极管104并联地形成于半导体装置3内，所以能利用与齐纳二极管104相同的工序来形成ESD保护用的齐纳二极管105。另外，也可以不将ESD保护用的齐纳二极管105内置于半导体装置中，而是进行外部安装。
(其他实施方式)
虽然描述了一些实施方式，但这些实施方式仅是作为例子而示出的，并不意在限制发明的范围。实际上，这里所描述的新的实施方式能以各种方式实施，进而，可以在不脱离发明的精神的情况下，对这里所描述的实施方式在形式上做出替换和改变。一同附上的权利要求书和其等同意在覆盖这些会落入发明的范围和精神内的形式或修改。

Claims (6)

1.一种半导体装置，具备：
晶体管，在栅电极与源电极之间插入有电阻；以及
二极管，相对于所述电阻串联地插入于所述栅电极与所述源电极之间。
2.根据权利要求1所述的半导体装置，其中，
所述二极管以从所述栅电极向所述源电极的方向成为正向的方式插入于所述栅电极与所述源电极之间。
3.根据权利要求1所述的半导体装置，其中，
所述二极管是齐纳二极管。
4.根据权利要求1所述的半导体装置，其中，
所述源极接地。
5.根据权利要求1所述的半导体装置，其中，
还具备齐纳二极管，该齐纳二极管相对于所述电阻和所述二极管并联地插入于所述栅电极与所述源电极之间。
6.根据权利要求1所述的半导体装置，其中，
所述二极管形成于所述半导体装置内。
CN2012100701159A 2011-09-20 2012-03-16 半导体装置 Pending CN103022027A (zh)

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