CN103001586B - A kind of broadband two-channel digital down converter - Google Patents
A kind of broadband two-channel digital down converter Download PDFInfo
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- CN103001586B CN103001586B CN201210534676.XA CN201210534676A CN103001586B CN 103001586 B CN103001586 B CN 103001586B CN 201210534676 A CN201210534676 A CN 201210534676A CN 103001586 B CN103001586 B CN 103001586B
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Abstract
The invention discloses a kind of broadband two-channel digital down converter, comprise A/D digital collection module, interface control module, mixing and filter input control module and parallel filtering module, described each module connects successively based on FPGA platform; A/D digital collection module of the present invention adopts the high-frequency digital signal of binary channels mode of operation collection to carry out first time frequency reducing respectively by A/D digital collection module, FPGA transceiver interface signal after mixing and filter input control module configure carries out second time frequency reducing by FPGA, each passage produces the final frequency signal that 16 tunnel frequencies are 1/16 of original signal, finally by mixing and filter input control module to 16 road signal phase demodulations of each passage, extraction, eventually through the filtering of parallel filtering modular concurrent.The invention solves the problems such as bandwidth restriction in wideband-radar signal Digtal Down Converter Designing is strict, message transmission rate is low, Digital Signal Processing poor real.
Description
Technical field
The present invention relates to Radar Signal Processing System, particularly adopt the Digital Down Convert process of the Radar Signal Processing middle width strip signal of wideband phased array radar, sophisticated signal waveform, High Data Rate.
Background technology
Along with the development of Radar Technology and signal processing theory, modern radar mostly adopts phase array system, its signal waveform and signal processing method become increasingly complex, and signal bandwidth is increasing, need data transfer rate to be processed and data processing requirement of real-time also more and more higher.And each wideband radar product signal processing subsystem all will be equipped with a Digital Down Converter Module, as the important component part of wideband radar product signal processor.
The development of current Radar Products digital down converter adopts classical mixing, phase demodulation and filtering principle substantially, and use serial structure to carry out Direct Programming realization to Digital Down Convert algorithm, this defining method exists several large shortcoming:
1. calculation of complex, does not add screening to sample frequency, makes the frequency mixer coefficient value used in optical mixing process without particularity, causes the computational process of whole mixing loaded down with trivial details, have impact on precision and the real-time of data processing;
2. data transfer rate is low, the filter structure of serial makes digital down converter maximum operating frequency to break through hardware constraints, optical mixing process without sample frequency screening limits the processing speed of digital signal, causes whole digital down conversion system cannot realize large data rate transmission and process;
3. poor real, data handling procedure is tediously long lowly makes system be difficult to requirement of real time with processing speed;
4. radar signal Bandwidth-Constrained, Digital Signal Processing speed cannot meet the High Data Rate requirement of wideband radar digital signal, limits the performance index of radar bandwidth.
Summary of the invention
In order to solve the problem, the invention provides a kind of broadband two-channel digital down converter, comprise and connecting successively based on FPGA platform:
A/D acquisition module, carries out signals collecting to an initialize signal, is converted into high-frequency digital signal, and makes down conversion process to this high-frequency digital signal, forms first frequency digital signal;
Interface control module, communicates with described FPGA high speed transceiver interface, and described first frequency digital signal is sent into FPGA, and described first frequency digital signal carries out down conversion process again in described FPGA, forms second frequency digital signal;
Mixing and filter input control module, carry out I/Q phase demodulation, Frequency mixing processing and I/Q two ways of digital signals respectively to described second frequency digital signal and extract; And
Parallel filtering module, carries out low-pass filtering to the second frequency signal after settling signal extracts.
Preferably, described A/D acquisition module adopts binary channels mode of operation, and described binary channels respectively produces the parallel first frequency digital signal in four tunnels, and the frequency of described first frequency digital signal is 1/4 of the frequency of described high-frequency digital signal.
Preferably, described FPGA has read and write the frequency reducing of described first frequency digital signal by serioparallel exchange and FIFO, and described binary channels produces the second frequency digital signal that 16 tunnel frequencies are 1/4 of described first frequency digital signal respectively.
Preferably, described mixing and filter input control module are respectively to I road and the Q road signal extraction of the second frequency digital signal after each passage mixing, and each passage exports 8 road I railway digital signals and 8 road Q railway digital signals.
Preferably, described mixing and filter input control module complete the input control to parallel filtering module by the register integral shift of one 8 signal word lengths.
Preferably, described parallelism wave filter is by improving its throughput efficiency and clock frequency through multi-stage pipeline after FIR filter.
Preferably, the frequency of described high-frequency signal is 5GHz.
Compared with prior art, beneficial effect of the present invention is as follows:
Achieve by general-purpose platform the Digital Down Convert process that frequency is up to the digital signal of 5GHz, the invention solves the problems such as bandwidth restriction in wideband-radar signal Digtal Down Converter Designing is strict, message transmission rate is low, Digital Signal Processing poor real.
Certainly, implement arbitrary product of the present invention might not need to reach above-described all advantages simultaneously.
Accompanying drawing explanation
Fig. 1 is the workflow diagram of broadband two-channel digital down converter provided by the invention.
Embodiment
The invention provides a kind of broadband two-channel digital down converter as shown in Figure 1, comprise and connecting successively based on FPGA platform:
A/D acquisition module, carries out signals collecting to an initialize signal, is converted into high-frequency digital signal, and makes down conversion process to this high-frequency digital signal, forms first frequency digital signal;
Interface control module, communicates with described FPGA high speed transceiver interface, and described first frequency digital signal is sent into FPGA, and described first frequency digital signal carries out down conversion process again in described FPGA, forms second frequency digital signal;
Mixing and filter input control module, carry out I/Q phase demodulation, Frequency mixing processing and I/Q two ways of digital signals respectively to described second frequency digital signal and extract; And
Parallel filtering module, carries out low-pass filtering to the second frequency signal after settling signal extracts.
Thought of the present invention is: the present invention adopts binary channels mode of operation to obtain high-frequency digital signal by utilizing A/D digital collection module acquires, each passage has high-frequency digital signal, twin-channel high-frequency digital signal is respectively by the first time frequency reducing of A/D digital collection module, FPGA transceiver interface signal after mixing and filter input control module configure carries out second time frequency reducing by FPGA, twice frequency reducing is reduced to 1/4 of primary frequency respectively, last each passage produces the final frequency signal that 16 tunnel frequencies are 1/16 of original signal, then by mixing and filter input control module to 16 road signal phase demodulations of each passage, extract, and eventually through the filtering of parallel filtering modular concurrent, so far the whole process of frequency conversion is completed.
Below only illustrate, composition of the present invention and function can not be limited to.
Application examples:
The present invention gathers wideband radar echo data by adopting the A/D data acquisition module of binary channels mode of operation by its A/D capture card, should in use-case, wideband radar echo data is converted to the high-frequency digital signal that frequency is 5GHz by A/D data acquisition module, this high-frequency digital signal is through a frequency reducing, two passages are the first frequency digital signal of 1/4 of high-frequency digital signal frequency respectively by the frequency that 4 roads walk abreast, and are 1.25GHz in this first frequency digital signal frequency;
Completed the communication of A/D data acquisition module and fpga chip High Speed I/O again by configuring its SPI interface register by interface control module configuration, the down conversion process of each passage 4 road first frequency digital signal is completed by FPGA serioparallel exchange and FIFO read-write operation, export the second frequency digital signal that 16 tunnel frequencies are 312.5MHz, the wherein mode of operation of each passage, gain, biased, the parameters such as difference and input impedance can pass through SPI serial line interface programming Control and adjustment, phase place when guaranteeing monolithic four passage interlaced samplings, gain, the consistency of side-play amount,
Mixing and filter input control module are by controlling the parallel data flow inputted, mixing and I/Q phase demodulation are carried out to the 16 road second frequency digital signals that each passage inputs, the once extraction simultaneously completing I/Q two paths of signals exports 8 road I road signals and 8 Q road, road signals, has operated the input control to called 8 parallel filtering modules by the integral shift of 8 signal word lengths.
Parallel filtering module, by the structure of streamline, FIR filtering process is carried out to the digital signal of parallel input, pipeline organization improves data throughput and the clock frequency of digital signal down variable frequency device, each clock completes the parallel filtering of 8 supplied with digital signal, maximum clock frequency is 328MHz, can complete the filter task that frequency is the second frequency signal of 312.5MHz.
The invention provides a kind of digital down converter being common to wideband radar product, owing to taking above-mentioned technical scheme, adopt conventional general device to build general-purpose platform, achieve by general-purpose platform the Digital Down Convert process that frequency is up to the digital signal of 5GHz.The present invention can be used for the Digital Down Convert process of wideband radar product signal treatment system, and research has great importance and purposes further.The invention solves the problems such as bandwidth restriction in wideband-radar signal Digtal Down Converter Designing is strict, message transmission rate is low, Digital Signal Processing poor real.
The disclosed preferred embodiment of the present invention just sets forth the present invention for helping above.Preferred embodiment does not have all details of detailed descriptionthe, does not limit the embodiment that this invention is only described yet.Obviously, according to the content of this specification, can make many modifications and variations.This specification is chosen and is specifically described these embodiments, is to explain principle of the present invention and practical application better, thus makes art technical staff understand well and to utilize the present invention.The present invention is only subject to the restriction of claims and four corner and equivalent.
Claims (6)
1. a broadband two-channel digital down converter, is characterized in that, comprises connecting successively based on FPGA platform:
A/D acquisition module, carries out signals collecting to an initialize signal, is converted into high-frequency digital signal, and makes down conversion process to this high-frequency digital signal, forms first frequency digital signal;
Interface control module, communicates with described FPGA high speed transceiver interface, and described first frequency digital signal is sent into FPGA, and described first frequency digital signal carries out down conversion process again in described FPGA, forms second frequency digital signal;
Mixing and filter input control module, carry out I/Q phase demodulation, Frequency mixing processing and I/Q two ways of digital signals respectively to described second frequency digital signal and extract; And
Parallel filtering module, carry out low-pass filtering to the second frequency signal after settling signal extracts, every road processing clock is 328MHz;
Described parallel filtering module is by improving its throughput efficiency and clock frequency through multi-stage pipeline after FIR filter.
2. broadband two-channel digital down converter as claimed in claim 1, it is characterized in that, described A/D acquisition module adopts binary channels mode of operation, described binary channels respectively produces the parallel described first frequency digital signal in four tunnels, and the frequency of described first frequency digital signal is 1/4 of the frequency of described high-frequency digital signal.
3. broadband two-channel digital down converter as claimed in claim 1, it is characterized in that, described FPGA has read and write the frequency reducing of described first frequency digital signal by serioparallel exchange and FIFO, and described binary channels produces the described second frequency digital signal that 16 tunnel frequencies are 1/4 of described first frequency digital signal respectively.
4. broadband two-channel digital down converter as claimed in claim 1, it is characterized in that, described mixing and filter input control module are respectively to I road and the Q road signal extraction of the described second frequency digital signal after each passage mixing, and each passage exports 8 road I railway digital signals and 8 road Q railway digital signals.
5. broadband two-channel digital down converter as claimed in claim 1, it is characterized in that, described mixing and filter input control module complete the input control to parallel filtering module by the register integral shift of one 8 signal word lengths.
6. broadband two-channel digital down converter as claimed in claim 1, it is characterized in that, the frequency of described high-frequency signal is 5GHz.
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| CN107659272A (en) * | 2017-09-21 | 2018-02-02 | 天津光电通信技术有限公司 | A kind of new up-converter circuit |
| US10502764B2 (en) * | 2018-01-05 | 2019-12-10 | Rohde & Schwarz Gmbh & Co. Kg | Signal analyzing circuit and method for auto setting an oscilloscope |
| CN112104382A (en) * | 2020-09-10 | 2020-12-18 | 中国电子科技集团公司第五十八研究所 | Parallel digital down-conversion processing system based on digital signals |
| CN113114166A (en) * | 2021-03-12 | 2021-07-13 | 成都辰天信息科技有限公司 | High-speed parallel DDC (direct digital control) and FIR (finite impulse response) filtering processing method based on FPGA (field programmable Gate array) |
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| CN101610095A (en) * | 2009-05-12 | 2009-12-23 | 北京航空航天大学 | A kind of ultra-wideband radio frequency digital receiver device and its implementation based on FPGA |
| CN101621301A (en) * | 2009-07-27 | 2010-01-06 | 重庆华伟工业（集团）有限责任公司 | Broadband digital monitoring receiver |
| CN101707473A (en) * | 2009-09-25 | 2010-05-12 | 中国科学院上海天文台 | GHz ultra wide band digital down converter method |
| CN201766581U (en) * | 2010-09-07 | 2011-03-16 | 中国电子科技集团公司第十四研究所 | 16-way great dynamic digital receiver |
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| CN101610095A (en) * | 2009-05-12 | 2009-12-23 | 北京航空航天大学 | A kind of ultra-wideband radio frequency digital receiver device and its implementation based on FPGA |
| CN101621301A (en) * | 2009-07-27 | 2010-01-06 | 重庆华伟工业（集团）有限责任公司 | Broadband digital monitoring receiver |
| CN101707473A (en) * | 2009-09-25 | 2010-05-12 | 中国科学院上海天文台 | GHz ultra wide band digital down converter method |
| CN201766581U (en) * | 2010-09-07 | 2011-03-16 | 中国电子科技集团公司第十四研究所 | 16-way great dynamic digital receiver |
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