CN113114166A - High-speed parallel DDC (direct digital control) and FIR (finite impulse response) filtering processing method based on FPGA (field programmable Gate array) - Google Patents
High-speed parallel DDC (direct digital control) and FIR (finite impulse response) filtering processing method based on FPGA (field programmable Gate array) Download PDFInfo
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Abstract
The invention discloses a high-speed parallel DDC and FIR filtering processing method based on FPGA, which comprises inputting signals and setting a parallel path number M according to the data sampling rate of the input signals; then, according to the number M of parallel paths, sequentially sampling the input signal according to each M sampling points to divide the input signal into M input sub-signals, and then performing digital down-conversion on each input sub-signal to generate a corresponding first intermediate signal and an intermediate signal; then, filtering the first intermediate signal or the second intermediate signal through an FIR filter to generate four corresponding output sub-signals; the data sampling rate of each output sub-signal, the data sampling rate of the input sub-signal, the data sampling rate of the first intermediate signal and the data sampling rate of the second intermediate signal are all 1/M of the data sampling rate of the input signal. The invention realizes the problem that the FPGA processor can not process the data signal with high data sampling rate by designing a parallel framework.
Description
Technical Field
The invention relates to signal processing of an FPGA processor, in particular to a high-speed parallel DDC and FIR filtering processing method based on an FPGA.
Background
The FPGA processor supports full parallel operation and is more suitable for processing high-speed data signals. For an FPGA processor, data signals are generally processed in a pipeline form in a fully parallel manner, and the operation speed of the FPGA processor is usually between 200M and 300M due to the limitations of internal lookup tables, routing, delay time of multiplier units, and the like of the FPGA processor. Especially for the echo signal of the radar equipment, due to the limitation of the internal hardware of the FPGA processor, the FPGA processor can only process the data signal with the sampling rate of 350MSPS and below.
However, the data sampling rate of the echo signal of the existing radar device is generally 480MSPS or above, and the existing FPGA processor cannot process the echo signal of the radar device with a high data sampling rate in time, so that the data signal is lost, and the detection result of the radar device is affected.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a high-speed parallel DDC and FIR filtering processing method based on an FPGA, which can solve the problem that an FPGA processor in the prior art cannot process data signals with high data sampling rate.
The purpose of the invention is realized by adopting the following technical scheme:
the high-speed parallel DDC and FIR filtering processing method based on FPGA includes the following steps:
a shunting step: acquiring the data sampling rate of an input signal, setting a parallel path number M according to the data sampling rate of the input signal, and sequentially and circularly sampling the input signal at intervals of M sampling points according to the parallel path number M, so that the input signal is divided into M input sub-signals; the data sampling rate of each input sub-signal is 1/M of the input signal;
frequency conversion: respectively carrying out digital down-conversion on each input sub-signal to generate a corresponding first intermediate signal and a corresponding second intermediate signal; the data sampling rate of each first intermediate signal and each second intermediate signal is 1/M of the input signal;
a first filtering step: firstly, dividing each first intermediate signal into M first intermediate sub-signals according to sampling points and in a mode of sequentially M1 extraction; then, filtering the M first intermediate sub-signals of each first intermediate signal through M sub-filters of an FIR filter in sequence to obtain corresponding M first filtered sub-signals; secondly, selecting a corresponding first filtering sub-signal from M first filtering sub-signals corresponding to each first intermediate signal according to sampling points and in a mode of sequentially M extracting 1 to combine to generate a first output sub-signal; the number of the first output sub signals is the same as that of the input sub signals, and the first output sub signals are M, and the data sampling rate of the first output sub signals is 1/M of that of the input signals;
a second filtering step: firstly, dividing each second intermediate signal into M second intermediate sub-signals according to sampling points and in a mode of sequentially M extracting 1; then, filtering the M second intermediate sub-signals of each second intermediate signal through M sub-filters of the FIR filter in sequence to obtain corresponding M second filtered sub-signals; secondly, selecting a corresponding second filtering sub-signal from M second filtering sub-signals corresponding to each second intermediate signal according to sampling points and in a mode of sequentially M extracting 1 to combine to generate a second output sub-signal; the number of the second output sub signals is the same as that of the input sub signals, and the number of the second output sub signals is M, and the data sampling rate of the first output sub signals is 1/M of that of the input signals;
the processing steps are as follows: and sending the M first output sub-signals and the M second output sub-signals to other data processing modules of the FPGA processor for data processing.
Further, the M sub-filters are respectively: a first sub-filter, a second sub-filter, a third sub-filter, …, and an Mth sub-filter; wherein the coefficient of the first sub-filter is h0、hM、…、hL-MThe coefficient of the second sub-filter is h1、hM+1、…、hL-M+1The coefficient of the third sub-filter is h2、hM+2、…、hL-M+2…, the coefficient of the Mth sub-filter is hM-1、hM+M-1、…、HL-1。
Further, the FIR filter is an L-order filter.
Further, L is an integer multiple of M.
Further, the input signal is an intermediate frequency digital signal sent by the ADC module; the first output signal is an I baseband digital signal, and the second output signal is a Q baseband digital signal.
Further, the central frequency point f of the input signal0＝4*n*fS+fS/M, wherein fSAs dataThe sampling rate.
Further, the step of performing digital down-conversion on each input sub-signal refers to performing frequency mixing processing on each input sub-signal and a local oscillator signal; wherein, the local oscillation signal is 1, 0, -1, 0, ….
Further, the data sampling rate of each input sub-signal is less than 350 MSPS.
Compared with the prior art, the invention has the beneficial effects that:
the invention splits the data signals of high-speed data sampling rate and processes the data signals respectively by adopting a parallel mode, and then combines the results after processing respectively, thereby reducing the data sampling rate of the original data signals of high data sampling rate, meeting the hardware requirement of an FPGA (field programmable gate array) processor on data signal processing, realizing that the existing FGPA processor can process the data signals of any data sampling rate, particularly processing echo signals of radar equipment of high data sampling rate, greatly improving the efficiency of data signal processing, and solving the problem that the FPGA processor in the prior art can not process the data signals of high data sampling rate due to the limitation of the internal hardware of the FPGA processor.
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Fig. 1 is a schematic diagram of an architecture of a conventional FPGA processor for processing a sampling signal with a data sampling rate of 480MSPS according to the present invention;
FIG. 2 is an architecture diagram of digital down-conversion of a sampled signal having a data sample rate of 480 MSPS;
FIG. 3 is a block diagram of a four-way parallel digital down-conversion of a data signal according to the present invention;
FIG. 4 is a schematic diagram of a filtering architecture for data signals according to the present invention;
fig. 5 is a schematic diagram of four parallel DDC and FIR filtering processes of an intermediate frequency digital signal with a data sampling rate of 480MSPS according to the present invention;
FIG. 6 is a schematic diagram of the DDC and FIR filtering processing architecture in the FPGA processor when the local oscillation signal is a fixed signal;
FIG. 7 is a block diagram of the decimation-2 process of FIG. 6;
fig. 8 is a flowchart of a high-speed parallel DDC and FIR filtering processing method based on an FPGA according to the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
The invention provides a preferred embodiment, which is based on a high-speed parallel DDC and FIR filtering processing architecture of an FPGA, is applied to an FPGA processor, can enable the FPGA processor to realize the processing of data signals with any data sampling rate, and solves the problem that the processing of the data signals with high data sampling rate can not be processed due to the limitation of the internal hardware of the FPGA processor in the prior art. More preferably, the present embodiment is particularly suitable for processing of echo signals of a radar apparatus of a high data sampling rate.
To better illustrate the architecture of the high-speed parallel DDC and FIR filtering processing based on FGPA provided by the present invention, the bit width of the ADC module is set to be 14 bits, the data sampling rate is 480MSPS, the center frequency of the sampled data signal is f0, and the bandwidth is 200 MHz.
The present embodiment takes an echo signal of a radar device as an example to explain: and the echo signal of the radar equipment is received by the antenna oscillator and then converted into an intermediate frequency digital signal, and the intermediate frequency digital signal is transmitted to the ADC module. And the ADC module converts the received intermediate frequency data signal into a baseband digital signal so as to facilitate the processing of subsequent hardware equipment.
More preferably, after receiving the intermediate frequency digital signal, the ADC module first mixes the intermediate frequency data signal with a local oscillator signal generated in the system to obtain two baseband digital signals, and then filters the two baseband signals through an FIR filter to obtain an I baseband digital signal and a Q baseband digital signal, as shown in fig. 1, which is an architecture diagram of mixing.
As can be seen from fig. 1, the intermediate frequency digital signal received by the ADC module is subjected to DDC (digital down conversion) and FIR filtering to obtain an I baseband digital signal and a Q baseband digital signal, so that the data sampling rate is reduced from 480MSPS to 240 MSPS. However, when the DDC module and the FIR filter process the intermediate data signal, the data sampling rate of the data signal is 480MSPS, but the conventional FPGA processor cannot directly process the data signal with the data sampling rate of 480MSPS due to the limitation of its internal hardware. Particularly, the running speed of the FIR filter is difficult to reach 480MSPS, and the processing requirement of the data signal with the data sampling rate of 480MSPS cannot be met; meanwhile, when the internal resources of the FPGA processor are used more, the running speeds of NCO, multiplier and other devices in the FPGA processor cannot meet the processing requirement of the data signal with the data sampling rate of 480 MSPS.
In view of the above problems of the FPGA processor, the present embodiment provides a parallel processing architecture, which can split the intermediate frequency digital signal received by the ADC module and then perform parallel processing in multiple paths, and then combine multiple data signals after parallel processing to achieve the purpose of reducing the data sampling rate, so that each parallel processing can meet the hardware requirement of the FPGA processor.
In this embodiment, the present invention is described with a 4-way parallel architecture:
and splitting the intermediate frequency digital signal received by the ADC module according to every 4 sampling points, so that the intermediate frequency digital signal is divided into 4 paths of intermediate frequency digital sub-signals. The data sampling rate of each intermediate frequency digital sub-signal is 1/4 of the intermediate frequency digital signal received by the ADC module.
Firstly, the mixing operation can be expressed by a mathematical formula according to the principle of digital frequency conversion, and is specifically shown in formula (1):
yj＝xj×LOj,j＝0、1、2、...、4m (1)。
where j represents a sample point.
The LO is a local oscillator signal for frequency mixing processing, that is: LO0,LO1,LO2,LO3,.... The NCO in fig. 1 is an oscillation circuit. The local oscillator signal LO is derived from an oscillator circuit NCO.
Setting X to represent an input signal, that is, an intermediate frequency digital signal before frequency conversion, specifically: x is the number of0,x1,x2,x3,.... Wherein x isjAnd represents the number corresponding to the j-th sampling point.
Setting Y to represent a data signal obtained after the data signal before frequency conversion is subjected to frequency mixing processing, and specifically comprising the following steps: y is0,y1,y2,y3,.... In the same way, yjAnd the j data represents the data of the j sampling point of the input signal after digital down-conversion processing.
As shown in fig. 2, the data signal with the data sampling rate of 480MSPS of this embodiment is converted into an intermediate frequency digital signal after passing through an ADC module, and then the intermediate frequency digital signal is mixed by two mixers to obtain two paths of baseband digital signals, where the data sampling rate of each baseband digital signal is 480 MSPS. Because the data signal of high data sampling rate can not be directly handled to current FPGA treater, consequently, this embodiment splits multichannel medium frequency digital branch signal through the intermediate frequency digital signal that is 480MSPS with the data sampling rate to make the data sampling rate of every medium frequency digital branch signal reduce, with the internal hardware requirement that satisfies the FPGA treater. Specifically, the present embodiment describes the DDC and FIR filtering processing architecture based on the FPGA in a four-way parallel manner:
sampling the intermediate frequency digital signals converted by the ADC module according to every M sampling points, so that the intermediate frequency digital signals with the data sampling rate of 480MSPS are divided into a plurality of intermediate frequency digital sub-signals, and then carrying out digital down-conversion processing on each intermediate frequency digital sub-signal through an FPGA processor. Wherein, the data sampling rate of each medium frequency digital sub-signal is 480 MSPS/M. More specifically, for example, when M is 4, the data sampling rate of the intermediate frequency digital partial signal is 120MSPS, which meets the internal hardware requirement of the FPGA processor. Therefore, the intermediate frequency digital signals of each path can be mixed according to the existing mixing mode to obtain two paths of corresponding baseband digital signals.
As shown in fig. 3, the data sampling rate of each if digital partial signal is 120MSPS, which is 1/4 of the data sampling rate of the original if digital signal.
And each intermediate frequency digital sub-signal is subjected to frequency mixing by a corresponding frequency mixer to obtain two corresponding paths of baseband digital signals.
Similarly, the data sampling rate of the local oscillation signal NCO of the frequency mixer when each intermediate frequency digital sub-signal is subjected to frequency mixing is 1/4 of the original local oscillation signal.
Preferably, the present embodiment further provides a mathematical reasoning formula to verify the operation architecture of fig. 3, specifically, the intermediate frequency digital signal is sampled every 4 sampling points, the intermediate frequency digital signal is divided into four intermediate frequency digital sub-signals, and the data sampling rate of each intermediate frequency digital sub-signal is 1/4 of the intermediate frequency digital signal.
Then equation (1) can be converted to equation (2) by a mathematical reasoning equation:
yi＝xi×LOi，i＝0,4,8,...，4m，
yi+1＝xi+1×LOi+1，i＝0,4,8,...，4m，
yi+2＝xi+2×LOi+2，i＝0,4,8,...，4m，
yi+3＝xi+3×LOi+3i is 0,4, 8. Where i also represents a sampling point. m is a natural number greater than or equal to zero.
As can be seen from equation (2), the first intermediate frequency digital division signal is: x is the number of0,x4,x8,x12,., the first local oscillator signal is: LO0,LO4,LO8,LO12,., each baseband digital signal obtained after frequency mixing is: y is0,y4,y8,y12,...。
The second intermediate frequency digital signal is: x is the number of1,x5,x9,x13,., the second local oscillator signal is: LO1,LO5,LO9,LO13,., each baseband digital signal obtained after mixing is: y is1,y5,y9,y13,...。
Third intermediate digital sub-signalComprises the following steps: x is the number of2,x6,x10,x14,., the third local oscillator signal is: LO2,LO6,LO10,LO14,., each baseband digital signal obtained after mixing is: y is2,y6,y10,y14,...。
The fourth intermediate frequency digital sub-signal is: x is the number of3,x7,x11,x15,., the fourth local oscillator signal is: LO3,LO7,LO11,LO15,., each baseband digital signal obtained after mixing is: y is3,y7,y11,y15,...。
As can be seen from fig. 3, the data sampling rate of the data signal processed by each mixer for frequency mixing operation is 120MSPS, which meets the hardware requirement of the existing FPGA processor, so that the processing of digital frequency conversion of the digital signal with high data sampling rate can be realized by applying the parallel architecture for frequency mixing operation provided by the present invention to the FPGA processor. That is, the data signal of the high-speed data sampling rate is divided into the data signals of the low-speed data sampling rate, and the frequency conversion processing is respectively carried out on the data signals of each low-speed data sampling rate, so that the problem that the FPGA processor in the prior art cannot process the data signals of the high-speed data sampling rate is solved.
Preferably, the FPGA processor performs digital frequency conversion on the intermediate frequency digital signal sent by the ADC module to generate a baseband digital signal, and the baseband digital signal further needs to be filtered by the FIR filter before being subjected to subsequent processing.
Similarly, the FIR filter in the FPGA processing cannot process the data signal with the data sampling rate higher than 350MSPS, so that, in the embodiment, based on the same principle, each data signal is divided into multiple data signals at intervals according to the sampling points, then each data signal is filtered, and finally the filtered multiple data signals are combined to generate the I-path signal and the Q-path signal.
Setting the input signal before filtering as X ═ X0,x1,x2,x3,x4,....,xk,.... Similarly, k represents a sampling point, and the value range of the sampling point is a natural number greater than or equal to zero.
Wherein x iskData representing the kth sample point of the input signal.
The output signal after being filtered by the FIR filter is Y ═ Y0,y1,y2,y3,y4,...,yk，...。
Wherein, ykRepresenting the data of the kth sample point of the input signal after filtering by the FIR filter.
The corresponding relation between the input signal X and the output signal Y can be obtained according to the principle of the filter as formula (3):
where h is the coefficient of the filter and L is the order of the filter.
Preferably, the input signal X is decomposed in four ways by a polynomial equation such that:
then equation (3) may be equivalent to equation (4):
yi＝ti+tti+ttti+tttti(4). Wherein i herein also denotesAnd (6) sampling points.
The architecture of the FIR filter can be derived from equation (4) as shown in fig. 4. As can be seen from fig. 4, the input signal X is decimated according to the sampling points in the sequence of 4 to 1, so that the input signal X is divided into four input sub-signals, and each input sub-signal is filtered by the FIR filter to obtain a corresponding output signal.
The data sampling rate of each input sub-signal after extraction is 1/4 of the original data sampling rate of the input signal, so that the data sampling rate of the processing signal of the FIR filter can be reduced in a sequential extraction mode, and the requirement of the FPGA filter on processing the data signal with a high data sampling rate is met.
More preferably, the FIR filter is an L-order filter. It is assumed that the FIR filter in the present embodiment includes four sub-filters, which are respectively denoted as a first sub-filter H0, a second sub-filter H1, a third sub-filter H2, and a fourth sub-filter H3.
Wherein the coefficient of the first sub-filter H0 is H0、h4、…、hL-4(ii) a The coefficient of the second sub-filter H1 is H1、h5、…、hL-3(ii) a The coefficient of the third sub-filter H2 is H2、h6、…、hL-2(ii) a The fourth sub-filter H3 has a coefficient H3、h7、…、hL-1。
Specifically, as shown in fig. 4, the input signal is divided into four input sub-signals in a 4-tap-1 sequence:
first input partial signal X4iRespectively filtering the four sub-filters of the FIR filter and outputting corresponding 4 filtering sub-signals: y00, y01, y02, y 03;
second input partial signal X4i+1Outputting corresponding 4 filtering sub-signals through four sub-filters of the FIR filter respectively: y10, y11, y12, y 13.
Third input partial signal X4i+2Outputting corresponding 4 filtering sub-signals through four sub-filters of the FIR filter respectively: y20, y21, y22, y 23.
Fourth input sub-signal X4i+3The four sub-filters of the FIR filter respectively output corresponding 4 filtered partial signals, namely y30, y31, y32 and y 33.
Then four output sub-signals y can be obtained according to the formula (4) and the way of sampling points and 4-1 extraction in sequence4i、y4i+1、y4i+2、y4i+3Are respectively obtained by the following formulas:
y4i＝y00+y11+y22+y33，
y4i+1＝y01+y12+y23+y30，
y4i+2＝y02+y13+y20+y31，
y4i+3＝y03+y10+y21+y32。
thus, the final output signal is obtained by combining the 4 output sub-signals.
As can be seen from the above, the present embodiment also divides the input signal into multiple input sub-signals according to the method of sequentially extracting sampling points, so that the data sampling rate of each input sub-signal is reduced to meet the internal hardware requirement of the FIR filter; then, each input sub-signal is filtered by an FIR filter, and finally, the signals output by the FIR filters are combined to generate a final output signal.
The invention can realize the processing of the data signal of the high-speed data sampling rate by the FPGA processor without changing any hardware of the original FPGA processor, thereby greatly improving the processing efficiency of the existing FPGA processor.
Preferably, for the echo signal of the radar device, after the ADC module converts the acquired echo signal into an intermediate frequency digital signal, the intermediate frequency digital signal is first digitally down-converted by the DDC module of the FPGA processor, and then filtered by the FIR filter of the FPGA processor and then sent to a subsequent component for processing.
Therefore, in order to meet the internal hardware requirement of the existing FPGA processor, the embodiment can implement processing of the echo signal with a high-speed data sampling rate by applying the parallel architecture of the digital down-conversion and the filtering processing to the FPGA processor. Specifically, a processing architecture diagram of the echo signal of the radar apparatus by the high-speed parallel DDC and FIR filtering processing method based on the FPGA processor is obtained by combining fig. 3 and fig. 4, as shown in fig. 5.
The intermediate frequency digital signal obtained by the conversion of the ADC module is sampled in sequence according to every 4 sampling points, and then the intermediate frequency digital signal is divided into 4 intermediate frequency digital sub-signals.
And then, carrying out digital down-conversion on each intermediate frequency digital sub-signal to obtain two baseband digital signals.
The data sampling rate of each baseband digital signal and the intermediate frequency digital sub-signal is 1/4 of the original intermediate frequency digital signal.
Similarly, the FIR filter in the present embodiment includes four sub-filters: h0, H1, H2, H3.
For each baseband digital signal, dividing each baseband digital signal into 4 baseband digital sub-signals according to sampling points and a mode of sequentially extracting 1 from 4, and then sequentially filtering the four baseband digital sub-signals through four sub-filters respectively to obtain four corresponding output sub-signals.
In the embodiment, when the data signal is divided, sequential extraction is performed according to the sampling points, so that corresponding output sub-signals can be respectively selected and combined to obtain a final output signal according to the characteristic that the sampling points are extracted by 1 in the sequence 4.
Specifically, for example, each intermediate frequency digital division signal is subjected to digital down-conversion to generate an I baseband digital signal and a Q baseband digital signal.
Wherein, I road bed area digital signal has 4, marks as respectively: the first I road band digital signal, the second I road band digital signal, the third I road band digital signal and the fourth I road band digital signal.
For a first I sideband digital signal: firstly, dividing an I roadbed band digital signal into 4I roadbed band digital sub-signals according to sampling points and a mode of sequentially extracting 1 from 4, and respectively recording the I roadbed band digital sub-signals as a first I roadbed band digital sub-signal, a second I roadbed band digital sub-signal, a third I roadbed band digital sub-signal and a fourth I roadbed band digital sub-signal.
Then, the first I baseband digital partial signal is filtered by a first sub-filter H0 of the FIR filter to obtain a first I output signal y00, the second I baseband digital partial signal is filtered by a second sub-filter H1 of the FIR filter to obtain a second I output signal y01, the third I baseband digital partial signal is filtered by a third sub-filter H2 of the FIR filter to obtain a third I output signal y02, and the fourth I baseband digital partial signal is filtered by a fourth sub-filter H3 of the FIR filter to obtain a fourth I output signal y 03.
And in the same way, the 4I baseband digital signals are all subjected to the splitting and filtering processing.
That is, the first I-band digital signal passes through four sub-filters of the FIR to obtain four I-band output signals, which are: y00, y01, y02, y03,
the second I-baseband digital signal passes through four sub-filters of the FIR to obtain four I-channel output signals, which are: y10, y11, y12, y13,
the third I-baseband digital signal passes through four sub-filters of the FIR to obtain four I-channel output signals, which are: y20, y21, y22, y23,
the fourth I-baseband digital signal passes through four sub-filters of the FIR to obtain four I-channel output signals, which are: y30, y31, y32 and y 33.
After the filtering processing is finished, selecting an I path output signal corresponding to each I path baseband digital signal according to the characteristics of sampling points and 4-sampling 1 in sequence, and combining to obtain four I path baseband digital sub-signals: yI4i，yI4i+1，yI4i+2，yI4i+3。
Finally, the four I baseband digital sub-signals can be combined to generate a final I baseband digital signal.
And in the same way, correspondingly processing the Q-road baseband digital signal.
Because other devices and hardware in the FPGA processor can not process the data signals with high-speed data sampling rate, the invention can obtain four I baseband digital sub-signals to be processed respectively by a splitting mode, and because the data sampling rate of each I baseband sub-signal is 1/4 of the original data sampling rate of the I baseband digital signals, the hardware requirement of the FPGA processor can be met.
More preferably, when the center frequency of the echo signal satisfies f0 ═ 4 × n × fs + fs/M, the local oscillator signal provided in this embodiment may be used to mix the sampling signal, so that the existing processing and computing architecture of the FPGA for processing the echo signal may perform the computation according to fig. 5 and fig. 6. Where fs is the sampling rate and M is the parallel number of decompositions.
At this time, the local oscillation signals selected in the system are 1, 0, -1, 0, …. Thus, many of the ways in FIG. 5 are zero, the operation diagram of FIG. 5 can be simplified to FIG. 6; and performing extraction 2 processing on the graph 6 to obtain a graph 7.
Therefore, the invention divides the echo signal of the radar into a multi-path parallel framework for operation when in operation processing, thereby solving the problem that the FPGA processor in the prior art can not process the data signal with the data rate higher than 350 MSPS. More preferably, the present embodiment is particularly suitable for processing of data signals at ultra-high data sampling rates.
Preferably, the present embodiment only provides an operation architecture that divides the operation architecture into 4 parallel paths, and similarly, in an actual operation process, the present embodiment may be extended to an arbitrary parallel operation architecture with M paths, where M is a natural number greater than or equal to 2. The value of M can be split according to the actual data rate of the radar echo signal and the actual requirement, so that the problems that the conventional FPGA processor cannot process DDC and FIR filtering processing of the data signal with high data rate due to the limitation of hardware equipment are solved.
More preferably, as shown in fig. 8, the method for processing high-speed parallel DDC and FIR filtering based on FPGA specifically includes the following steps:
and step S1, acquiring the data sampling rate of the input signal and setting the parallel path number M according to the data sampling rate of the input signal.
And step S2, according to the parallel path number M, sequentially and circularly sampling the input signal at intervals of M sampling points, thereby dividing the input signal into M input sub-signals. Wherein the data sampling rate of each input sub-signal is 1/M of the input signal.
And step S3, performing digital down-conversion on each input sub-signal to generate a corresponding first intermediate signal and a corresponding second intermediate signal. And the data sampling rate of each of the first intermediate signal and the second intermediate signal is 1/M of that of the input signal.
As can be seen from the foregoing, the data sampling rate of the input division signal processed by the digital down conversion can be 1/M of the original input signal through the division, that is, the original high-speed data sampling rate is reduced, which is favorable for meeting the requirement of the internal hardware of the FPGA processor.
For example, in this embodiment, the original input signal has a data sampling rate of 480MSPS, and M is 4, the data sampling rate of each input sub-signal is 120MSPS, which meets the requirement of the internal hardware of the FPGA processor, and meets the operation rate of the FPGA processor on the data signal.
After the data signal is subjected to digital down-conversion, each of the generated first intermediate signal and the second intermediate signal is required to be filtered.
More preferably, the FIR filter in the present embodiment includes M sub-filters.
The present embodiment further includes step S41 of dividing each first intermediate signal into M first intermediate partial signals according to the sampling points and in a manner of sequentially M decimating 1.
And step S42, filtering the M first intermediate sub-signals of each first intermediate signal respectively through the M sub-filters of the FIR filter in sequence to obtain corresponding M first filtered sub-signals.
Step S43, selecting a corresponding first filtered sub-signal from the M first filtered sub-signals corresponding to each first intermediate signal according to the sampling points and in the order of M to 1, and combining the selected first filtered sub-signals to generate a first output sub-signal.
The number of the first output sub signals is the same as that of the output sub signals, and the data sampling rate of the first output sub signals of the weapon is 1/M of that of the input signal.
Specifically, the first output sub-signals shown in fig. 5 of this embodiment respectively include: yI4i、yI4i+1、yI4i+2、yI4i+3。
Similarly, this embodiment further includes:
and step 51, dividing each second intermediate signal into M second intermediate sub-signals according to the sampling points and in a mode of sequentially M extracting 1.
And step S52, filtering the M second intermediate partial signals of each second intermediate signal respectively through M sub-filters of the FIR filter in sequence to obtain M corresponding second filtered partial signals.
And step S53, selecting a corresponding second filtering sub-signal from the M second filtering sub-signals corresponding to each second intermediate signal according to the sampling points and in the order of M to 1, and combining to generate a second output sub-signal.
The number of the second output sub signals is the same as that of the input sub signals, and the number of the second output sub signals is M, and the data sampling rate of the first output sub signals is 1/M of that of the input signals.
The second output sub-signals as in fig. 5 of this embodiment respectively include: yQ4i、yQ4i+1、yQ4i+2、yQ4i+3。
Since the data sampling rates of the first output sub-signal and the second output sub-signal in this embodiment both meet the requirements of the FPGA processor, the M first output sub-signals and the M second output sub-signals are sent to other data processing modules of the FPGA processor for data processing, and the processing rate requirements of the other data processing modules can be met as well.
The number of the sub-filters of the FIR filter is the same as the number of the parallel paths of the digital down-conversion. I.e. the FIR filter comprises M sub-filters.
More preferably, the M sub-filters are respectively expressed as: a first sub-filter, a second sub-filter, a third sub-filter, …, and an Mth sub-filter. Wherein the coefficient of the first sub-filter is h0、hM、…、hL-MThe coefficient of the second sub-filter is h1、hM+1、…、hL-M+1The coefficient of the third sub-filter is h2、hM+2、…、hL-M+2…, the coefficient of the Mth sub-filter is hM-1、hM+M-1、…、HL—1。
Preferably, the present invention further provides an FPGA processor for executing the steps of the FPGA-based high-speed parallel DDC and FIR filter processing method according to the present invention. That is, the present invention applies the high-speed parallel DDC and FIR filtering processing method based on FPGA in the present embodiment to the existing FPGA processor, so as to solve the processing problem that the existing FPGA processor cannot process the data signal with high data rate due to the problem of the internal hardware device, and realize the processing of the data signal with high data rate without improving the internal hardware device processed by the existing FGPA.
Preferably, the embodiment implements digital down conversion and filtering processing of a data signal of a high-speed data sampling rate by the FPGA processor by using a novel efficient parallel processing architecture, and solves the problem that the FPGA processor cannot process data of the high-speed data sampling rate due to the limitation of internal hardware in the prior art; the embodiment can greatly improve the processing speed particularly when processing the data signals with ultra-high data sampling rate, and meanwhile, the invention can also expand any parallel path number of the processing framework according to the actual requirement, and is determined according to the resource usage amount and the data sampling rate of the FPGA processor. Meanwhile, the embodiment adopts a parallel architecture, and splits the data signal with the high-speed data sampling rate to reduce the data sampling rate, so that the complexity of the processing operation of the data signal of each path is correspondingly reduced.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are within the protection scope of the present invention.
Claims (8)
1. The high-speed parallel DDC and FIR filtering processing method based on FPGA is characterized by comprising the following steps:
a shunting step: acquiring the data sampling rate of an input signal, setting a parallel path number M according to the data sampling rate of the input signal, and sequentially and circularly sampling the input signal at intervals of M sampling points according to the parallel path number M, so that the input signal is divided into M input sub-signals; the data sampling rate of each input sub-signal is 1/M of the input signal;
frequency conversion: respectively carrying out digital down-conversion on each input sub-signal to generate a corresponding first intermediate signal and a corresponding second intermediate signal; the data sampling rate of each first intermediate signal and each second intermediate signal is 1/M of the input signal;
a first filtering step: firstly, dividing each first intermediate signal into M first intermediate sub-signals according to sampling points and in a mode of sequentially M1 extraction; then, filtering the M first intermediate sub-signals of each first intermediate signal through M sub-filters of an FIR filter in sequence to obtain corresponding M first filtered sub-signals; secondly, selecting a corresponding first filtering sub-signal from M first filtering sub-signals corresponding to each first intermediate signal according to sampling points and in a mode of sequentially M extracting 1 to combine to generate a first output sub-signal; the number of the first output sub signals is the same as that of the input sub signals, and the first output sub signals are M, and the data sampling rate of the first output sub signals is 1/M of that of the input signals;
a second filtering step: firstly, dividing each second intermediate signal into M second intermediate sub-signals according to sampling points and in a mode of sequentially M extracting 1; then, filtering the M second intermediate sub-signals of each second intermediate signal through M sub-filters of the FIR filter in sequence to obtain corresponding M second filtered sub-signals; secondly, selecting a corresponding second filtering sub-signal from M second filtering sub-signals corresponding to each second intermediate signal according to sampling points and in a mode of sequentially M extracting 1 to combine to generate a second output sub-signal; the number of the second output sub signals is the same as that of the input sub signals, and the number of the second output sub signals is M, and the data sampling rate of the first output sub signals is 1/M of that of the input signals;
the processing steps are as follows: and sending the M first output sub-signals and the M second output sub-signals to other data processing modules of the FPGA processor for data processing.
2. The FPGA-based high-speed parallel DDC and FIR filter processing method of claim 1, wherein M sub-filters are respectively: a first sub-filter, a second sub-filter, a third sub-filter, …, and an Mth sub-filter; wherein the coefficient of the first sub-filter is h0、hM、…、hL-MThe coefficient of the second sub-filter is h1、hM+1、…、hL-M+1The coefficient of the third sub-filter is h2、hM+2、…、hL-M+2…, the coefficient of the Mth sub-filter is hM-1、hM+M-1、…、HL—1。
3. The FPGA-based high-speed parallel DDC and FIR filter processing method of claim 1, wherein the FIR filter is an L-order filter.
4. The FPGA-based high-speed parallel DDC and FIR filter processing method of claim 3, wherein L is an integer multiple of M.
5. The FPGA-based high-speed parallel DDC and FIR filter processing method of claim 1, wherein the input signal is an intermediate frequency digital signal sent by an ADC module; the first output signal is an I baseband digital signal, and the second output signal is a Q baseband digital signal.
6. The FPGA-based high-speed parallel DDC and FIR filter processing method of claim 5, wherein the center frequency f of the input signal0＝4*n*fS+fS/M, wherein fSIs the data sampling rate.
7. The FPGA-based high-speed parallel DDC and FIR filter processing method of claim 6, wherein the performing digital down-conversion on each input divided signal means performing frequency mixing processing on each input divided signal and a local oscillator signal; wherein, the local oscillation signal is 1, 0, -1, 0, ….
8. The FPGA-based high-speed parallel DDC and FIR filter processing method of claim 1, wherein the data sampling rate of each input partial signal is less than 350 MSPS.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101707473A (en) * | 2009-09-25 | 2010-05-12 | 中国科学院上海天文台 | GHz ultra wide band digital down converter method |
| CN101827055A (en) * | 2009-03-04 | 2010-09-08 | 中国科学院电子学研究所 | Broadband digital down converter based on FPGA (Field Programmable Gate Array) |
| CN103001586A (en) * | 2012-12-12 | 2013-03-27 | 上海航天测控通信研究所 | Broadband two-channel digital down converter |
| CN103095220A (en) * | 2013-01-25 | 2013-05-08 | 西安电子科技大学 | Design method of miniature synthetic aperture radar (SAR) digital down converter based on rapidly-moving finite impulse response (FIR) filter |
| CN104954061A (en) * | 2015-05-21 | 2015-09-30 | 武汉虹信通信技术有限责任公司 | High-speed sampling low-speed processing system and high-speed sampling low-speed processing method |
| CN105024650A (en) * | 2015-07-02 | 2015-11-04 | 中国空间技术研究院 | Multi-beam signal interleaving digital down-conversion (DDC) method based on super-speed analog to digital conversion (ADC) |
| US9634679B1 (en) * | 2016-08-19 | 2017-04-25 | Guzik Technical Enterprises | Digital down converter with equalization |
| US20170324423A1 (en) * | 2016-05-04 | 2017-11-09 | Texas Instruments Incorporated | Digital down converter |
| CN107707219A (en) * | 2017-10-26 | 2018-02-16 | 电子科技大学 | A kind of high sampling rate FIR based on FPGA filters equivalent implementation method |
| US10084587B1 (en) * | 2017-07-28 | 2018-09-25 | Raytheon Company | Multifunction channelizer/DDC architecture for a digital receiver/exciter |
| CN108631809A (en) * | 2018-04-09 | 2018-10-09 | 成都泰格微电子研究所有限责任公司 | A kind of multi-channel digital TR components |
| CN109639277A (en) * | 2018-10-31 | 2019-04-16 | 上海无线电设备研究所 | A kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR |
-
2021
- 2021-03-12 CN CN202110268821.3A patent/CN113114166A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101827055A (en) * | 2009-03-04 | 2010-09-08 | 中国科学院电子学研究所 | Broadband digital down converter based on FPGA (Field Programmable Gate Array) |
| CN101707473A (en) * | 2009-09-25 | 2010-05-12 | 中国科学院上海天文台 | GHz ultra wide band digital down converter method |
| CN103001586A (en) * | 2012-12-12 | 2013-03-27 | 上海航天测控通信研究所 | Broadband two-channel digital down converter |
| CN103095220A (en) * | 2013-01-25 | 2013-05-08 | 西安电子科技大学 | Design method of miniature synthetic aperture radar (SAR) digital down converter based on rapidly-moving finite impulse response (FIR) filter |
| CN104954061A (en) * | 2015-05-21 | 2015-09-30 | 武汉虹信通信技术有限责任公司 | High-speed sampling low-speed processing system and high-speed sampling low-speed processing method |
| CN105024650A (en) * | 2015-07-02 | 2015-11-04 | 中国空间技术研究院 | Multi-beam signal interleaving digital down-conversion (DDC) method based on super-speed analog to digital conversion (ADC) |
| US20170324423A1 (en) * | 2016-05-04 | 2017-11-09 | Texas Instruments Incorporated | Digital down converter |
| US9634679B1 (en) * | 2016-08-19 | 2017-04-25 | Guzik Technical Enterprises | Digital down converter with equalization |
| US10084587B1 (en) * | 2017-07-28 | 2018-09-25 | Raytheon Company | Multifunction channelizer/DDC architecture for a digital receiver/exciter |
| CN107707219A (en) * | 2017-10-26 | 2018-02-16 | 电子科技大学 | A kind of high sampling rate FIR based on FPGA filters equivalent implementation method |
| CN108631809A (en) * | 2018-04-09 | 2018-10-09 | 成都泰格微电子研究所有限责任公司 | A kind of multi-channel digital TR components |
| CN109639277A (en) * | 2018-10-31 | 2019-04-16 | 上海无线电设备研究所 | A kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR |
Non-Patent Citations (4)
| Title |
|---|
| LONG PANG: "A highly efficient digital down converter in wide band digital radar receiver", 《2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING》 * |
| 余华章: "ISAR基带干扰信号研究与实现", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》 * |
| 顾嘉辉: "高速采样信号并行数字下变频及FIR滤波方法", 《空间电子技术》 * |
| 龚世鹏: "基于FPGA并行FIR滤波器的设计与实现", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》 * |
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