CN101827055A - Broadband digital down converter based on FPGA (Field Programmable Gate Array) - Google Patents

Abstract

The invention relates to a broadband digital down converter based on a FPGA (Field Programmable Gate Array), wherein the digital down-conversion of one path signal is realized by a piece of FPGA; after multi-path parallel data enter the FPGA, firstly, the multi-path parallel data are subjected to extraction for extracting positive integers with interval D more than 1, and a data extraction module inside the FPGA reforms a data stream input after extraction and divides the data stream to d branches, wherein the dereferencing of d is positive integer more than 1; each branch is subjected to extraction according to an extraction factor D; after the extraction, a data rate is decreased by D times, and a multi-phase filtering module carries out filtering processing on input data decreased by D times in the process of low speed so as to realize the antialiasing filtering and the anti-mirror filtering of the input signal; the output of d branches is subjected to interpolation by d' times, wherein an interpolation factor is 0; a base band complex signal is obtained after a mixing block carries out mixing integration on the data subjected to the interpolation by d' times, and a real part and a virtual part of the base band complex signal are separated to output two paths of orthogonal I and Q signals.

Description

Wideband digital low-converter based on FPGA

Technical field

The present invention relates to a kind of digital receiver, relate more specifically to a kind of based on field programmable gate array (Field Programmable Gate Array, wideband digital low-converter FPGA).

Background technology

At present, software and radio technique becomes the focus of studying in military, the commercial communication technical field both at home and abroad.Its basic ideas are: by (Analog to Digital Convertor ADC) moves on to intermediate frequency even radio frequency from base band, the signal that receives digitlization as early as possible with analog to digital converter.As a critical component in the digitlization process, digital down converter (Digital DownConvertor, DDC) at Digital Signal Processing (the Digital Signal Processing of high-speed ADC and relative low speed, DSP) set up a bridge block between the system, alleviate the unmatched contradiction of their speed.DDC becomes the digitized radar intermediate-freuqncy signal quadrature demodulation that receives I, the Q baseband signal of two-way quadrature.

The Digital Down Convert algorithm is divided into two classes: the first kind is aimed at the Digital Down Convert algorithm of quadrature sampling; Second class is the Digital Down Convert algorithm at nonopiate sampling.

Analog if signal is through behind the quadrature sampling, and digital I, Q signal are therefrom separated in the frequency data stream.But the two paths of signals of separating is the phase difference of half sampling period on the sampling time, therefore also needs further processing, obtains two-way quadrature I, the Q signal of time unanimity.At this problem, Chinese scholars has been carried out a large amount of research, has proposed serial of methods, more typically has three kinds: Hilbert converter technique, filtering interpolation method (product of numbers detection method) and low pass filtering method.

The Hilbert converter is actually 90 ° of phase shifters, by real signal is carried out the Hilbert conversion, can obtain the quadrature component of this signal.The Hilbert converter technique utilizes this fact, the way word intermediate-freuqncy signal that merit is divided in the two-way is carried out the Hilbert conversion, combine then with through another road of time-delay, form complete I, Q signal, they are extracted with shift frequency can obtain I, Q signal (as shown in Figure 1).

The interpolation filter method is carried out odd even from time domain to digital intermediate frequency data stream earlier and is extracted, and obtains I, the Q signal (supposing that I is more leading than Q) in phase difference of half sampling period.In order to guarantee the consistency of two-way, simultaneously to they interpolations of delaying time, d road time-delay interpolation 3/4 sample only, Q road time-delay interpolation 1/4 sample.Guarantee that finally two paths of signals occurs simultaneously at 3/4 sample place, realize the separation (as shown in Figure 2) of I, Q signal.

Low pass filtering method at first multiplies each other digital intermediate frequency signal respectively with the two-way orthogonal local oscillation that NCO produces, obtain two paths of signals.Pass through FIR low pass filter and extracting unit then respectively, the two-way baseband signal I and the Q (as shown in Figure 3) of output changing down.

Relative other two kinds of methods, the amount of calculation maximum of low pass filtering method, but it is applicable to the quadrature and the nonopiate sampling of analog signal, therefore uses the most extensive on the contrary.

If signal is non-quadrature sampling, the Digital Down Convert algorithm can only be used low pass filtering method so.Some ripe digital down converters that the present communications field provides all are to adopt this method.But owing in the process that realizes, do not adopt heterogeneous structure, the therefore frequency all lower (less than 150MHz) of demodulation in real time.Therefore, the research highly effective algorithm operand that reduces low pass filtering method becomes the key that can algorithm for this reason be used widely.As everyone knows, be that heterogeneous structure is realized for extracting the most effectual way of handling after the first filtering.Show that by looking into newly most high-efficiency digital down-conversion algorithm all is that digital input signal is carried out D extraction doubly, each branch carries out compound frequently then, and low-pass filtering extracts at last then.Because mixing and low-pass filtering are placed on the low data rate part after extracting, therefore reduced requirement to system hardware.Owing to only handled the partial arithmetic relevant with output, for traditional algorithm, efficient has improved D doubly in addition.But this algorithm also has shortcoming: can not realize being complementary with the bandwidth of the band processing system of back.If it is excessive to guarantee not mix extraction factor D repeatedly, then DSP is more leisurely; If extract too smallly, the burden of DSP is heavier.Because in the process of handling, digital local oscillator is that duplicate shakes, therefore follow-up filter needs two the same filters, the resource of relatively wasting FPGA.When reality realized, it needed the high performance FPGA of 3-4 sheet to realize, wherein first is used for data are extracted and mixing; Second and third sheet is used for realizing multiphase filtering; Last a slice is carried out the output of data fusion and I, Q signal.The hardware that this mode needs is many, controls also cumbersome.

In sum, above the whole bag of tricks all has pluses and minuses, has certain application limitation.

Summary of the invention

The object of the present invention is to provide a kind of wideband digital low-converter, overcoming the shortcoming of the high-efficiency digital down-conversion algorithm of mentioning in the background technology, and allow the Digital Down Convert algorithm have versatility widely based on FPGA.

For achieving the above object, the wideband digital low-converter based on FPGA provided by the invention is realized the Digital Down Convert of one road signal by a slice FPGA; FPGA inside comprises data pick-up, multiphase filtering, interpolation, mixing and base band output function module;

After the multidiameter delay data enter FPGA, at first these multidiameter delay data are extracted, the extraction interval D is the positive integer greater than 1, by the data extraction module of FPGA inside the data flow that extracts the back input is reformed, assign to d branch road, the value of d is the positive integer greater than 1; Each branch road extracts according to extracting factor D;

After extracting, data transfer rate has reduced D doubly, and the multiphase filtering module is carried out Filtering Processing in the low speed link to having reduced D input data doubly, mixes repeatedly filtering and anti-mirror image filtering to realize resisting of input signal;

D ' times of interpolation carried out in the output of d branch road, and interpolation factor is 0;

The data that to carry out d ' times of interpolation by the mixing piece carry out mixing and comprehensive after, obtain baseband complex signal, the real part of baseband complex signal is separated with imaginary part with output two-way quadrature I and Q signal.

High efficiency and broad band digital down converter based on FPGA provided by the invention adopts the high performance fpga chip of a slice to finish the huge Digital Down Convert work of amount of calculation.Compare with traditional highly effective algorithm, have the following advantage:

1. under the situation that quality of output signals remains unchanged, number of chips has only the former about 1/3, not only provides cost savings, and has reduced power consumption, and highly beneficial to the miniaturization of whole digital received system;

2. the bandwidth match that realizes input signal receives, and makes full use of the processing resource of dpch signal;

3. frequency mixer is moved on to the back of filter, multiple filtering has become real filtering, has reduced by a filter;

4. bigger owing to extracting the factor, so it can realize the real-time digital down-converted of broadband or ultra-broadband signal.

Description of drawings

Fig. 1 is digital Hilbert transform ratio juris block diagram.

Fig. 2 is a filtering interpolation method theory diagram.

Fig. 3 is the theory diagram of low pass filtering method.

Fig. 4 is a high efficiency and broad band digital down converter implementation structure.

Fig. 5 is a fraction time sampling rate transformational structure.

Fig. 6 is the heterogeneous structure of fraction time sampling rate conversion.

Fig. 7 is the realization of i bar branch road.

Fig. 8 is the efficient implementation structure of the i bar branch road of branch several times extraction.

Fig. 9 is to be the efficient implementation structure of DDC of even number in the local oscillator cycle.

Figure 10 is the efficient implementation structure of DDC when the local oscillator cycle being odd number.

Figure 11 is the amplitude/phase characteristic curves of FIR filter.

Figure 12 is the Systolic FIR Filter structure.

Figure 13 is an I signal.

Figure 14 is a Q signal.

Embodiment

The present invention is further described below in conjunction with drawings and Examples.

High efficiency and broad band digital down converter based on FPGA provided by the invention has solved two technical problems: frequency mixer is moved on to the back of filter and the coupling reception of bandwidth.The scheme that its technical problem adopted that solves is described below.

This scheme is in two steps: at first research divides the efficient realization that several times extract, and studies the efficient realization of digital down converter then.The structure that the branch several times extract as shown in Figure 5.D is an interpolation factor among the figure, and D is for extracting the factor.Sample rate before extracting is f ₁, the sample rate after the extraction is f ₂Pass between them is:

$\frac{f_1}{{\mathrm{<figure-callout\; id="2"\; label="f"\; filenames="H2009100788678E0000042.png,H2009100788678E0000051.png"\; state="\{\{state\}\}">f</figure-callout>}}_2}=\frac{D}{d}---\left(1\right)$

H (n) is the FIR low pass filter.It is anti-mirror filter and anti-mixed repeatedly filter cascade, and its passband by frequency is:

$f_c=\min \{\frac{f_1}{2},\frac{f_1}{2}*\frac{d}{D}\}---\left(2\right)$

Regard two parts in the front among Fig. 5 as a d times of interpolater, write it as heterogeneous form, for:

$H\left(z_3\right)=\underset{i=0}{\overset{d-1}{\mathrm{\&Sigma;}}}{z}_3^{-(d-1-i)}{R}_i\left(z_3^d\right)---\left(3\right)$

Wherein $R_{d-1-i}\left(z_3\right)=\underset{n=0}{\overset{M-1}{\mathrm{\&Sigma;}}}h(\mathrm{nd}+i){\left(z_3^d\right)}^{-n}---\left(4\right)$

Fig. 6 has provided the polyphase implementation structure that the branch several times extract.Because d and D are relatively prime, so, can find two integer p and q to satisfy according to the Euclid algorithm:

pd+qD＝-1 (5)

I bar branch road among Fig. 6 is extracted, and replace-1, as shown in Figure 7 with (5) formula.R _i(z ₁), i=0,1,2 ..., the d-1 and the extraction factor are as withdrawal device, with R _i(z ₁), i=0,1,2 ..., d-1 does the D phase decomposition:

$R_i\left(z_1\right)=\underset{l=0}{\overset{D-1}{\mathrm{\&Sigma;}}}{R}_{\mathrm{il}}\left(z_1^D\right)z_1^{-l}---\left(6\right)$

Wherein $R_{\mathrm{il}}\left(z_1^D\right)=\underset{n=0}{\overset{K-1}{\mathrm{\&Sigma;}}}h((\mathrm{nD}+l)d+i)z_1^{-\mathrm{nD}}---\left(7\right)$

(6) formula is updated in the structure that obtains i bar branch road among Fig. 7, can obtains the efficient implementation structure of i bar branch road, as shown in Figure 8.The comprehensive of Fig. 6 and Fig. 8 is exactly the efficient implementation structure that the branch several times extract.

The sufficient and necessary condition that digital mixer can be positioned at behind the filter is: the cycle of digital local oscillator with extract the twice that the factor equates or extract the factor.Obviously, in nonopiate sampling, require integral multiple to extract above use satisfying may to make the signal of last output to occur mixing repeatedly and can't correctly rebuild baseband signal, ways of addressing this issue divides several times to extract for using, then reasonably select to extract factor D and interpolation factor d.If the local oscillator period L is an even number, extract factor D so and get L/2, if the local oscillator cycle is a technology, extracts the factor so and get L.The selection of interpolation factor d will guarantee that the signal of exporting must satisfy the nyquist sampling law, that is:

${\mathrm{<figure-callout\; id="1"\; label="f"\; filenames="H2009100788678E0000012.png,H2009100788678E0000032.png"\; state="\{\{state\}\}">f</figure-callout>}}_1\&CenterDot;\frac{d}{D}\&GreaterEqual;B.$

Divide the situation discussion below.

Situation 1: the local oscillator period L is an even number.After process D doubly extracted, there were two digital local oscillator values in each heterogeneous branch, and they are opposite number each other, the absolute value of digital local oscillator is moved on to the back of filter, signal enters before the multiphase filter like this, need alternately multiply by+1/-1, if with the filter R of each branch _Il(z ₃) use R _Il(z ₃) replace, so+and 1/-1 also can be put into the last of total, and its efficient configuration is as shown in Figure 9.Filtering extraction mixing 1 usefulness Fig. 9 b among Fig. 9 a replaces.

Situation 2: the local oscillator period L is an odd number.Through after D doubly extracts, the digital local oscillator of each heterogeneous branch is a constant, so it can directly be put into the back of multiphase filter, and efficient implementation structure as shown in figure 10.Filtering extraction mixing 2 usefulness Figure 10 b among Figure 10 a replace.

With reference to figure 4, Fig. 9 and Figure 10, the high efficiency and broad band digital down converter characteristics in implementation process based on FPGA that the present invention proposes are:

1) different fully with traditional structure realization, its extracts earlier, multiphase filtering, mixing then, and interpolation, last comprehensive, generation I and Q signal;

2) Fig. 9 and Figure 10 median filter adopt systolic structures in FPGA, as shown in figure 12.This structure has made full use of the hardware characteristics of FPGA, and in the control of synchronised clock, the input data can automatically realize displacement realizing the convolution algorithm between input and the filter, and it has made full use of the feature of register, and the result of centre is carried out buffer memory.Though this structure has the time-delay of filter length+3 clock, because data of input can be exported a result simultaneously.Input and output are synchronous fully, so do not influence use fully;

3) selection of extracting factor D interpolation factor d also needs to take into full account the relation between local oscillator and the sample rate except satisfying nyquist sampling theorem, and the disposal ability of band processing system;

4) after two factors are determined, begin to design the FIR filter again.Determining by (2) formula of low pass filter by frequency, the outer dynamic range decision that suppresses by ADC of band.

As examples of implementation, the bandwidth that is input to the digital medium-frequency signal of DDC is 400MHz, and pulse duration is 1 μ s, and centre frequency is 1000MHz, and sample frequency is 1500MSPS, 8 tunnel inputs of high-speed data flow point, the speed of each road 187.5MHz.According to selective rule, extract factor D and be chosen as 3, interpolation factor is 0.The amplitude/phase characteristic curves of She Ji FIR filter as shown in figure 11 in view of the above.After Shu Chu I, Q signal are changed through high-speed DAC at last, with waveform such as Figure 13 and shown in Figure 14 of oscilloscope collection.

Claims (3)

1. the wideband digital low-converter based on FPGA is realized the Digital Down Convert of one road signal by a slice FPGA; FPGA inside comprises data pick-up, multiphase filtering, interpolation, mixing and base band output function module;

After the multidiameter delay data enter FPGA, at first these multidiameter delay data are extracted, the extraction interval D is the positive integer greater than 1, by the data extraction module of FPGA inside the data flow that extracts the back input is reformed, assign to d branch road, the value of d is the positive integer greater than 1; Each branch road extracts according to extracting factor D;

After extracting, data transfer rate has reduced D doubly, and the multiphase filtering module is carried out Filtering Processing in the low speed link to having reduced D input data doubly, mixes repeatedly filtering and anti-mirror image filtering to realize resisting of input signal;

D ' times of interpolation carried out in the output of d branch road, and interpolation factor is 0;

The data that to carry out d ' times of interpolation by the mixing piece carry out mixing and comprehensive after, obtain baseband complex signal, the real part of baseband complex signal is separated with imaginary part with output two-way quadrature I and Q signal.

2. the high efficiency and broad band digital down converter based on FPGA according to claim 1, wherein, described extraction is extraction earlier, back interpolation, receives with the bandwidth match that realizes signal.

3. the high efficiency and broad band digital down converter based on FPGA according to claim 1.Wherein, described multiphase filtering module realizes with systolic structures.

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