CN106100588A - A kind of restructural multi-channel digital down conversion system based on FPGA and method - Google Patents
A kind of restructural multi-channel digital down conversion system based on FPGA and method Download PDFInfo
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- CN106100588A CN106100588A CN201610592272.4A CN201610592272A CN106100588A CN 106100588 A CN106100588 A CN 106100588A CN 201610592272 A CN201610592272 A CN 201610592272A CN 106100588 A CN106100588 A CN 106100588A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The present invention provides a kind of restructural multi-channel digital down conversion system based on FPGA and method, wherein, described system includes that the I/Q signal being sequentially connected generates link, mixing link, frequency reducing module and half-band filter assembly, and described I/Q signal generates the outfan of link and includes I signal outfan and Q signal outfan；Described mixing link includes the first multiplier and the second multiplier being respectively connected with described I signal outfan and described Q signal outfan, described first multiplier is all connected with DDS with described second multiplier, the outfan output difference frequency signal of described mixing link and and frequency signal；Described frequency reducing modular reconfigurable is Integrator-Comb cic filter or multinomial decimation filter, and described half-band filter assembly includes the first half-band filter and second half-band filter of cascade.A kind of based on FPGA restructural multi-channel digital down conversion system of present invention offer and method, it is possible to the volume of simplified system architecture, and reduce the resource needed for system architecture.
Description
Technical field
The present invention relates to signal processing technology field, particularly relate to become under a kind of restructural multi-channel digital based on FPGA
Frequently system and method.
Background technology
In electronic system, its modulation demodulation system of the electromagnetic signal of transmission, host-host protocol, working frequency range and broadband etc. are deposited
In the biggest difference, it is simultaneous for the intentional or unintentional interference of electromagnetic signal of transmission and to the reception of signal and anti-interference also brings
Huge challenge, the Modern Communication System developed rapidly also requires that receiver can be to process from multiband different modulating mode
And the signal under agreement, therefore solve intercommunity, the compatibility of information transmission between different system and complete many to greatest extent
Signal under wave band, multi-mode receives the focus becoming research.
Currently, in order to realize that the signal under multiband, multi-mode is received, multichannel system tray is often used
Structure.But in multichannel system architecture, each passage is required to arrange independent signal processing module, thus makes manifold
The system architecture volume ratio in road is huger, and can cause the serious waste of resource.
Summary of the invention
It is an object of the invention to provide a kind of restructural multi-channel digital down conversion system based on FPGA and method, energy
The volume of enough simplified system architecture, and reduce the resource needed for system architecture.
For achieving the above object, the invention provides a kind of restructural multi-channel digital down conversion system based on FPGA,
Described system includes that the I/Q signal being sequentially connected generates link, mixing link, frequency reducing module and half-band filter assembly, its
In: described I/Q signal generates the input input echo-signal of link, and described I/Q signal generates the outfan of link and includes I signal
Outfan and Q signal outfan；Described mixing link includes and described I signal outfan and described Q signal outfan phase respectively
The first multiplier even and the second multiplier, described first multiplier and described second multiplier are all and direct digital synthesis technique
Device DDS is connected, the outfan output difference frequency signal of described mixing link and and frequency signal；Described frequency reducing modular reconfigurable is integration
Pectination cic filter or multinomial decimation filter, described half-band filter assembly include cascade the first half-band filter and
Second half-band filter.
Further, described Integrator-Comb cic filter includes 4 grades of cascades, the cic filter of 50 times of extractions.
Further, described multinomial decimation filter includes 5 times of multinomial decimation filters extracted.
Further, described I/Q signal generate echo signal reception antenna that link includes being sequentially connected, band filter,
Balun, IQ demodulator, filtering unit, digitized assembly and down conversion components, wherein, described IQ demodulator also with local oscillation signal
Being connected, the outfan of described IQ demodulator includes I passage and Q passage, and the signal of described I passage and Q passage is by described filtering
Assembly, digitized assembly and down conversion components generate I signal and Q signal respectively.
For achieving the above object, the present invention also provides for a kind of restructural multi-channel digital down conversion method based on FPGA,
Described method includes: generates link beforehand through I/Q signal and generates I signal and Q signal；Utilize the first multiplier by described I signal
It is mixed with the sinusoidal signal of Direct Digital Frequency Synthesizers DDS output, obtains and frequency signal；Utilize the second multiplier by institute
State the cosine signal that Q signal and Direct Digital Frequency Synthesizers DDS export to be mixed, obtain difference frequency signal；By default frequency reducing
Restructuring Module is Integrator-Comb cic filter, and with described and frequency signal, described difference frequency signal is passed sequentially through described CIC filtering
Device and half-band filter assembly, obtain the first down-conversion signal；It is multinomial filtering extraction by described default frequency reducing Restructuring Module
Device, and described difference frequency signal is passed sequentially through described multinomial decimation filter and half-band filter group with described and frequency signal
Part, obtains the second down-conversion signal, and wherein, the frequency of described second down-conversion signal is the frequency of described first down-conversion signal
10 times, described half-band filter assembly include cascade the first half-band filter and the second half-band filter.
Further, described Integrator-Comb cic filter includes 4 grades of cascades, the cic filter of 50 times of extractions.
Further, described multinomial decimation filter includes 5 times of multinomial decimation filters extracted.
Further, generate link generation I signal beforehand through I/Q signal and Q signal specifically includes: echo-signal is depended on
Secondary by echo signal reception antenna, band filter, balun, IQ demodulator, filtering unit, digitized assembly and down coversion
Assembly processes, and to generate described I signal and Q signal, wherein, described IQ demodulator is also connected with local oscillation signal, described IQ
The outfan of demodulator includes I passage and Q passage, and the signal of described I passage and Q passage passes through described filtering unit, digitized
Assembly and down conversion components generate I signal and Q signal respectively.
Further, the frequency of described I signal and described Q signal is the sinusoidal signal and remaining of 5MHz, described DDS synthesis
The frequency of string signal is 4.95MHz, and the frequency of described difference frequency signal is 0.05MHz, and described and frequency signal frequency is
9.95MHz, the frequency of described first down-conversion signal is 0.025MHz, and the frequency of described second down-conversion signal is 0.25MHz.
The present invention generates link by I/Q signal, can generate I signal and the Q signal of intermediate frequency.By I signal and Q are believed
Number respectively carry out Frequency mixing processing by mixing link, such that it is able to obtain difference frequency signal and and frequency signal.Described difference frequency signal and
With frequency signal by reconfigurable frequency reducing module and half-band filter assembly, such that it is able to first time after obtaining down coversion
Frequency variation signal and the second down-conversion signal.In the present invention can be by single pass restructural characteristic, it is achieved multi channel signals
Generation, thus simplify the volume of system architecture, and decrease the resource needed for system architecture.
Accompanying drawing explanation
The frame diagram of a kind of based on FPGA restructural multi-channel digital down conversion system that Fig. 1 provides for the present invention；
Fig. 2 is the structural representation that in the present invention, I/Q signal generates link；
The flow chart of a kind of based on FPGA restructural multi-channel digital down conversion method that Fig. 3 provides for the present invention.
Detailed description of the invention
For the technical scheme making those skilled in the art be more fully understood that in the application, real below in conjunction with the application
Execute the accompanying drawing in mode, the technical scheme in the application embodiment is clearly and completely described, it is clear that described
Embodiment is only a part of embodiment of the application rather than whole embodiments.Based on the embodiment party in the application
Formula, other embodiments all that those of ordinary skill in the art are obtained under not making creative work premise, all answer
When the scope belonging to the application protection.
The frame diagram of a kind of based on FPGA restructural multi-channel digital down conversion system that Fig. 1 provides for the present invention.As
Shown in Fig. 1, described system can include that the I/Q signal being sequentially connected generates link, mixing link, frequency reducing module and the filter of half band
Ripple device assembly, wherein:
Described I/Q signal generates the input of link can input echo-signal, and described I/Q signal generates the outfan of link
Including I signal outfan and Q signal outfan.Specifically, referring to Fig. 2, in the present embodiment, described I/Q signal generates chain
Echo signal reception antenna 11 that road includes being sequentially connected, band filter 12, balun 13, IQ demodulator 14, filtering unit 15,
Digitized assembly 16 and down conversion components 17, wherein, single-ended unbalanced echo-signal can be become poor by described balun 13
Balance-dividing signal, described differential balanced signals is such that it is able to input IQ demodulator 14.Described IQ demodulator 14 is gone back and local oscillation signal
18 are connected, and the outfan of described IQ demodulator 14 includes I passage 141 and Q passage 142, described I passage 141 and Q passage 142
Signal generates I signal and Q signal respectively by described filtering unit 15, digitized assembly 16 and down conversion components 17.At this
In embodiment, the frequency of described I signal and Q signal can be all 5MHz.
In the present embodiment, described mixing link includes and described I signal outfan and described Q signal outfan difference
The first multiplier 21 and the second multiplier 22 being connected, described first multiplier 21 and described second multiplier 22 are all with directly several
Word frequency synthesizer DDS is connected, the outfan output difference frequency signal of described mixing link and and frequency signal.
In the present embodiment, described DDS can sinusoidal signal with frequency synthesis as 4.95MHz and cosine signal.Described
The sinusoidal signal that described I signal and Direct Digital Frequency Synthesizers DDS export can be mixed by the first multiplier 21, thus
Obtain frequency be 9.95MHz and frequency signal.Described second multiplier 22 can be by described Q signal and direct digital synthesis technique
The cosine signal of device DDS output is mixed, thus obtains the difference frequency signal that frequency is 0.05MHz.
In the present embodiment, described and frequency signal and difference frequency signal can by reconfigurable frequency reducing module and half band filter
Ripple device assembly, thus obtain the first down-conversion signal and the second down-conversion signal.Specifically, described frequency reducing modular reconfigurable is long-pending
Point pectination cic filter 31 or multinomial decimation filter 32, described half-band filter assembly includes the first half band filters of cascade
Ripple device 41 and the second half-band filter 42.
In the present embodiment, it is contemplated that cic filter 41 itself includes multiplier, it is suitable for the process of High Data Rate,
Complete the extraction of bigger multiple.But the maximum side lobe attenuation of single cic filter is-13.46dB, do not reach actually used wanting
Asking, cascade too much can cause stopband attenuation to increase, thus can use 4 grades of cascades in the present embodiment, the CIC of 50 times of extractions
Wave filter, then passes through the first down-conversion signal that two half-band filter output frequencies are 0.025MHz.
In the present embodiment, owing to there is the biggest pass band damping in cic filter, and the taking out of the second down-conversion signal
Take multiple demand smaller, therefore when generating the second down-conversion signal, can be 5 times of extractions by described frequency reducing Restructuring Module
Multinomial decimation filter, afterwards through two half-band filters such that it is able to the second down coversion that output frequency is 0.25MHz
Signal.
In the present embodiment, the system modeling tool System Generator of Xilinx company can be selected
The system of the present invention is emulated by forDSP.The Matlab/Similink of this Tool Extensions MathWorks company puts down
Platform, it is provided that Digital Signal Processing (DSP) modeling environment, can be converted into reliable hardware simultaneously by digital information processing system,
Realize the conversion between abstract algorithm and FPGA.
After the emulation of System generator entirety terminates, can generate hardware co-simulation module, hardware uses
Kintex7XC7K325T Target Board, embedded 840 DSP48E modules, the resource needed for the passage that the first down-conversion signal is corresponding
As shown in table 1, from table 1 it follows that passage corresponding to the first down-conversion signal is relatively big to DSP demand, kintex7 Target Board
Meet demand.
The passage demand resource that table 1 first down-conversion signal is corresponding
| Resource name | Slice | LUT | RAM | DSP48E |
| Use resource | 709 | 2011 | 2 | 48 |
Resource needed for the passage that second down-conversion signal is corresponding can be as shown in table 2:
The passage demand resource that table 2 second down-conversion signal is corresponding
| Resource name | Slice | LUT | RAM | DSP48E |
| Use resource | 1720 | 1062 | 2 | 18 |
As shown in table 2, compared with the passage corresponding with the first down-conversion signal, the passage that the second down-conversion signal is corresponding
DSP number reduces, and Slice number increases.
In the present embodiment, for reducing hardware consumption, the mode of partial reconfiguration is selected.Wherein DDS and the first multiplier,
Second multiplier can be as static module, and frequency reducing module and half-band filter assembly in passage can be as dynamic reconfigurables
Module realizes virtual restructural multi-channel system.Whole system actual only one of which passage, but realized many by reconfiguration technique
Passage.In the present embodiment, the frequency reducing module required for each passage and half-band filter assembly can be made difference and join
Put file, realize different channel functions by different configuration files being configured to reconstruction region, thus realize multichannel
Target.For meeting the demand of disparate modules, when dividing dynamic area, to comprise all hardware resources wanting configuration file, as a means of
Source can be many compared with during single passage, but cumulative few more a lot of than the resource of multiple passages, thus save hardware resource.
The application also provides for a kind of restructural multi-channel digital down conversion method based on FPGA.Refer to Fig. 3, described side
Method includes:
Step S1: generate link beforehand through I/Q signal and generate I signal and Q signal；
Step S2: utilize the first multiplier by the sinusoidal signal of described I signal with the output of Direct Digital Frequency Synthesizers DDS
It is mixed, obtains and frequency signal；
Step S3: utilize the second multiplier by the cosine signal of described Q signal with the output of Direct Digital Frequency Synthesizers DDS
It is mixed, obtains difference frequency signal；
Step S4: be Integrator-Comb cic filter by default frequency reducing Restructuring Module, and by described difference frequency signal with described and
Frequently signal passes sequentially through described cic filter and half-band filter assembly, obtains the first down-conversion signal；
Step S5: be multinomial decimation filter by described default frequency reducing Restructuring Module, and by described difference frequency signal with described
Pass sequentially through described multinomial decimation filter and half-band filter assembly with frequency signal, obtain the second down-conversion signal, wherein,
The frequency of described second down-conversion signal is 10 times of the frequency of described first down-conversion signal, described half-band filter assembly bag
Include the first half-band filter and second half-band filter of cascade.
In one preferred implementation of the application, described Integrator-Comb cic filter includes 4 grades of cascades, 50 times of extractions
Cic filter.
In one preferred implementation of the application, described multinomial decimation filter includes 5 times of multinomial extraction filters extracted
Ripple device.
In one preferred implementation of the application, generate link generation I signal beforehand through I/Q signal and Q signal is concrete
Including:
Echo-signal is passed sequentially through echo signal reception antenna, band filter, balun, IQ demodulator, filtering unit,
Digitized assembly and down conversion components process, to generate described I signal and Q signal, wherein, described IQ demodulator also with
Local oscillation signal is connected, and the outfan of described IQ demodulator includes that I passage and Q passage, the signal of described I passage and Q passage pass through
Described filtering unit, digitized assembly and down conversion components generate I signal and Q signal respectively.
In one preferred implementation of the application, the frequency of described I signal and described Q signal is 5MHz, described DDS
Sinusoidal signal and the frequency of cosine signal of synthesis are 4.95MHz, and the frequency of described difference frequency signal is 0.05MHz, described and
Frequently the frequency of signal is 9.95MHz, and the frequency of described first down-conversion signal is 0.025MHz, described second down-conversion signal
Frequency is 0.25MHz.
It should be noted that the specific implementation of each method step above-mentioned all with the retouching of each functional module in system
State consistent, the most just repeat no more.
Therefore, the present invention generates link by I/Q signal, can generate I signal and the Q signal of intermediate frequency.By by I
Signal and Q signal carry out Frequency mixing processing by mixing link respectively, such that it is able to obtain difference frequency signal and and frequency signal.Described difference
Frequently signal and and frequency signal by reconfigurable frequency reducing module and half-band filter assembly, such that it is able to after obtaining down coversion
The first down-conversion signal and the second down-conversion signal.In the present invention can be by single pass restructural characteristic, it is achieved many
The generation of channel signal, thus simplify the volume of system architecture, and decrease the resource needed for system architecture.
Above the describing of various embodiments of the application is supplied to those skilled in the art with the purpose described.It is not
It is intended to exhaustive or is not intended to limit the invention to single disclosed embodiment.As it has been described above, the application's is various
Substitute and change will be apparent from for above-mentioned technology one of ordinary skill in the art.Therefore, although the most specifically beg for
Discuss the embodiment of some alternatives, but other embodiment will be apparent from, or those skilled in the art are relative
Easily draw.The application is intended to be included in all replacements of this present invention discussed, amendment and change, and falls
Other embodiment in the spirit and scope of above-mentioned application.
Each embodiment in this specification all uses the mode gone forward one by one to describe, identical similar between each embodiment
Part see mutually, what each embodiment stressed is the difference with other embodiments.
Although depicting the application by embodiment, it will be appreciated by the skilled addressee that the application has many deformation
With change without deviating from spirit herein, it is desirable to appended claim includes that these deformation and change are without deviating from the application
Spirit.
Claims (9)
1. a restructural multi-channel digital down conversion system based on FPGA, it is characterised in that described system includes phase successively
I/Q signal even generates link, mixing link, frequency reducing module and half-band filter assembly, wherein:
Described I/Q signal generates the input input echo-signal of link, and described I/Q signal generates the outfan of link and includes that I believes
Number outfan and Q signal outfan；
Described mixing link include the first multiplier of being respectively connected with described I signal outfan and described Q signal outfan and
Second multiplier, described first multiplier is all connected with Direct Digital Frequency Synthesizers DDS with described second multiplier, described mixed
The outfan output difference frequency signal of frequency link and and frequency signal；
Described frequency reducing modular reconfigurable is Integrator-Comb cic filter or multinomial decimation filter, described half-band filter group
Part includes the first half-band filter and second half-band filter of cascade.
System the most according to claim 1, it is characterised in that described Integrator-Comb cic filter include 4 grades of cascades, 50
The cic filter of extraction again.
System the most according to claim 1, it is characterised in that described multinomial decimation filter include 5 times extract multinomial
Decimation filter.
System the most according to claim 1, it is characterised in that described I/Q signal generates the echo that link includes being sequentially connected
Signal receiving antenna, band filter, balun, IQ demodulator, filtering unit, digitized assembly and down conversion components, wherein,
Described IQ demodulator is also connected with local oscillation signal, and the outfan of described IQ demodulator includes I passage and Q passage, described I passage and
The signal of Q passage generates I signal and Q signal respectively by described filtering unit, digitized assembly and down conversion components.
5. one kind is applied to the restructural multi-channel digital down coversion based on FPGA of any claim in Claims 1-4
Method, it is characterised in that described method includes:
Generate link beforehand through I/Q signal and generate I signal and Q signal；
The first multiplier is utilized the sinusoidal signal that described I signal and Direct Digital Frequency Synthesizers DDS export to be mixed,
Arrive and frequency signal；
The second multiplier is utilized to be mixed by the cosine signal that described Q signal and Direct Digital Frequency Synthesizers DDS export,
To difference frequency signal；
It is Integrator-Comb cic filter by default frequency reducing Restructuring Module, and by described difference frequency signal with described and frequently signal is successively
By described cic filter and half-band filter assembly, obtain the first down-conversion signal；
It is multinomial decimation filter by described default frequency reducing Restructuring Module, and by described difference frequency signal with described and frequently signal is successively
By described multinomial decimation filter and half-band filter assembly, obtain the second down-conversion signal, wherein, become for described second time
Frequently the frequency of signal is 10 times of frequency of described first down-conversion signal, and described half-band filter assembly includes the first of cascade
Half-band filter and the second half-band filter.
Method the most according to claim 5, it is characterised in that described Integrator-Comb cic filter include 4 grades of cascades, 50
The cic filter of extraction again.
Method the most according to claim 5, it is characterised in that described multinomial decimation filter include 5 times extract multinomial
Decimation filter.
Method the most according to claim 5, it is characterised in that generate link beforehand through I/Q signal and generate I signal and Q letter
Number specifically include:
Echo-signal is passed sequentially through echo signal reception antenna, band filter, balun, IQ demodulator, filtering unit, numeral
Change assembly and down conversion components to process, to generate described I signal and Q signal, wherein, described IQ demodulator also with local oscillator
Signal is connected, and the outfan of described IQ demodulator includes I passage and Q passage, and the signal of described I passage and Q passage is by described
Filtering unit, digitized assembly and down conversion components generate I signal and Q signal respectively.
Method the most according to claim 5, it is characterised in that the frequency of described I signal and described Q signal is 5MHz,
The sinusoidal signal of described DDS synthesis and the frequency of cosine signal are 4.95MHz, and the frequency of described difference frequency signal is 0.05MHz,
Described and frequency signal frequency is 9.95MHz, and the frequency of described first down-conversion signal is 0.025MHz, described second down coversion
The frequency of signal is 0.25MHz.
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| CN110474619A (en) * | 2019-07-25 | 2019-11-19 | 中国电子科技集团公司第四十三研究所 | A kind of adjustable frequency conversion system of multi-channel wide frequency band power number word and its control method |
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| CN106100588B (en) | 2023-08-25 |
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