CN205883168U

CN205883168U - Restructural multichannel digital down conversion system based on FPGA

Info

Publication number: CN205883168U
Application number: CN201620787757.4U
Authority: CN
Inventors: 钟雪燕; 李春英; 丁民豆; 张纯伟; 李志明; 许鹤
Original assignee: Nanjing Institute of Railway Technology
Current assignee: Nanjing Institute of Railway Technology
Priority date: 2016-07-25
Filing date: 2016-07-25
Publication date: 2017-01-11
Anticipated expiration: 2026-07-25

Abstract

The utility model provides a restructural multichannel digital down conversion system based on FPGA, the system includes consecutive IQ signal generation link, mixing link, falls the frequency module and partly take the wave filter subassembly, the output of IQ signal generation link includes I signal output part and Q signal output part, the mixing link include with I signal output part with first multiplier and second multiplier that Q signal output part links to each other respectively, first multiplier with the second multiplier all links to each other with DDS, the output difference frequency signal and the frequency signal of mixing link, falling frequently, the module restructural is total mark pectination CIC wave filter or multinomial decimation filter, partly take the wave filter subassembly to include that cascaded first wave filter and the second partly taken partly take the wave filter. The utility model provides a pair of restructural multichannel digital down conversion system based on FPGA, can simplified system the volume of framework to reduce the required resource of system architecture.

Description

A kind of restructural multi-channel digital down conversion system based on FPGA

Technical field

This utility model relates to signal processing technology field, particularly relates to a kind of restructural multi-channel digital based on FPGA Down conversion system.

Background technology

In electronic system, its modulation demodulation system of the electromagnetic signal of transmission, host-host protocol, working frequency range and broadband etc. are deposited In the biggest difference, it is simultaneous for the intentional or unintentional interference of electromagnetic signal of transmission and to the reception of signal and anti-interference also brings Huge challenge, the Modern Communication System developed rapidly also requires that receiver can be to process from multiband different modulating mode And the signal under agreement, therefore solve intercommunity, the compatibility of information transmission between different system and complete many to greatest extent Signal under wave band, multi-mode receives the focus becoming research.

Currently, in order to realize that the signal under multiband, multi-mode is received, multichannel system tray is often used Structure.But in multichannel system architecture, each passage is required to arrange independent signal processing module, thus makes manifold The system architecture volume ratio in road is huger, and can cause the serious waste of resource.

Utility model content

The purpose of this utility model is to provide a kind of restructural multi-channel digital down conversion system based on FPGA, it is possible to The volume of simplified system architecture, and reduce the resource needed for system architecture.

For achieving the above object, this utility model provides a kind of restructural of based on FPGA multi-channel digital down coversion system System, described system includes that the I/Q signal being sequentially connected generates link, mixing link, frequency reducing module and half-band filter assembly, Wherein: described I/Q signal generates the input input echo-signal of link, and described I/Q signal generates the outfan of link and includes that I believes Number outfan and Q signal outfan；Described mixing link includes and described I signal outfan and described Q signal outfan difference The first multiplier being connected and the second multiplier, described first multiplier and described second multiplier all close with Direct Digital frequency The DDS that grows up to be a useful person is connected, the outfan output difference frequency signal of described mixing link and and frequency signal；Described frequency reducing modular reconfigurable is long-pending Dividing pectination cic filter or multinomial decimation filter, described half-band filter assembly includes the first half-band filter of cascade With the second half-band filter.

Further, described Integrator-Comb cic filter includes 4 grades of cascades, the cic filter of 50 times of extractions.

Further, described multinomial decimation filter includes 5 times of multinomial decimation filters extracted.

Further, described I/Q signal generate echo signal reception antenna that link includes being sequentially connected, band filter, Balun, IQ demodulator, filtering unit, digitized assembly and down conversion components, wherein, described IQ demodulator also with local oscillation signal Being connected, the outfan of described IQ demodulator includes I passage and Q passage, and the signal of described I passage and Q passage is by described filtering Assembly, digitized assembly and down conversion components generate I signal and Q signal respectively.

This utility model generates link by I/Q signal, can generate I signal and the Q signal of intermediate frequency.By by I signal and Q signal carries out Frequency mixing processing by mixing link respectively, such that it is able to obtain difference frequency signal and and frequency signal.Described difference frequency signal With with frequency signal by reconfigurable frequency reducing module and half-band filter assembly, such that it is able to first after obtaining down coversion Down-conversion signal and the second down-conversion signal.Can be by single pass restructural characteristic in this utility model, it is achieved manifold The generation of road signal, thus simplify the volume of system architecture, and decrease the resource needed for system architecture.

Accompanying drawing explanation

The framework of a kind of based on FPGA restructural multi-channel digital down conversion system that Fig. 1 provides for this utility model Figure；

Fig. 2 is the structural representation that in this utility model, I/Q signal generates link.

Detailed description of the invention

For the technical scheme making those skilled in the art be more fully understood that in the application, real below in conjunction with the application Execute the accompanying drawing in mode, the technical scheme in the application embodiment is clearly and completely described, it is clear that described Embodiment is only a part of embodiment of the application rather than whole embodiments.Based on the embodiment party in the application Formula, other embodiments all that those of ordinary skill in the art are obtained under not making creative work premise, all answer When the scope belonging to the application protection.

The framework of a kind of based on FPGA restructural multi-channel digital down conversion system that Fig. 1 provides for this utility model Figure.As it is shown in figure 1, described system can include that the I/Q signal being sequentially connected generates link, mixing link, frequency reducing module and half Band filter assembly, wherein:

Described I/Q signal generates the input of link can input echo-signal, and described I/Q signal generates the outfan of link Including I signal outfan and Q signal outfan.Specifically, referring to Fig. 2, in the present embodiment, described I/Q signal generates chain Echo signal reception antenna 11 that road includes being sequentially connected, band filter 12, balun 13, IQ demodulator 14, filtering unit 15, Digitized assembly 16 and down conversion components 17, wherein, single-ended unbalanced echo-signal can be become poor by described balun 13 Balance-dividing signal, described differential balanced signals is such that it is able to input IQ demodulator 14.Described IQ demodulator 14 is gone back and local oscillation signal 18 are connected, and the outfan of described IQ demodulator 14 includes I passage 141 and Q passage 142, described I passage 141 and Q passage 142 Signal generates I signal and Q signal respectively by described filtering unit 15, digitized assembly 16 and down conversion components 17.At this In embodiment, the frequency of described I signal and Q signal can be all 5MHz.

In the present embodiment, described mixing link includes and described I signal outfan and described Q signal outfan difference The first multiplier 21 and the second multiplier 22 being connected, described first multiplier 21 and described second multiplier 22 are all with directly several Word frequency synthesizer DDS is connected, the outfan output difference frequency signal of described mixing link and and frequency signal.

In the present embodiment, described DDS can sinusoidal signal with frequency synthesis as 4.95MHz and cosine signal.Described The sinusoidal signal that described I signal and Direct Digital Frequency Synthesizers DDS export can be mixed by the first multiplier 21, thus Obtain frequency be 9.95MHz and frequency signal.Described second multiplier 22 can be by described Q signal and direct digital synthesis technique The cosine signal of device DDS output is mixed, thus obtains the difference frequency signal that frequency is 0.05MHz.

In the present embodiment, described and frequency signal and difference frequency signal can by reconfigurable frequency reducing module and half band filter Ripple device assembly, thus obtain the first down-conversion signal and the second down-conversion signal.Specifically, described frequency reducing modular reconfigurable is long-pending Point pectination cic filter 31 or multinomial decimation filter 32, described half-band filter assembly includes the first half band filters of cascade Ripple device 41 and the second half-band filter 42.

In the present embodiment, it is contemplated that cic filter 41 itself includes multiplier, it is suitable for the process of High Data Rate, Complete the extraction of bigger multiple.But the maximum side lobe attenuation of single cic filter is-13.46dB, do not reach actually used wanting Asking, cascade too much can cause stopband attenuation to increase, thus can use 4 grades of cascades in the present embodiment, the CIC of 50 times of extractions Wave filter, then passes through the first down-conversion signal that two half-band filter output frequencies are 0.025MHz.

In the present embodiment, owing to there is the biggest pass band damping in cic filter, and the taking out of the second down-conversion signal Take multiple demand smaller, therefore when generating the second down-conversion signal, can be 5 times of extractions by described frequency reducing Restructuring Module Multinomial decimation filter, afterwards through two half-band filters such that it is able to the second down coversion that output frequency is 0.25MHz Signal.

In the present embodiment, the system modeling tool System Generator for of Xilinx company can be selected System of the present utility model is emulated by DSP.The Matlab/Similink of this Tool Extensions MathWorks company puts down Platform, it is provided that Digital Signal Processing (DSP) modeling environment, can be converted into reliable hardware simultaneously by digital information processing system, Realize the conversion between abstract algorithm and FPGA.

After the emulation of System generator entirety terminates, can generate hardware co-simulation module, hardware uses Kintex7XC7K325T Target Board, embedded 840 DSP48E modules, the resource needed for the passage that the first down-conversion signal is corresponding As shown in table 1, from table 1 it follows that passage corresponding to the first down-conversion signal is relatively big to DSP demand, kintex7 Target Board Meet demand.

The passage demand resource that table 1 first down-conversion signal is corresponding

Resource name	Slice	LUT	RAM	DSP48E
					Use resource	709	2011	2	48

Resource needed for the passage that second down-conversion signal is corresponding can be as shown in table 2:

The passage demand resource that table 2 second down-conversion signal is corresponding

Resource name	Slice	LUT	RAM	DSP48E
					Use resource	1720	1062	2	18

As shown in table 2, compared with the passage corresponding with the first down-conversion signal, the passage that the second down-conversion signal is corresponding DSP number reduces, and Slice number increases.

In the present embodiment, for reducing hardware consumption, the mode of partial reconfiguration is selected.Wherein DDS and the first multiplier, Second multiplier can be as static module, and frequency reducing module and half-band filter assembly in passage can be as dynamic reconfigurables Module realizes virtual restructural multi-channel system.Whole system actual only one of which passage, but realized many by reconfiguration technique Passage.In the present embodiment, the frequency reducing module required for each passage and half-band filter assembly can be made difference and join Put file, realize different channel functions by different configuration files being configured to reconstruction region, thus realize multichannel Target.For meeting the demand of disparate modules, when dividing dynamic area, to comprise all hardware resources wanting configuration file, as a means of Source can be many compared with during single passage, but cumulative few more a lot of than the resource of multiple passages, thus save hardware resource.

Therefore, this utility model generates link by I/Q signal, can generate I signal and the Q signal of intermediate frequency.Pass through I signal and Q signal are carried out Frequency mixing processing by mixing link respectively, such that it is able to obtain difference frequency signal and and frequency signal.Institute State difference frequency signal and and signal is by reconfigurable frequency reducing module and half-band filter assembly, such that it is able to obtain down coversion frequently The first down-conversion signal afterwards and the second down-conversion signal.Can be special by single pass restructural in this utility model Property, it is achieved the generation of multi channel signals, thus simplify the volume of system architecture, and decrease the money needed for system architecture Source.

Above the describing of various embodiments of the application is supplied to those skilled in the art with the purpose described.It is not It is intended to exhaustive or is not intended to be limited to this utility model single disclosed embodiment.As it has been described above, the application Various replacements and change will be apparent from for above-mentioned technology one of ordinary skill in the art.Therefore, although had Body discusses the embodiment of some alternatives, but other embodiment will be apparent from, or those skilled in the art Relatively easily draw.The application is intended to be included in these of the present utility model all replacements discussed, amendment and change, And other embodiment in the spirit and scope of above-mentioned application that falls.

Each embodiment in this specification all uses the mode gone forward one by one to describe, identical similar between each embodiment Part see mutually, what each embodiment stressed is the difference with other embodiments.

Although depicting the application by embodiment, it will be appreciated by the skilled addressee that the application has many deformation With change without deviating from spirit herein, it is desirable to appended claim includes that these deformation and change are without deviating from the application Spirit.

Claims

1. a restructural multi-channel digital down conversion system based on FPGA, it is characterised in that described system includes phase successively I/Q signal even generates link, mixing link, frequency reducing module and half-band filter assembly, wherein:

Described I/Q signal generates the input input echo-signal of link, and described I/Q signal generates the outfan of link and includes that I believes Number outfan and Q signal outfan；

Described mixing link include the first multiplier of being respectively connected with described I signal outfan and described Q signal outfan and Second multiplier, described first multiplier is all connected with Direct Digital Frequency Synthesizers DDS with described second multiplier, described mixed The outfan output difference frequency signal of frequency link and and frequency signal；

Described frequency reducing modular reconfigurable is Integrator-Comb cic filter or multinomial decimation filter, described half-band filter group Part includes the first half-band filter and second half-band filter of cascade.

System the most according to claim 1, it is characterised in that described Integrator-Comb cic filter include 4 grades of cascades, 50 The cic filter of extraction again.

System the most according to claim 1, it is characterised in that described multinomial decimation filter include 5 times extract multinomial Decimation filter.

System the most according to claim 1, it is characterised in that described I/Q signal generates the echo that link includes being sequentially connected Signal receiving antenna, band filter, balun, IQ demodulator, filtering unit, digitized assembly and down conversion components, wherein, Described IQ demodulator is also connected with local oscillation signal, and the outfan of described IQ demodulator includes I passage and Q passage, described I passage and The signal of Q passage generates I signal and Q signal respectively by described filtering unit, digitized assembly and down conversion components.