CN109639277A - A kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR - Google Patents
A kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR Download PDFInfo
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Abstract
The invention discloses a kind of high speed signal preprocess methods filtered based on ISERDES and parallel FIR, it is characterised in that comprises the steps of: S1, is to the sample rate of high-speed ADC outputf s Data carry out ISERDES string turn and handle, be converted toLRoad sample rate isf s /LLow speed signal；S2, generalLRoad low speed sampled signal carries out parallel orthogonal transformation, handles per low speed signal all the way as the zero intermediate frequency signals comprising I, Q component；S3, parallel FIR filtering is carried out to the zero intermediate frequency signals that S2 is generated using parallel FIR filtering method, image frequency components therein is filtered out；S4, the filtered signal of parallel FIR obtain with addition is combined toLRoad sample rate isf s /LBaseband signal.Its advantage is that: in the case where signal bandwidth is big, sampling rate is high, FPGA processing speed is limited, the internal resource of FPGA device is made full use of to carry out reduction of speed processing to high speed signal, and the parallel FIR filtering method of application carries out image frequency inhibition to multi-path parallel signal, solves the problems, such as that high speed signal is handled in real time in FPGA.
Description
Technical field
The present invention relates to a kind of high speed signal preprocess methods, and in particular to one kind is filtered based on ISERDES and parallel FIR
High speed signal preprocess method.
Background technique
With the continuous development and progress of electronic science and technology and technology, high-speed ADC sampling A/D chip and extensive
Fpga chip is gradually applied in the engineering development of the wireless devices such as radar, and this high-speed ADC sampling A/D chip increases scale
The hardware structure of fpga chip can complete the work handled to the direct high-speed sampling of big bandwidth signal and in real time, utilize big bandwidth
The high advantage of signal resolution solves the problems, such as high-resolution imaging radar real time imagery.ADC chip is entered at present
Signal is generally intermediate-freuqncy signal, enters inside FPGA after ADC sampling and also needs to carry out the pretreatment such as orthogonal transformation and filtering extraction,
Then it enters back into dsp processor and carries out the processing such as subsequent imaging and parameter extraction.However, high-speed ADC sampling A/D chip exports
High-speed sampling signal limited in FPGA inter-process by FPGA maximum operating frequency, traditional preprocess method can not be applied
It is pre-processed.Currently, each IO of Xilinx company K7 Series FPGA all has input string and conversion logic resource
ISERDES, the resource may be implemented the serioparallel exchange function of high-speed sampling signal, two-forty signal are converted into multidiameter delay
Low-rate signal is convenient for FPGA inter-process.Parallel data after ISERDES serioparallel exchange also can not using it is traditional just
Hand over transform method and FIR filtering method to be handled, every road parallel signal must use orthogonalization coefficient identical with its phase into
Row parallel orthogonalization is handled, and then the method for application parallel FIR filtering carries out parallel filtering, and same be combined to is carried out after parallel filtering
Form the baseband output signal of multidiameter delay.
There is a kind of (" the high speed FIR filtering realization side based on segmentation parallel processing patent CN105281708A in the country at present
Method ") a kind of high speed FIR filter achieving method based on segmentation parallel processing is disclosed, first using sliding window method to high data
Rate data carry out segment processing, every segment data length and filter coefficient equal length, and same clock process segments of data number is
Twice of filter coefficient number, this method can reduce operating rate in filtering stage, but in data sliding window fragmentation procedure
Middle work clock is still high-frequency clock, and treatment process will receive the limitation of FPGA highest work clock.
Patent CN106817106A (" a kind of parallel FIR filtering method and FIR filter ") discloses a kind of parallel FIR filter
Wave method and FIR filter, for effectively reducing hardware spending and improving calculating speed.The inventive embodiments method includes: pair
Input signal carries out pre-add union operation and obtains the first signal to be processed, the input signal and the first signal number to be processed
Amount is all larger than all the way；Pre-multiplied is carried out to the described first signal to be processed and target filter coefficient to operate to obtain the second letter to be processed
Number, the target filter coefficient is corresponding with the described first signal to be processed；Delay conjunction is carried out to the described second signal to be processed
And it operates and obtains output signal.The invention is intended to introduce a kind of parallel FIR filtering method and FIR filter, which can be with
It effectively reduces hardware spending and improves calculating speed, but filter excessively complexity is unfavorable for Project Realization.
Patent CN103093052A (" a kind of design method of low power consumption parallel Finite Impulse Response filter ") discloses a kind of low
The design method of the parallel Finite Impulse Response filter of power consumption.This method is for 2 tunnels of linear phase FIR filter and the parallel reality on 3 tunnels
Existing, needed for making whole subfilters that there is coefficient symmetry, subfilter to realize by new Factoring Polynomials method multiplication
Device quantity can be reduced to original half, and the number of multipliers needed for whole parallel organization filter is realized also is reduced to originally
Half, corresponding cost is the increase of adder.The invention saves hardware resource compared with traditional structure, reduces realization
Power consumption, but the parallel FIR filtering on 2 roads and 3 tunnels is only provided, do not provide the parallel FIR filtering method of higher order number.
" FPGA of high-speed parallel FIR filter is real for open source literature in " system engineering and the electronic technology " of 8th phase in 2009
It is existing " a kind of parallel finite impulse respective filter structure based on multiphase filter is proposed, carry out the emulation of MATLAB floating-point
It is realized with FPGA hardware.The design can effectively improve the throughput and arithmetic speed of filter operation, but the paper is only
It is introduced for parallel filtering part, is not directed to complete Parallel Digital down coversion process.
" fire control radar technology " open source literature of 3rd phase in 2010 " becomes under the number based on parallel FIR filter structure
Frequently a kind of parallel quick FIR filter design method that can be realized in FPGA is proposed ".This method, which passes through, applies parallel multiphase
One of processing technique new distribution type Processing Algorithm, the form of multi-stage cascade is realized on filter construction, is enhanced
Hardware spending is saved in the flexibility and versatility of IF process.Serioparallel exchange operation in the paper is realized by register, is somebody's turn to do
It is relatively low that method is only applicable to sample rate, is difficult to realize in the case where sample rate is higher than FPGA highest work clock.
The present invention is based on the deficiencies of the above method, propose a kind of high speed signal filtered based on ISERDES and parallel FIR
Preprocess method, making full use of FPGA to carry ISERDES resource high speed signal is carried out serioparallel exchange is to be handled in real time
Parallel low speed signal, integrating parallel orthogonal transformation and parallel FIR filtering method carry out Digital Down Convert, complete high-speed sampling letter
Number real-time processing.
Summary of the invention
The purpose of the present invention is to provide a kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR,
The internal resource that can make full use of FPGA device, solve inside big bandwidth signal sample rate height and FPGA maximum operating frequency by
Contradiction between limit realizes that high-speed sampling signal is handled in real time inside FPGA.
In order to achieve the above object, the invention is realized by the following technical scheme:
A kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR, characterized in that include following step
It is rapid:
It S1, is f to the sample rate of high-speed ADC outputsData carry out ISERDES string turn and handle, be converted to the road L sampling
Rate is fsThe low speed signal of/L, into S2；
S2, the road L low speed signal is subjected to parallel orthogonal transformation, handling per low speed signal all the way is comprising I, Q component
Zero intermediate frequency signals, into S3；
S3, the S2 zero intermediate frequency signals generated are filtered using parallel FIR filtering method, image frequency components therein is filtered
It removes, into S4；
S4, the filtered signal of parallel FIR is carried out with addition is combined to, obtaining the road L sample rate is fsThe base band of/L
Signal.
In the step S1:
Serioparallel exchange, the input letter of ISERDES are carried out to ADC high-speed sampling signal using ISERDES resource inside FPGA
Number can be serial D DR signal or serial SDR signal, during serioparallel exchange ISERDES need two clocks, one is
Serial signal synchronised clock DCLK, when input signal is DDR signal, clock frequency is sample rate fsHalf, that is, fs/ 2, defeated
Enter signal be SDR signal when, clock frequency be equal to sample rate fs, another is the synchronised clock of parallel signal after serioparallel exchange
FCLK, clock frequency are that L/mono- of sample rate is fs/L；
During ISERDES serioparallel exchange, the test pattern of ADC sampling can be opened, to verify serioparallel exchange
The validity of data afterwards can pass through the case where not being inconsistent if there is data after serioparallel exchange and ADC reality output data
IODELAY logical resource is delayed to DCLK clock, records delay beat C of the data by entering effective in vain when1, and
Delay beat C when data are by being efficiently entering invalid2, final by (C1+C2The value of)/2 is sent into the delay beat interface of IODELAY,；
The mathematic(al) representation of the i-th road parallel signal is after serioparallel exchange
Si(n)=S (nL+i)
In formula: S (n) is serial samples signal, and i=0,1 ..., L, L are the parallel number after serioparallel exchange.
In the step S2,
Assuming that sample rate is fsThe in-phase component and quadrature component of the orthogonal transformation local oscillation signal of serial signal be respectively
I (n)=cos (2 π fL0n/fs)
Q (n)=sin (2 π fL0n/fs)
Then the in-phase component and quadrature component of the orthogonal transformation local oscillation signal of the i-th road parallel signal are respectively after parallelization
Ii(n)=I (nL+i)
=cos (2 π fL0(nL+i)/fs)
Qi(n)=I (nL+i)
=sin (2 π fL0(nL+i)/fs)
In formula: i=0,1 ..., L；
The in-phase component X_I of i-th road parallel signal after parallel orthogonal transformationi(n) with quadrature component X_Qi(n) it is respectively
X_Ii(n)=Si(n)*Ii(n)
X_Qi(n)=Si(n)*Qi(n)
In the step S3,
If the filter coefficient of serial FIR filtering is h (n), then the sub-filter coefficient of the parallel FIR filter in the i-th tunnel is
hi(n)=h (nL+i)
The process of parallel FIR filtering be by step S2 export per in-phase component and quadrature component all pass through respectively all the way
L parallelism wave filter is filtered, and by taking the 1st tunnel as an example, parallel FIR filtering can be expressed as follows
In formula: Y_I10(n) pass through the output of the 0th path filter, Y_I for first via in-phase component1L(n) same for the first via
Phase component passes through the output of L path filter；Y_Q10(n) pass through the output of the 0th path filter, Y_ for first via quadrature component
Q1L(n) pass through the output of L path filter for first via quadrature component；
L is shared after parallel FIR filtering2A in-phase component output and L2A quadrature component output.
In the step S4,
Every L In-phase output signal in step S3 is carried out with being combined to, by taking eight channel parallel FIR filtering as an example, together
The expression formula for being combined to rear 0th tunnel is
Y_I0(n)=Y_I00(n)+Y_I17(n-1)+Y_I26(n-1)
+Y_I35(n-1)+Y_I44(n-1)+Y_I53(n-1)
+Y_I62(n-1)+Y_I71(n-1)
In formula: Y_I0It (n) is the in-phase component on the 0th tunnel after parallel FIR filtering；Y_Q0It (n) is the 0th tunnel after parallel FIR filtering
Quadrature component；Y_ImnIt (n) is the in-phase component of the road m parallel signal after parallel orthogonal transformation by the same of the n-th path filter
It mutually exports, such as Y_I17It (n) is the in-phase component of the 1st road parallel signal after parallel orthogonal transformation by the same of the 7th path filter
Mutually export；Y_QmnIt (n) is the quadrature component of the road m parallel signal after parallel orthogonal transformation by the orthogonal defeated of the n-th path filter
Out, such as Y_Q17It (n) is the quadrature component of the 1st road parallel signal after parallel orthogonal transformation by the orthogonal defeated of the 7th path filter
Out.
Compared with the prior art, the present invention has the following advantages:
1, it is related to entire high speed signal pretreatment process, including from ADC sampled signal serioparallel exchange to generation baseband signal
Every single stepping；
2, portable strong, process flow can be used for any using high-speed ADC sampling A/D chip and with ISERDES logic
In the high speed signal pre-conditioning stage of the FPGA hardware framework of resource.
Detailed description of the invention
Fig. 1 is the process flow diagram of the method for the present invention；
Fig. 2 is the schematic block diagram that ISERDES string turns simultaneously process in the present invention；
Fig. 3 is the parallel FIR filtering of the 0th tunnel output of the invention and the signal flow diagram of synthesis；
Fig. 4 is the parallel FIR filtering of the 2nd tunnel output of the invention and the signal flow diagram of synthesis；
Fig. 5 is the parallel FIR filtering of the 4th tunnel output of the invention and the signal flow diagram of synthesis；
Fig. 6 is the parallel FIR filtering of the 6th tunnel output of the invention and the signal flow diagram of synthesis；
Specific embodiment
Below in conjunction with attached drawing, the present invention is further elaborated by making board by oneself.
Embodiment condition: self-control board is using EV10AQ190A high-speed ADC sampling A/D chip+XC7K325T high-performance FPGA's
Framework, the highest sample rate of EV10AQ190A sampling A/D chip are 5Gsps, in XC7K325T high-performance FPGA IODELAY and
ISERDES serial data synchronised clock is up to 800MHz, and global work clock is up to 710MHz.
The design parameter that the present invention uses is 800MHz for the sample rate of ADC sampling A/D chip, and ADC exports the speed of DDR signal
Rate is 400MHz, and serioparallel exchange number is that 8, ISERDES work clock DCLK is 400MHz, FCLK 100MHz.
As shown in Figure 1, method proposed by the present invention executes following steps to above-described embodiment condition:
It S1, is f to the sample rate of high-speed ADC outputsData carry out ISERDES string turn and handle, be converted to the road L sampling
Rate is fsThe low speed signal of/L, into S2；
Specifically, the serial D DR signal of the 400MHz of ADC output is sent into the ISERDES serioparallel exchange processing module of K7,
In order to enable the signal after the serioparallel exchange arrived is more reliable effectively, as shown in Fig. 2, can adjust DCLK phase with IODELAY module
Position makes double edges of DCLK just adopt the center position of DDR signal.It is 8 tunnels, every road by ISERDES treated signal
The sample rate of signal is 100MHz.
S2, the road L low speed signal is subjected to parallel orthogonal transformation, handling per low speed signal all the way is comprising I, Q component
Zero intermediate frequency signals, into S3；
S3, the S2 zero intermediate frequency signals generated are filtered using parallel FIR filtering method, image frequency components therein is filtered
It removes, into S4；
S4, the filtered signal of parallel FIR is carried out with addition is combined to, obtaining the road L sample rate is fsThe base band of/L
Signal.
In the step S1:
Serioparallel exchange, the input letter of ISERDES are carried out to ADC high-speed sampling signal using ISERDES resource inside FPGA
Number can be serial D DR signal or serial SDR signal, during serioparallel exchange ISERDES need two clocks, one is
Serial signal synchronised clock DCLK, when input signal is DDR signal, clock frequency is sample rate fsHalf, that is, fs/ 2, defeated
Enter signal be SDR signal when, clock frequency be equal to sample rate fs, another is the synchronised clock of parallel signal after serioparallel exchange
FCLK, clock frequency are that L/mono- of sample rate is fs/L；
During ISERDES serioparallel exchange, the test pattern of ADC sampling can be opened, to verify serioparallel exchange
The validity of data afterwards can pass through the case where not being inconsistent if there is data after serioparallel exchange and ADC reality output data
IODELAY logical resource is delayed to DCLK clock, records delay beat C of the data by entering effective in vain when1, and
Delay beat C when data are by being efficiently entering invalid2, final by (C1+C2The value of)/2 is sent into the delay beat interface of IODELAY,；
The mathematic(al) representation of the i-th road parallel signal is after serioparallel exchange
Si(n)=S (nL+i)
In formula: S (n) is serial samples signal, and i=0,1 ..., L, L are the parallel number after serioparallel exchange.
Step S2 specifically: eight road parallel signals of S1 output are subjected to parallel orthogonal conversion process, parallel orthogonal transformation
The road Hou Mei parallel signal will generate an in-phase component and a quadrature component respectively.
In the step S2,
Assuming that sample rate is fsThe in-phase component and quadrature component of the orthogonal transformation local oscillation signal of serial signal be respectively
I (n)=cos (2 π fL0n/fs)
Q (n)=sin (2 π fL0n/fs)
Then the in-phase component and quadrature component of the orthogonal transformation local oscillation signal of the i-th road parallel signal are respectively after parallelization
Ii(n)=I (nL+i)
=cos (2 π fL0(nL+i)/fs)
Qi(n)=I (nL+i)
=sin (2 π fL0(nL+i)/fs)
In formula: i=0,1 ..., L；
The in-phase component X_I of i-th road parallel signal after parallel orthogonal transformationi(n) with quadrature component X_Qi(n) it is respectively
X_Ii(n)=Si(n)*Ii(n)
X_Qi(n)=Si(n)*Qi(n)
In conjunction with Fig. 3~Fig. 6, the step S3 eight tunnel in-phase components exported and eight tunnel quadrature components are subjected to parallel FIR respectively
Filtering will be filtered with eight parallel FIR filters in parallel FIR filtering per signal all the way respectively, and
64 tunnel in-phase components and 64 tunnel quadrature components will be ultimately generated after row FIR filtering.
In the step S3,
If the filter coefficient of serial FIR filtering is h (n), then the sub-filter coefficient of the parallel FIR filter in the i-th tunnel is
hi(n)=h (nL+i)
The process of parallel FIR filtering be by step S2 export per in-phase component and quadrature component all pass through respectively all the way
L parallelism wave filter is filtered, and by taking the 1st tunnel as an example, parallel FIR filtering can be expressed as follows
In formula: Y_I10(n) pass through the output of the 0th path filter, Y_I for first via in-phase component1L(n) same for the first via
Phase component passes through the output of L path filter；Y_Q10(n) pass through the output of the 0th path filter, Y_ for first via quadrature component
Q1L(n) pass through the output of L path filter for first via quadrature component；
L is shared after parallel FIR filtering2A in-phase component and L2A quadrature component output.
In conjunction with Fig. 3-Fig. 6, the identical branch of phase in 64 tunnel in-phase components is carried out with phase additional combining, by 64 tunnels
The identical branch of phase in quadrature component carries out finally obtaining eight tunnel in-phase components and orthogonal point of eight tunnels with phase additional combining
Amount.
In the step S4,
Every L In-phase output signal in step S3 is carried out with being combined to, by taking eight channel parallel FIR filtering as an example, together
The expression formula for being combined to rear 0th tunnel is
Y_I0(n)=Y_I00(n)+Y_I17(n-1)+Y_I26(n-1)
+Y_I35(n-1)+Y_I44(n-1)+Y_I53(n-1)
+Y_I62(n-1)+Y_I71(n-1)
In formula: Y_I0It (n) is the in-phase component on the 0th tunnel after parallel FIR filtering；Y_Q0It (n) is the 0th tunnel after parallel FIR filtering
Quadrature component；Y_ImnIt (n) is the in-phase component of the road m parallel signal after parallel orthogonal transformation by the same of the n-th path filter
It mutually exports, such as Y_I17It (n) is the in-phase component of the 1st road parallel signal after parallel orthogonal transformation by the same of the 7th path filter
Mutually export；Y_QmnIt (n) is the quadrature component of the road m parallel signal after parallel orthogonal transformation by the orthogonal defeated of the n-th path filter
Out, such as Y_Q17It (n) is the quadrature component of the 1st road parallel signal after parallel orthogonal transformation by the orthogonal defeated of the 7th path filter
Out.
Although the contents of the present invention are discussed in detail through the above steps, but it should be appreciated that the description above is not
It should be considered as limitation of the present invention.After those skilled in the art have read above content, a variety of repaired for of the invention
Changing and substituting all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (5)
1. a kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR, which is characterized in that include following step
It is rapid:
It S1, is f to the sample rate of high-speed ADC outputsData carry out ISERDES string turn and handle, it is equal to be converted to the road L sample rate
For fsThe low speed signal of/L, into S2；
S2, the road L low speed signal is subjected to parallel orthogonal transformation, is handled per low speed signal all the way as in zero comprising I, Q component
Frequency signal, into S3；
S3, the S2 zero intermediate frequency signals generated are filtered using parallel FIR filtering method, image frequency components therein are filtered out,
Into S4；
S4, the filtered signal of parallel FIR is carried out with addition is combined to, obtaining the road L sample rate is fsThe baseband signal of/L.
2. a kind of high speed signal preprocess method filtered based on ISERDES and parallel FIR as described in claim 1, special
Sign is, in the step S1:
Serioparallel exchange is carried out to ADC high-speed sampling signal using ISERDES resource inside FPGA, the input signal of ISERDES can
Think serial D DR signal or serial SDR signal, ISERDES needs two clocks during serioparallel exchange, and one is serial
Signal synchronised clock DCLK, when input signal is DDR signal, clock frequency is sample rate fsHalf, that is, fs/ 2, believe in input
Number be SDR signal when, clock frequency be equal to sample rate fs, another is the synchronised clock FCLK of parallel signal after serioparallel exchange,
Clock frequency is that L/mono- of sample rate is fs/L；
During ISERDES serioparallel exchange, the test pattern of ADC sampling can be opened, to count after verifying serioparallel exchange
According to validity can pass through IODELAY the case where not being inconsistent if there is data after serioparallel exchange and ADC reality output data
Logical resource is delayed to DCLK clock, records delay beat C of the data by entering effective in vain when1And data by
Delay beat C when being efficiently entering invalid2, final by (C1+C2The delay beat interface of the value of)/2 feeding IODELAY；
The mathematic(al) representation of the i-th road parallel signal is after serioparallel exchange
Si(n)=S (nL+i)
In formula: S (n) is serial samples signal, and i=0,1 ..., L, L are the parallel number after serioparallel exchange.
3. the high speed signal preprocess method filtered as described in claim 1 based on ISERDES and parallel FIR, feature are existed
In, in the step S2,
Assuming that sample rate is fsThe in-phase component and quadrature component of the orthogonal transformation local oscillation signal of serial signal be respectively
I (n)=cos (2 π fL0n/fs)
Q (n)=sin (2 π fL0n/fs)
Then the in-phase component and quadrature component of the orthogonal transformation local oscillation signal of the i-th road parallel signal are respectively after parallelization
Ii(n)=I (nL+i)
=cos (2 π fL0(nL+i)/fs)
Qi(n)=I (nL+i)
=sin (2 π fL0(nL+i)/fs)
In formula: i=0,1 ..., L；
The in-phase component X_I of i-th road parallel signal after parallel orthogonal transformationi(n) with quadrature component X_Qi(n) it is respectively
X_Ii(n)=Si(n)*Ii(n)
X_Qi(n)=Si(n)*Qi(n)。
4. the high speed signal preprocess method filtered as described in claim 1 based on ISERDES and parallel FIR, feature are existed
In, in the step S3,
If the filter coefficient of serial FIR filtering is h (n), then the sub-filter coefficient of the parallel FIR filter in the i-th tunnel is
hi(n)=h (nL+i)
The process of parallel FIR filtering is all to pass through L respectively per in-phase component all the way and quadrature component for what step S2 was exported
Parallelism wave filter is filtered, and by taking the 1st tunnel as an example, parallel FIR filtering can be expressed as follows
In formula: Y_I10(n) pass through the output of the 0th path filter, Y_I for first via in-phase component1LIt (n) is first via in-phase component
By the output of L path filter；Y_Q10(n) pass through the output of the 0th path filter, Y_Q for first via quadrature component1L(n) it is
First via quadrature component passes through the output of L path filter；
L is shared after parallel FIR filtering2A in-phase component output and L2A quadrature component output.
5. the high speed signal preprocess method filtered as described in claim 1 based on ISERDES and parallel FIR, feature are existed
In, in the step S4,
Every L In-phase output signal in step S3 be combined to together, it is same to be harmonious by taking eight channel parallel FIR filtering as an example
The expression formula on 0 tunnel Cheng Hou is
Y_I0(n)=Y_I00(n)+Y_I17(n-1)+Y_I26(n-1)
+Y_I35(n-1)+Y_I44(n-1)+Y_I53(n-1)
+Y_I62(n-1)+Y_I71(n-1)
Y_Q0(n)=Y_Q00(n)+Y_Q17(n-1)+Y_Q26(n-1)
+Y_Q35(n-1)+Y_Q44(n-1)+Y_Q53(n-1)。
+Y_Q62(n-1)+Y_Q71(n-1)
In formula: Y_I0It (n) is the in-phase component on the 0th tunnel after parallel FIR filtering；Y_Q0(n) just for the 0th tunnel after parallel FIR filtering
Hand over component；Y_ImnIt (n) is the in-phase component of the road m parallel signal after parallel orthogonal transformation by the same mutually defeated of the n-th path filter
Out, such as Y_I17It (n) is the in-phase component of the 1st road parallel signal after parallel orthogonal transformation by the same mutually defeated of the 7th path filter
Out；Y_Qmn(n) quadrature component for the road m parallel signal after parallel orthogonal transformation passes through the orthogonal output of the n-th path filter, example
Such as Y_Q17(n) quadrature component for the 1st road parallel signal after parallel orthogonal transformation passes through the orthogonal output of the 7th path filter.
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