CN101334456A - Magnetic nuclear resonance radio frequency receiving signal digital downward conversion implementing device and method - Google Patents

Abstract

The invention relates to a device and a method for realizing the nuclear magnetic resonance radio frequency received signal digital down conversion, which are realized on the basis of the FPGA technology, the device comprises a DC-offset suppressor, a command decoder, a numerical controlled oscillator, a real part channel, an imaginary part channel and an output control interface, wherein, the DC-offset suppressor suppresses the DC-offset which is generated during the digital signal processing process; the command decoder decodes control words of the numerical controlled oscillator, the related control words of a CIC comb filter and the control words of a DDC output in a real-time manner; the numerical controlled oscillator decodes the control words of the numerical controlled oscillator in the real-time manner; the real part channel and the imaginary part channel complete the orthogonal detection operation of a digital nuclear magnetic resonance free induction decay signal from the radio frequency signal to the baseband signal; and the output control interface realizes the data communication with a follow-up digital signal processing module or a data memory. The device has strong practicability and can be flexibly updated according to user needs, thereby avoiding the crises that the whole product can not be continued or the production of the whole product is stopped due to the termination of the life cycle of key components, etc.

Description

Magnetic nuclear resonance radio frequency receiving signal digital is the implement device and the method for conversion downwards

Technical field

The present invention relates to the nuclear magnetic resonance technique field, specifically a kind of magnetic nuclear resonance radio frequency receiving signal digital is the implement device and the method for conversion downwards.

Background technology

DDC (Digital Down Converter) numeral is the nucleus module of radio frequency receiving unit in the MRI scanning control system to down-converter, be responsible for finishing functions such as the demodulation of digitizing FID (Free Induced Decay) free induction decay signal, downward data transfer rate conversion, digital filtering, directly related with MRI signal noise ratio (snr) of image SNR (Signal-to-Noise-Rate).Simultaneously, the DDC numeral also is the Modern Communication System core devices to down-converter, bears the post-processing function of digital communication signal.

Numeral in the tradition MRI scanning control system is to down-converter, and the digital signal of current digital communication system reception processing, mostly adopt special-purpose programmable DDC chip to realize, thereby the life cycle of corresponding product can be subjected to the restriction of DDC chip supplier.

In the prior art, altera corp has proposed two kinds respectively based on the DDC implementation method of FPGA, method 1: adopted FIR (the Finite Impulse Resonance) wave filter and the NCO (Numerically Controlled Oscillator) of single type, realized the real part I of base-band input signal and the numeral conversion (DDC) downwards of imaginary part Q are handled.The technical theme that realizes this conversion all has the FIR wave filter cascade that fixed decimation rate, fixed data are blocked by three rank, finish total extraction yield and be fixed as (2 * 4 * 3=) 24 numeral conversion (reference " AN 279:Digital Downconverter (DDC) Reference Design Altera July 2003, ver.2.1 " downwards; Http:// www.altera.com.cn/literature/an/an279.pdf); Method 2: adopted CIC (Cascaded Integrator Comb) wave filter and compensation FIR wave filter, realized the numeral conversion (DDC) downwards of TDM signal is handled.The technical theme that realizes this conversion is to be the cic filter of R=4 by extraction yield is constant, with the compensation FIR cascade on one 110 rank, finish total extraction yield and be fixed as (2 * 4=) 8 numeral conversion (" Designing Digital Down ConversionSystems using CIC and FIR Filters " downwards; Http:// www.altera.com.cn/support/examples/dsp-builder/exm-digit al-down-conv-cic-fir.html).

At method 1, the method that Altera proposes is to adopt a plurality of cascades with FIR wave filter of extract function, realizes the numeral conversion downwards of fixed data extraction yield, and its structure as shown in Figure 1.Because the extraction yield of FIR is all lower usually, realize the conversion of High Data Rate, need a plurality of extract function FIR wave filters that have to realize, therefore this method will take a large amount of FPGA resources, thereby causes the raising of design cost.

At method 2, the method that Altera proposes is better than method 1 from structure, it mainly is made up of cic filter and compensation FIR wave filter, the relative much less of used resource, but the extraction yield of the cic filter that this method adopted remains fixing, the principle of its realization as shown in Figure 2, therefore this method can only become a High Data Rate base-band input signal baseband signal of the constant low data rate of numerical value.

By above analysis to two kinds of DDC implementation methods of Altera, we draw such conclusion: the required FPGA resource of the implementation structure that method 1 provides is many, can not realize the real-time conversion of variable data rate simultaneously according to user's requirement; Though the implementation structure that method 2 provides can be saved the FPGA resource, can not realize the real-time conversion of variable data rate.

Summary of the invention

The problem of the real-time conversion that can not realize variable data that exists at the downward conversion method of magnetic nuclear resonance radio frequency receiving signal digital in the prior art, the technical problem to be solved in the present invention provide a kind of magnetic nuclear resonance radio frequency receiving signal digital based on Altera FPGA the technology implement device and the method for conversion downwards.

For solving the problems of the technologies described above, the technical solution used in the present invention is:

A kind of magnetic nuclear resonance radio frequency receiving signal digital of the present invention is the implement device of conversion downwards, realizes based on the FPGA technology, comprises direct current offset rejector, command decoder, digital controlled oscillator, real part passage and imaginary part passage and output control interface, wherein:

The direct current offset rejector will suppress from the dc offset of the free induction decay signal of MRI RF receiving coil and the dc offset that produces in digital signal processing, and be sent to real part passage and imaginary part passage respectively;

Command decoder, reception is from the DDC control command of microprocessor, real time parsing goes out digital controlled oscillator control word, the relevant control word of CIC comb filter and DDC output control word, delivers to cic filter assembly and output control interface in digital controlled oscillator, real part passage and the imaginary part passage respectively;

Digital controlled oscillator, the digital controlled oscillator control word that goes out according to the command decoder real time parsing, from its in-phase signal output terminal and orthogonal signal output terminal identical, the quadrature in phase of output frequency, in-phase signal and the orthogonal signal represented with two's complement respectively, wherein in-phase signal is sent into the real part passage of DDC, and orthogonal signal are sent to the imaginary part passage of DDC;

Real part passage and imaginary part passage, finish the quadrature detection operation of digitized nuclear magnetic resonance free induction decay signal from the radiofrequency signal to the baseband signal, conversion operations from the High Data Rate to the low data rate, and to the inhibition of the dc offset that in digital signal processing, produces and the processing that data are overflowed;

The output control interface, the parallel data output channel by the output data of real part passage and imaginary part passage is formed realizes the data communication with follow-up digital signal processing module or data-carrier store.

Described real part passage and imaginary part passage are formed by quadrature detection assembly, cic filter assembly, FIR compensating filter assembly, wherein:

The quadrature detection assembly, comprise the anti-overflow data cropper of radio-frequency (RF) demodulator and the anti-direct current of I type, in the radio-frequency (RF) demodulator of real part passage and imaginary part passage, do the demodulation computing with homophase output signal and positive blending output signal respectively from digital controlled oscillator, obtain the demodulating data result; The anti-overflow data cropper of the anti-direct current of I type carries out anti-direct current and anti-overflow data convergence break-in operation to the result data of passage demodulation output separately;

The cic filter assembly, forms by the variable cic filter of extraction yield, CIC output adjuster, the anti-overflow data cropper of the anti-direct current of II type, CIC gain compensator, the anti-overflow data cropper of the anti-direct current of III type successively along the control flow path direction, be used for to the sampled data from the free induction decay signal of MRI RF receiving coil extract, CIC output adjustment, gain compensation and the anti-data truncation that overflows of anti-direct current operate;

FIR compensating filter assembly, overflow cropper and form by FIR compensating filter and the anti-direct current of IV type are anti-, be used to compensate the frequency characteristic that the cic filter passband curls downwards, realize that the anti-overflow data of direct current blocks, its output and the data width of output control interface are complementary.

A kind of magnetic nuclear resonance radio frequency receiving signal digital of the present invention implementation method of conversion downwards may further comprise the steps:

By the free induction decay signal of direct current offset rejector reception from the MRI RF receiving coil, command decoder receives from the DDC control of host computer by standard serial interface and imports data,

To the DDC of the above-mentioned serial control input data conversion operations that walk abreast, the concurrent control word that parses is sent into the cic filter assembly in corresponding digital controlled oscillator, real part passage and the imaginary part passage respectively and is exported control interface in command decoder;

The assigned frequency that the quadrature detection assembly transmits according to digital controlled oscillator, two mutually orthogonal local oscillation signals of phase place and frequency spectrum, to carry out the quadrature detection operation through D.C. suppressed free induction decay signal from the MRI RF receiving coil, the real part data of output and the imaginary data cic filter assembly of sending into the real part passage respectively and the cic filter assembly and the FIR compensating filter assembly of FIR compensating filter assembly and imaginary part passage are realized the sampled data from the free induction decay signal of MRI RF receiving coil is extracted, CIC exports adjustment, the CIC gain compensation, the break-in operation of FIR compensation filter and the anti-overflow data of anti-direct current;

By the output control interface real part data and imaginary data are integrated, be sent to follow-up digital signal processing module or data-carrier store.

The above-mentioned concurrent three class control words that parse may further comprise the steps:

Definition serial communication interface agreement;

If after existing reset signal and reset operation to finish, under the CCLK clock drives, begin to intercept the level state of serial synchronous triggering signal, if high level, then begin to read serial data on the serial data bus constantly at the negative edge of thereafter first CCLK clock; According to the serial communication interface agreement, the digital controlled oscillator control word that from the serial data that serial data bus receives, parses, the relevant control word of CIC comb filter and DDC output control word, and deliver in the corresponding impact damper; According to the level state of the destination address lowest order of serial data, determining whether control word in each impact damper is loaded in the corresponding register upgrades content of registers.

Described direct current offset rejector suppresses to comprise from the DC component of the free induction decay signal of MRI RF receiving coil:

By the FIR Hi-pass filter filtering in the direct current offset rejector from the flip-flop of the simulation free induction decay signal of MRI RF receiving coil or because the non-linear flip-flop that causes of modulus switching device, thereby eliminate the direct current interference noise of MRI image, the FIR High Pass Filter Cutoff Frequency satisfies following relational expression: $0<f_C\&le;\frac{1}{2}(f_{\mathrm{RF}}-\frac{1}{2}{\mathrm{BW}}_{\mathrm{FID}}),$ F wherein _CBe the cutoff frequency of FIR Hi-pass filter, f _RFBe the carrier frequency of nuclear magnetic resonance narrow radio frequency received signal, BW _FIDBandwidth for nuclear magnetic resonance narrow radio frequency received signal.

Described quadrature detection operation comprises:

Numerical value according to frequency control word, phase control words and the spectrum control word of command decoder from the digital controlled oscillator control word that the standard serial communication interface parses, the in-phase output end of digital controlled oscillator (NCO) and quadrature output terminal be the local oscillation signal of output phase quadrature respectively, and the frequency of the nuclear magnetic resonance free induction signal that its local oscillation signal frequency is all imported with system is consistent; Wherein the homophase local oscillation signal outputs to the real part passage, and orthogonal local oscillation signal outputs to the imaginary part passage;

The MRI free induction decay signal of input in the radio-frequency (RF) demodulator of real part passage and imaginary part passage, is done the demodulation computing with homophase output signal and positive blending output signal from digital controlled oscillator respectively, obtains data result;

In the anti-overflow data cropper of the anti-direct current of I type of real part passage and imaginary part passage, to the result data bit of the output of passage demodulation separately ₃₂Bit ₃₁Bit ₃₀～bit ₁Bit ₀Carry out anti-direct current and anti-overflow data convergence break-in operation.

Described CIC output is adjusted and is comprised:

Calculate the longest output data width B _Full

Extract control word according to reality and calculate displacement control word Shift_Factor, formula is as follows:

Shift_Factor＝(B _full-1)-ceilling(B _in-1+Nlog ₂RM)；

B wherein _InBe the input data width, R is actual extraction control word, and M is the CIC differential delay, and N is a CIC progression; Ceiling (X) is an operational symbol, if X is an integer, and Ceiling (X)=X then; If X is a decimal, then Ceiling (X) equals hithermost maximum integer;

According to displacement control word Shift_Factor to the longest output data width B of CIC _FullData are made logical shift left and are handled;

Data to CIC output adjuster output in the cic filter assembly are carried out the anti-overflow data break-in operation of the anti-direct current of II type, obtain the cic filter output data of desired data length.

Described CIC gain compensation comprises:

Calculated gains compensation control word, formula is as follows:

Wherein Ceiling (X) is an operational symbol, if X is an integer, and Ceiling (X)=X then; If X is a decimal, then Ceiling (X) equals hithermost maximum integer, and N is a CIC progression; R is actual extraction control word;

Carry out the gain compensation multiplying, two multipliers are respectively the CIC gain compensation control word that parses from the output data of the anti-overflow data cropper of the anti-direct current of II type and command decoder;

By the anti-overflow data cropper of the anti-direct current of III type CIC gain compensation output data being carried out data truncation handles.

Described FIR compensation filter comprises:

The FIR wave filter adopts method for normalizing to carry out match exponents, coefficient width, input data width, output data width, receive data channel bandwidth, the setting of transitional zone bandwidth parameter, is F at the receiving cable data sampling rate wherein _SPrerequisite under, extract control word and be: the monolateral band bandwidth BW of-3dB with the corresponding relation that receives data channel bandwidth _SS=0.06875F _S/ R;

By the grand caryogenic Matlab script of operation CIC, under the condition that above-mentioned parameter is provided with, obtain the FIR compensating filter coefficient sets of corresponding maximum CIC extraction yield.

The anti-data truncation operation of overflowing of described anti-direct current comprises:

Design has I type, II type and III type and the anti-overflow data cropper of the anti-direct current of IV type respectively in quadrature detection assembly, cic filter assembly and FIR compensating filter assembly, and the anti-overflow data cropper of various anti-direct current control procedure is as follows:

The anti-overflow data cropper of anti-direct current receives n bit width input data;

Whether the high m position of judging highest byte is identical, and wherein m is the sign extended figure place of highest byte;

In this way, then intercept the n-m-1 position to the data between the n-m-L position, wherein L is the data width of exporting behind the data cutout;

Judge that whether above-mentioned data are for being worth most;

As not being to be worth most, judge then whether above-mentioned data are negative;

If not negative, then judge whether to cut out data division greater than 0.5;

If then data intercept partly adds 1;

Whether step data is negative in the judgement;

If not negative, then export L bit width data;

Finish.

If when data were negative after data intercept partly added 1, these data became complement code, go to output L bit width data step.

Be not more than 0.5 if cut out data division, judge then whether cut out data division equals 0.5;

Judge then in this way whether the data intercept part is odd number;

If above-mentioned judged result is an odd number, then goes to data intercept and partly add 1 step; If above-mentioned judged result is an even number, then goes to and judge that data intercept adds partly whether 1 back data are to be the negative step;

Not that the data that are worth most are negative if be judged as, then negative data is become true form, go to judgement and whether cut out data division greater than 0.5 step.

Whether the result that is worth most when judgment data for being to judge then whether these data are positive number;

If, then export L position positive peak, go to output L bit width data step; If these data are non-positive number, then export L position negative peak, go to output L bit width data step.

Whether whether identical if judge the high m position of highest byte result for not, then going to judgement has been the positive number step for the data of value.

Described output control interface is realized by following steps:

Receive the output mode control word;

Judge which kind of bit width mode the output mode that above-mentioned control word is represented is;

If be 32 bit width modes, then receive the input data of 32 real part passages and imaginary part passage;

Whether the imaginary part channel data of judging input is prior to the real part channel data of input;

If the result is for being, two channel data common data bus then, by imaginary data preceding, real part data after order output;

Judge whether output data is to force output mode;

If, then judge whether to exist reset signal for not;

If there is not reset signal, the synchronizing signal of output data bus and real part data and imaginary data then;

Finish.

If there is reset signal, then the reset signal low level time expanded to the CIC extraction yield and multiply by time constant 3.275 μ s;

The synchronizing signal output of no real part channel data and imaginary part notice channel data between compulsory mode or reset signal low period;

Finish.

When judging that whether output data is the judged result of forcing output mode when being, go between compulsory mode or reset signal low period no real part channel data and imaginary part and notify the synchronizing signal of channel data to export step.

When the imaginary part channel data of judging input whether prior to the result of the real part channel data of input for not, two channel data common data bus then, press the real part data preceding, imaginary data after order output;

Go to and judge whether it is to force the output mode step.

When judging that the represented output mode of above-mentioned output mode control word for the result of which kind of bit width mode is 16, then intercepts high 16 bit data of real part and imaginary part two passages;

Judge that whether above-mentioned data are for being worth most;

When above-mentioned judged result not when being worth most, the low 16 bit data convergence that is cut out is rounded on high 16 bit data of intercepting;

Go to judge input the imaginary part channel data whether prior to the real part channel data step of input.

When judging above-mentioned data when being worth most, go to imaginary part channel data the real part channel data step whether of judging input prior to importing.

The present invention has following beneficial effect and advantage:

1. practical, dirigibility is good.The data provided by the present invention device and method of conversion downwards realize based on FPGA (Field Programmable Gate Array) technology; can upgrade flexibly according to user's request; the machine product that can avoid fully causing owing to the Primary Component end of life can't continue to release or potential collision hazard such as stopping production thereupon; when realizing the digital input signal quadrature demodulation; not only can save the FPGA resource; but also can be according to the extraction yield of user's request real time altering data; thereby real-time conversion transmission signals bandwidth; output data overflowed processing unusually; inhibition is from the digital input signals; and the dc offset that in digital signal processing, produces; response time is short; have fabulous dirigibility and practicality, in the MRI scanning control system, obtained checking.

2. be widely used.Numeral of the present invention is changed (DDC) downwards, except being used for the reception processing to MRI imaging system narrow radio frequency signal, can also be used for the communication system that all need the downward translation function of data.

Description of drawings

Fig. 1 is the 1st kind of DDC implementation method process flow diagram of Altera in the prior art;

Fig. 2 is the 2nd kind of DDC implementation method process flow diagram of Altera in the prior art;

Fig. 3 is apparatus of the present invention structural representation;

Fig. 4 is the inventive method general flow chart;

Fig. 5 is the workflow diagram of the anti-overflow data cropper of anti-direct current in the inventive method;

Fig. 6 is the control flow chart of output control interface in the inventive method.

Embodiment

The present invention is directed to free induction decay (FID) signal of nuclear magnetic resonance, propose a kind of numeral based on Altera FPGA the technology downwards implement device and the method for conversion (DDC), realized digital nuclear magnetic resonance free induction decay (FID) but the numeral conversion downwards of quadrature detection, extraction yield and the channel bandwidth real time altering of signal.The VHDL source program and the fpga chip carrier of translation function are formed downwards by finishing numeral in numeral conversion (DDC) downwards.Numeral conversion (DDC) downwards is that to be loaded into the Cyclone II of altera corp series, model by the VHDL source program with the downward translation function of combine digital be that the fpga chip of EP2C70F672C6N is realized.Under the prerequisite that does not change the VHDL source program, the VHDL source program of the downward translation function of combine digital can be grafted directly in Cyclone III series, Stratix II series and the Stratix III Series FPGA chip of altera corp.

As shown in Figure 3, magnetic nuclear resonance radio frequency receiving signal digital of the present invention is the implement device of conversion downwards, realize based on the FPGA technology, comprise direct current offset rejector, command decoder, digital controlled oscillator, real part passage and imaginary part passage and output control interface, wherein:

The direct current offset rejector to suppressing from the dc offset of the free induction decay signal of MRI RF receiving coil and the dc offset that produces, and is sent to real part passage and imaginary part passage respectively in digital signal processing;

Command decoder, reception is from the DDC control command of host computer, real time parsing goes out digital controlled oscillator control word, the relevant control word of CIC comb filter and DDC output control word, delivers to cic filter assembly and output control interface in digital controlled oscillator, real part passage and the imaginary part passage respectively;

Digital controlled oscillator, the digital controlled oscillator control word that goes out according to the command decoder real time parsing, from its in-phase signal output terminal and orthogonal signal output terminal identical, the quadrature in phase of output frequency, in-phase signal and the orthogonal signal represented with 17 two's complement respectively, wherein in-phase signal is sent into the real part passage of DDC, and orthogonal signal are sent to the imaginary part passage of DDC; Digital controlled oscillator in the present embodiment (NCO) adopts the grand nuclear of IP (MegaCore) of Altera to realize; Radio-frequency (RF) demodulator (RF Demodulation) realizes by 16 * 17 the sign multiplication device that has.

Real part passage and imaginary part passage, finish the quadrature detection operation of digitized nuclear magnetic resonance free induction decay signal from the radiofrequency signal to the baseband signal, conversion operations from the High Data Rate to the low data rate, and to the inhibition of the dc offset that in digital signal processing, produces and the processing that data are overflowed;

The output control interface, 32 of the output data compositions of real part passage and imaginary part passage or the parallel data output channel of 16 bit wides realize the data communication with follow-up digital signal processing module or data-carrier store.

Described real part passage and imaginary part passage are formed by quadrature detection assembly, cic filter assembly, FIR compensating filter assembly, wherein:

The quadrature detection assembly, comprise the anti-overflow data cropper of radio-frequency (RF) demodulator and the anti-direct current of I type, in the radio-frequency (RF) demodulator of real part passage and imaginary part passage, do the demodulation computing, the demodulating data result of 33 bit wides that obtain with homophase output signal and positive blending output signal respectively from digital controlled oscillator; The anti-direct current of I type is anti-to be overflowed cropper 33 result datas of passage demodulation output is separately carried out anti-direct current and anti-overflow data convergence break-in operation;

The cic filter assembly, be made up of the variable cic filter of extraction yield, CIC output adjuster, the anti-overflow data cropper of the anti-direct current of II type, CIC gain compensator, the anti-overflow data cropper of the anti-direct current of III type successively along the control flow path direction, the sampled data that is used for the free induction decay signal of MRI RF receiving coil extracts, the break-in operation of CIC output adjustment, gain compensation and the anti-overflow data of anti-direct current;

FIR compensating filter assembly, overflow cropper and form by FIR compensating filter and the anti-direct current of IV type are anti-, be used to compensate the frequency characteristic that the cic filter passband curls downwards, realize that the anti-overflow data of direct current blocks, its output and the data width of output control interface are complementary.

All undertaken interconnected between above-mentioned each assembly in each passage by the Avalon-ST interface protocol.

In the present embodiment, command decoder is by the DDC control word of standard serial interface reception from host computer.Command decoder real time parsing from the DDC control data that receives goes out three class control words: the first kind is digital controlled oscillator (NCO) control word, comprise frequency, phase control words and output spectrum pattern control word, be used to implement the control of digital controlled oscillator (NCO) output signal frequency, phase place and amplitude polarity its rear end; The second class control word is the relevant control word of CIC comb filter, the displacement control word, extraction control word and the convergent-divergent control word that comprise the CIC comb filter are used to implement the control of cic filter, CIC output adjuster and CIC gain compensator to its rear end real part I passage and imaginary part Q passage; The 3rd class control word is a DDC output control word, is used to implement the control to output mode.In command decoder, for the decoded operation of instruction, apparatus of the present invention have adopted concurrent decoding as shown in Figure 4 to carry out link, get final product the output order analysis result in the time a drive clock, have improved the real-time of system's control.

Apparatus of the present invention course of work is as follows: free induction decay (FID) signal that receives from the MRI RF receiving coil is after through the ADC analog to digital conversion, at first be fed to the direct current offset rejector, to from analog domain or because the non-linear dc offset that causes of analog to digital converter suppresses, be distributed to the radio-frequency (RF) demodulator (RF Demodulation) of real part passage and the radio-frequency (RF) demodulator (RF Demodulation) of imaginary part passage at last.

The digital controlled oscillator control word that goes out according to the command decoder real time parsing, digital controlled oscillator (NCO) is from Cos signal output part and Sin signal output part identical, the quadrature in phase of output frequency, Cos signal and the Sin signal represented with 17 two's complement respectively, wherein the Cos signal is sent to real part (I) passage of DDC, and the Sin signal is sent to imaginary part (Q) passage of DDC.By setting the spectrum mode control word, can select the amplitude polarity of Sin output signal, to realize the control of DDC output spectrum upset.In the radio-frequency (RF) demodulator (RF Demodulation) of the radio-frequency (RF) demodulator (RF Demodulation) of real part passage and imaginary part passage, 16 bit digital free induction decay (FID) signals of no dc offset are identical with the frequency that digital controlled oscillator (NCO) is sent here respectively, two local oscillation signals of quadrature in phase, that is Cos signal and Sin signal, carry out the radio demodulating operation, obtain real part (I) component and imaginary part (Q) component of free induction decay (FID) signal simultaneously, and send into real part (I) passage and imaginary part (Q) passage of DDC respectively, thereby realize changing to baseband signal, finished quadrature detection the MRI radio frequency receiving signal from the radio frequency sampling signal.

In real part (I) passage and imaginary part (Q) passage, two baseband signals of quadrature in phase need be carried out digital signal processing operations such as the anti-overflow data of anti-direct current blocks, digital filtering, extraction.

The output data width of radio-frequency (RF) demodulator (RF Demodulation) is 33, data convergence break-in operation by the anti-overflow data cropper of the anti-direct current of I type, 17 bit data having kept from the 31st to the 15th have been avoided the generation of dc offset simultaneously again.

Data length is the anti-overflow data cropper of the anti-direct current of the I type output data of 17 bits, at first be imported into 5 grades, differential delay and be 1 cic filter, CIC between 16～32000 extracts control word according to 15 bit data width that obtain from command decoder, numerical value, it is carried out conversion operations from the high sampling rate to the low sampling rate, export the low sampling rate signal of 92 bit data width.

Owing to extract at different CIC under the condition of control word, the valid data width of cic filter output is different, therefore, the data of cic filter output need be input in the follow-up CIC output adjuster, extract control word according to different CIC, the valid data of cic filter output are moved to left to aliging with highest significant position (MSB), through the anti-overflow data cropper of the anti-direct current of II type low level is carried out data convergence break-in operation again, export the CIC output data of 18 Bit data width.

Be that the output of cic filter is also decay to some extent numerically under non-2 n power (n the is a natural number) condition when the CIC extraction yield.For the gain that makes cic filter output signal and input signal remains unchanged, the CIC gain compensation control word with 16 bit data width that the design parses according to command decoder is carried out the gain compensation operation to the CIC amplitude output signal in the CIC gain compensator.

The output data width of the gain compensator of cic filter is 35, the data convergence break-in operation by the anti-overflow data cropper of the anti-direct current of III type, and 17 bit data having kept from the 33rd to the 17th have been avoided the generation of dc offset simultaneously again.

Though cic filter does not take the multiplier resources among the FPGA, arithmetic speed is very fast, but its passband curls downwards, the transitional zone broad, thereby increase in the rear end of the anti-overflow data cropper of the anti-direct current of CIC that an input data width is that 17, exponent number are 121, the coefficient width is that 22, output data width are 42 low pass FIR compensating filter, realizes the compensation to the cic filter pass-band performance.The FIR compensating filter adopts the normalization design, and its passband width is real-time change along with the variation of CIC extraction control word.It is high more that CIC extracts control word numerical value, and the pass band width of FIR compensating filter is narrow more.

Resist the data convergence of overflowing cropper to block by the anti-direct current of IV type and overflow the inhibition operation with data, kept in the FIR compensating filter output data from the 39th to the 8th data, realized being complementary, guaranteed the maximum dynamic data output area of DDC simultaneously with the data width of 32 bit data interface of nextport universal digital signal processor NextPort.

The quadrature detection output data of sending here from real part (I) passage and imaginary part (Q) passage, in the output control interface, according to real part (I) data formerly imaginary part (Q) data after principle be incorporated into together.By selecting the DDC output mode, can 32 bit data width or 16 bit data width forms, by standard parallel communication interface sequential, send to rear end digital signal processing (DSP) module.

As shown in Figure 4, apparatus of the present invention adopt following method to realize its function: by the free induction decay signal of direct current offset rejector reception MRI RF receiving coil, command decoder receives from the DDC control of host computer by standard serial interface and imports data;

In command decoder, the DDC control input data of above-mentioned serial are carried out conversion and the instruction decode operation of serial data to parallel data, the concurrent control word that parses, if there is reset signal, the three class control words that then will parse are sent into cic filter assembly and the output control interface in corresponding digital controlled oscillator, real part passage and the imaginary part passage respectively;

The assigned frequency that the quadrature detection assembly transmits according to digital controlled oscillator, two mutually orthogonal local oscillation signals of phase place and frequency spectrum, to carry out the quadrature detection operation through D.C. suppressed free induction decay signal from the MRI RF receiving coil, the real part data of output and the imaginary data cic filter assembly of sending into the real part passage respectively and the cic filter assembly and the FIR compensating filter assembly of FIR compensating filter assembly and imaginary part passage are realized the sampled data from the free induction decay signal of MRI RF receiving coil is extracted, CIC exports adjustment, the CIC gain compensation, the anti-data truncation operation of overflowing of FIR compensation filter and anti-direct current;

By the output control interface real part data and imaginary data are integrated, be sent to follow-up digital signal processing module or data-carrier store.

The described concurrent three class control words that parse may further comprise the steps:

Definition serial communication interface agreement;

If after existing reset signal and reset operation to finish, under the CCLK clock drives, begin to intercept the level state of serial synchronous triggering signal, if high level, then begin to read serial data on the serial data bus constantly at the negative edge of thereafter first CCLK clock; According to the serial communication interface agreement, the digital controlled oscillator control word that from the serial data that serial data bus receives, parses, the relevant control word of CIC comb filter and DDC output control word, and deliver in the corresponding impact damper; According to the level state of the destination address lowest order of serial data, determine whether to be loaded in the corresponding register and upgrade content of registers.Present embodiment adopts two-level cache mechanism that control word is carried out caching, to shorten the state exchange time, improves the real-time of operation;

The dc offset of the free induction decay signal of described inhibition MRI RF receiving coil comprises:

By the FIR Hi-pass filter filtering in the direct current offset rejector from the flip-flop of the free induction decay signal of MRI RF receiving coil or because the non-linear flip-flop that causes of modulus switching device, thereby eliminate the direct current interference noise of MRI image, the cutoff frequency of FIR Hi-pass filter satisfies following relational expression: $0<f_C\&le;\frac{1}{2}(f_{\mathrm{RF}}-\frac{1}{2}{\mathrm{BW}}_{\mathrm{FID}}),$ F wherein _CBe the cutoff frequency of FIR Hi-pass filter, f _RFBe the carrier frequency of nuclear magnetic resonance narrow radio frequency received signal, BW _FIDBandwidth for nuclear magnetic resonance narrow radio frequency received signal.

In this device, the cutoff frequency f of this FIR Hi-pass filter _CBe 1MHz, sample frequency f _SBe 40MHz, filter order (Tap counts) is 121, and the coefficient width is 22, the coefficient form is a fixed-point number, and the width of input data is 16, and the output data width is 16, adopt the Blackman window function, can realize dc offset is carried out amplitude fading greater than 70dB.

The operation of described quadrature detection is responsible for finishing the demodulation of nuclear magnetic resonance free induction decay (FID) signal from the radiofrequency signal to the baseband signal, and separating between real part (I) part and imaginary part (Q) part.Quadrature detection assembly wherein is made up of radio-frequency (RF) demodulator (RF Demodulation) and the anti-overflow data cropper of the anti-direct current of I type, and its control flow may further comprise the steps:

Numerical value according to the frequency control word of command decoder from the 32 figure place controlled oscillator control words that the standard serial communication interface parses, 18 phase control words and spectrum control word, the in-phase output end of digital controlled oscillator (NCO) and quadrature output terminal are exported 17 local oscillation signals complement representation, quadrature in phase with 2 respectively, and its local oscillation signal frequency all frequency with 16 nuclear magnetic resonance free induction signals of system input is consistent; Wherein the homophase local oscillation signal outputs to the real part passage, and orthogonal local oscillation signal outputs to the imaginary part passage;

16 MRI free induction decay signals of input in the radio-frequency (RF) demodulator of real part passage and imaginary part passage, are done the demodulation computing, the data result of 33 bit wides that obtain with homophase output signal and positive blending output signal from digital controlled oscillator respectively;

For saving the FPGA resource and prevent that data from overflowing, overflow in the cropper in that the anti-direct current of I type of real part passage and imaginary part passage is anti-, 33 result data bit of passage demodulation output separately ₃₂Bit ₃₁Bit ₃₀～bit ₁Bit ₀Carry out anti-direct current and anti-overflow data convergence break-in operation; , intention is with bit ₃₁With bit ₃₀～bit ₁₅Combining and forming data layout is bit ₃₁Bit ₃₀Bit ₂₉～bit ₁₆Bit ₁₅17 quadrature detection results, wherein bit ₃₁Be highest significant position (MSB).

Described CIC output is adjusted and is comprised:

Calculate the longest output data width B _Full

Extract control word according to reality and calculate displacement control word Shift_Factor, formula is as follows:

Shift_Factor＝(B _full-1)-ceilling(B _in-1+Nlog ₂RM)；

B wherein _InBe the input data width, R is actual extraction control word, and M is the CIC differential delay, and N is a CIC progression; Ceiling (X) is an operational symbol, if X is an integer, and Ceiling (X)=X then; If X is a decimal, then Ceiling (X) equals hithermost maximum integer;

According to displacement control word Shift_Factor to the longest output data width B of CIC _FullData are made logical shift left and are handled;

The data of CIC output adjuster output in the cic filter assembly are carried out the anti-overflow data of the anti-direct current of II type blocks.

Described CIC gain compensation comprises:

Calculated gains compensation control word, formula is as follows:

$\mathrm{Scale}\_\mathrm{Factor}=2^{\mathrm{Ceiling}\left(N\log 2^{\left(R\right)}\right)}/{\left(R\right)}^N$

Wherein Ceiling (X) is an operational symbol, if X is an integer, and Ceiling (X)=X then; If X is a decimal, then Ceiling (X) equals hithermost maximum integer, and N is a CIC progression; R is actual extraction control word;

Carry out the gain compensation multiplying, two multipliers are respectively 17 CIC gain compensation control words that parse from 18 bit width output datas of the anti-overflow data cropper of the anti-direct current of II type and command decoder;

The data of CIC gain compensator output in the cic filter assembly are carried out the anti-overflow data of the anti-direct current of III type blocks.

Described FIR compensation filter comprises:

The FIR wave filter adopts method for normalizing to carry out match exponents, coefficient width, input data width, output data width, receive data channel bandwidth, the setting of transitional zone bandwidth parameter, is F at the receiving cable data sampling rate wherein _SPrerequisite under, extract control word and be: the monolateral band bandwidth BW of-3dB with the corresponding relation that receives data channel bandwidth _SS=0.06875F _S/ R;

By the grand caryogenic Matlab script of operation CIC, under the condition that above-mentioned parameter is provided with, obtain the FIR compensating filter 121 rank coefficient sets of corresponding maximum CIC extraction yield.

As shown in Figure 5, the anti-data truncation operation of overflowing of described anti-direct current comprises:

Be respectively equipped with I type, II type and III type and the anti-overflow data cropper of the anti-direct current of IV type in quadrature detection assembly, cic filter assembly and FIR compensating filter assembly, the anti-overflow data cropper of various anti-direct current control procedure is as follows:

The anti-overflow data cropper of anti-direct current receives n bit width input data;

Whether the high m position of judging highest byte is identical, and wherein m is the sign extended figure place of highest byte;

In this way, then intercept the n-m-1 position to the data between the n-m-L position, wherein L is the data width of exporting behind the data cutout;

Judge that whether above-mentioned data are for being worth most;

As not being to be worth most, judge then whether above-mentioned data are negative;

If not negative, then judge whether to cut out data division greater than 0.5;

If then data intercept partly adds 1;

Whether step data is negative in the judgement;

If not negative, then export L bit width data;

Finish.

In the above-mentioned steps, if data intercept partly adds when data are negative after 1, these data become complement code, go to output L bit width data step.Be not more than 0.5 if cut out data division, judge then whether cut out data division equals 0.5; Judge then in this way whether the data intercept part is odd number; If above-mentioned judged result is an odd number, then goes to data intercept and partly add 1 step; If above-mentioned judged result is an even number, then goes to and judge that data intercept partly is not to be the positive number step.

Not that the data that are worth most are negative if be judged as, then negative data is become true form, go to judgement and whether cut out data division greater than 0.5 step.

Whether the result that is worth most when judgment data for being to judge then whether these data are positive number; If, then export L position positive peak, go to output L bit width data step; If these data are non-positive number, then export L position negative peak, go to output L bit width data step.

Whether whether identical if judge the high m position of highest byte result for not, then going to judgement has been the positive number step for the data of value.

As shown in Figure 6, described output control interface is realized by following steps:

Receive the output mode control word;

Judge which kind of bit width mode the output mode that above-mentioned control word is represented is;

If be 32 bit width modes, then receive the input data of 32 real part passages and imaginary part passage;

Whether the imaginary part channel data of judging input is prior to the real part channel data of input;

If the result is for being, two channel data common data bus then, by imaginary data preceding, real part data after order output;

Judge whether output data is to force output mode;

If, then judge whether to exist reset signal for not;

If there is not reset signal, the synchronizing signal of output data bus and real part data and imaginary data then;

Finish.

If there is reset signal, then the reset signal low level time expanded to the CIC extraction yield and multiply by time constant 3.275 μ s; The synchronizing signal output of no real part channel data and imaginary part notice channel data between compulsory mode or reset signal low period; Finish.

When judging that whether output data is the judged result of forcing output mode when being, go between compulsory mode or reset signal low period no real part channel data and imaginary part and notify the synchronizing signal of channel data to export step.

When the imaginary part channel data of judging input whether prior to the result of the real part channel data of input for not, two channel data common data bus then, press the real part data preceding, imaginary data after order output; Go to and judge whether it is to force the output mode step.

When judging that the represented output mode of above-mentioned output mode control word for the result of which kind of bit width mode is 16, then intercepts high 16 bit data of real part and imaginary part two passages; Judge that whether above-mentioned data are for being worth most; When above-mentioned judged result not when being worth most, the low 16 bit data convergence that is cut out is rounded on high 16 bit data of intercepting; Go to judge input the imaginary part channel data whether prior to the real part channel data step of input.

When judging above-mentioned data when being worth most, go to imaginary part channel data the real part channel data step whether of judging input prior to importing.

The implement device of magnetic nuclear resonance radio frequency receiving signal digital of the present invention conversion downwards is by the operation control command word of microprocessor serial line interface reception from host computer, and the process command decoder, realizes the control to each functional module.Compare with at present disclosed two kinds of DDC structures that realize based on Altera FPGA, the DDC of this invention has diverse with it implementation structure.

The implementation procedure of Primary Component in apparatus of the present invention is below described respectively.

A. command decoder

The input end of command decoder adopts the standard serial communication interface, and its input signal comprises reset signal (RESET), serial trigger pip (CSTB), serial data (CDATA) and control clock (CCLK).Its interface protocol is defined as follows:

High level appears in 1) serial trigger pip (CSTB), and when control clock (CCLK) is negative edge, represent one group of serial input data preparation transmission, begin to receive 36 bit serial input control data (CDATA) at its next negative edge of controlling clock (CCLK);

2) serial data (CDATA) width is 36, and highest significant position MSB (Most SignificantBit) transmits at first.(bit35～bit32) is the destination address position, and thereafter 32 (bit31～bit0) is a data bit from initial high 4 of highest significant position MSB;

3) at the rising edge of control clock (CCLK), serial data appears on the serial data line (CDATA); At the negative edge of control clock (CCLK), the data on the serial data line (CDATA) can read with being stabilized;

4) " DAF destination address field " and " address contents field " of 36 bit serial input control datas (CDATA) definition as table:

Destination address (bit35～bit32)	Address contents (bit31～bit0)
		#00	Frequency control word
#
	01	Phase control words
#
	02	The spectrum control word
#
	03	CIC extracts control word
#
	04	The CIC control word that is shifted
#05			CIC gain compensation control word
	#06	DDC output mode word
Other			Keep

Table 1

5) adopt two-level cache mechanism, define the impact damper of one group of 32 bit wide and the register of one group of 32 bit wide respectively.Wherein, impact damper comprises: frequency control word buffer, phase control word buffer, spectrum control word buffer, CIC extract control word impact damper, CIC displacement control word impact damper, CIC gain compensation control word impact damper and DDC output mode word buffer; Register comprises that frequency control word register, phase control word register, spectrum control word register, CIC extract control word register, CIC displacement control word register and CIC gain compensation control word register and DDC output mode word register.Impact damper is used for various control words and the control data that buffer memory parses from the serial data mouth, needed various control words and control data when register is used to deposit DDC work, two-level cache mechanism can be guaranteed can receive new control word and control data in DDC work;

6) when RESET when low, then the content with each impact damper all writes in the corresponding registers, to upgrade register.

The implementation procedure of instruction decode is as follows:

After the RESET operation that resets is finished, under the CCLK clock drives, system begins to intercept the level state of CSTB signal, in case high level appears in the CSTB signal, so just begins to read serial data on the CDATA data line at the falling edge of thereafter first CCLK clock.

According to the serial communication interface agreement, control word that from the serial data (CDATA) that serial data line receives, parses and control control word, and deliver in the corresponding buffer register, and according to the 32nd bit level state of serial data (CDATA), determine whether to be loaded in the corresponding register, so that upgrade content of registers.

B. direct current offset rejector

From the flip-flop of analog domain or because the non-linear flip-flop that causes of modulus switching device can make the MRI image direct current interference noise occur, reduce signal noise ratio (snr) of image.In order to eliminate DC component, improve picture quality, this DDC processor has increased a direct current offset and has suppressed link.

Direct current offset suppresses link and is made of the FIR Hi-pass filter, and its cutoff frequency satisfies following relational expression: $0<f_C\&le;\frac{1}{2}(f_{\mathrm{RF}}-\frac{1}{2}{\mathrm{BW}}_{\mathrm{FID}}),$ F wherein _CBe the cutoff frequency of FIR Hi-pass filter, f _RFBe the carrier frequency of nuclear magnetic resonance narrow radio frequency received signal, BW _FIDBandwidth for nuclear magnetic resonance narrow radio frequency received signal.In this device, the cutoff frequency f of this FIR Hi-pass filter _CBe 1MHz, sample frequency f _SBe 40MHz, filter order (Tap counts) is 121, and the coefficient width is 22, the coefficient form is a fixed-point number, and the width of input data is 16, and the output data width is 16, adopt the Blackman window function, can realize dc offset is carried out amplitude fading greater than 70dB.

C. quadrature detector

Quadrature detector is made up of quadrature detection assembly and digital controlled oscillator (NCO), is responsible for finishing the demodulation of nuclear magnetic resonance free induction decay (FID) signal from the radiofrequency signal to the baseband signal, and separating between real part (I) part and imaginary part (Q) part.Quadrature detection assembly wherein is made up of radio-frequency (RF) demodulator (RF Demodulation) and the anti-overflow data cropper of the anti-direct current of I type.

32 bit frequency control words and 18 phase control words numerical value of parsing from the standard serial communication interface according to command decoder, the in-phase output end of digital controlled oscillator (NCO) and quadrature output terminal are exported 17 local oscillation signals complement representation, quadrature in phase with 2 respectively, and its local oscillation signal frequency all frequency with 16 nuclear magnetic resonance free inductions (FID) signal of system input is consistent.The homophase local oscillation signal outputs to real part (I) passage, and orthogonal local oscillation signal outputs to imaginary part (Q) passage.

Digital controlled oscillator (NCO) adopts the grand nuclear of IP (MegaCore) of Altera to realize; Radio-frequency (RF) demodulator (RF Demodulation) realizes by 16 * 17 the sign multiplication device that has.

16 nuclear magnetic resonance free induction decays (FID) signal of input, in the radio-frequency (RF) demodulator (RF Demodulation) of real part (I) passage and imaginary part (Q) passage, do the demodulation computing, the data result of 33 bit wides that the demodulation computing obtains with homophase (Cos) output signal and quadrature (Sin) output signal respectively from digital controlled oscillator (NCO).

For saving the FPGA resource and prevent that data from overflowing, the anti-cropper that overflows of the anti-direct current of I type of real part (I) passage and imaginary part (Q) passage is to 33 result data bit of passage demodulation output separately ₃₂Bit ₃₁Bit ₃₀～bit ₁Bit ₀Carry out anti-direct current and anti-overflow data convergence break-in operation, intention is with bit ₃₁With bit ₃₀～bit ₁₅Combining and forming data layout is bit ₃₁Bit ₃₀Bit ₂₉～bit ₁₆Bit ₁₅17 quadrature detection results, wherein bit ₃₁Be highest significant position (MSB).

D.CIC exports adjuster

Suppose that in the input data width be B _InPosition, differential delay M, progression N and the maximum control word R that extracts _MaxBe provided with under the condition, the full resolution output data width of CIC (Cascaded Integrator Comb) wave filter is B _FullThe position, how so no matter actual extraction control word R change, as long as B _In, M and three parameters of N remain unchanged, the overall width of cic filter output data still is a full resolution output data width B _FullThe position, but the valid data width of cic filter output is different because of the difference that extracts control word R.

For data input width B of the present invention _In=17, differential delay M=1, the maximum control word R that extracts _Max=32000, the extraction type cic filter of progression N=5 is provided with under the condition data width B of its output in full resolution output _Full=92, the data layout of output is B ₉₁B ₉₀～B ₁B ₀

When the extraction control word R of system not simultaneously, in 92 CIC full resolution output datas, the actual effectively highest significant position B of output data _MSBWith least significant bit (LSB) B _LSBThe position also be different.At the effective output data width of reality is B _OutCondition under, its highest significant position B _MSBWith least significant bit (LSB) B _LSBPosition in 92 CIC full resolution output datas is respectively: B _MSB=Ceiling (B _In-1+Nlog ₂ ^RM), B _LSB=B _MSB-B _Out+ 1, wherein, the algorithm of Ceiling (X) is: if X is an integer, and Ceiling (X)=X then; If X is a decimal, then Ceiling (X) equals hithermost maximum integer.

For under different extraction control word conditions, extract actual effectively CIC output data, in CIC output adjuster, according to CIC displacement control word numerical values recited, 92 CIC full resolution output datas are made logical shift left handle operation, make and extract under the control word condition that the highest significant position of 92 CIC full resolution output datas overlaps with the actual effectively highest significant position of CIC output data in difference.

CIC displacement control word (Shift Factor) and B _Full, B _In, B _MSB, the contextual definition between N, R and the M is: Shift_Factor=(B _Full-1)-B _MSB=(B _Full-1)-ceilling (B _In-1+Nlog ₂RM).This numerical value is responsible for given by host computer, command decoder parses it from the control command that receives then, then is sent to CIC output adjuster, so that the logical shift left operation of the full width of cloth output data of control CIC.

Shift_Factor=75-ceilling (5log is set under the condition in parameter of the present invention ₂R).According to different extraction control word R, in CIC output adjuster, do the not shift left operation of isotopic number, make and extract under the control word condition that the highest significant position of 92 CIC full resolution output datas overlaps with the actual effectively highest significant position of CIC output data in difference.

Be positioned at B in order to obtain highest significant position _MSB, data length is B _OutActual effectively CIC output data, handle the operation except the CIC output data being made the data logical shift left, also need be in the anti-overflow data cropper of the anti-direct current of II type, further 92 CIC full resolution output datas are done anti-direct current and anti-data convergence truncation operation of overflowing, wherein intercepted data length is defined as Rounding=(B _MSB+ 1)-B _Out, like this, the B of 92 CIC full resolution output datas before the data truncation _Rounding+1The position has become that width is B after the data truncation operation _OutThe actual effectively least significant bit (LSB) of output data.Require B in the design _OutUnder the situation of=18 bit data width, the data length Rounding that need block also can obtain by following formula: Rounding=-1+Ceiling (5Log ₂ ^R).

The E.CIC gain compensator

When CIC extracts control word R is that the cic filter output signal is also decay to some extent numerically, the amplitude of decay under non-2 n power (n the is a natural number) condition $\mathrm{Attenu}=R^N/2^{\mathrm{Ceiling}\left(N\log 2^{\left(R\right)}\right)},$ The decay numerical range be (0.5..1] times.

For the gain that makes cic filter output signal and input signal remains unchanged, set up CIC gain compensator link at the output terminal of the anti-overflow data cropper of the anti-direct current of II type.Gain compensation proportional control word $\mathrm{Scale}\_\mathrm{Factor}=2^{\mathrm{CEILING}\left(N\log 2^{\left(R\right)}\right)}/{\left(R\right)}^N=2^{\mathrm{CEILING}\left(5\log 2^{\left(R\right)}\right)}/{\left(R\right)}^5,$ The span of Scale_Factor be [1..2), data layout is 2 ⁰.2 ^-1... 2 ^-15Extraction control word R=2 when cic filter ⁿThe time, Scale_Factor=1.000 is when R ≠ 2 ⁿThe time, 1＜Scale_Factor＜2.This CIC gain compensation control word (Scale_Factor) by outer microprocessor in advance according to formula $\mathrm{Scale}\_\mathrm{Factor}=2^{\mathrm{CEILING}\left(5\log 2^{\left(R\right)}\right)}/{\left(R\right)}^5$ Calculate, obtain 16 signless gain compensation control words, and send to command decoder by parallel communication interface.In command decoder, 16 signless gain compensation control words are extended to the gain compensation control word that 17 bit strips have plus sign.

This CIC gain compensator is made up of 18 * 17 multipliers by symbol, output with 2 complement representation, 35 bit width data.Two multipliers come from 18 bit width output datas of the anti-overflow data cropper of the anti-direct current of II type and 17 CIC gain compensation control words that command decoder parses respectively.

After the CIC gain compensator, designed an anti-direct current of III type and anti-overflow data cropper, 35 output datas of CIC gain compensator are carried out data convergences block, to save the FPGA resource and to prevent that data from overflowing.

The F.FIR compensating filter

The FIR compensating filter is used to compensate the frequency characteristic that the cic filter passband curls downwards.In the present invention, the FIR wave filter adopts the normalization method for designing, and its exponent number (Tap counts) is 121, and coefficient is the fixed-point number of 22 bit wides, and the width of input data is 17, and the output data width is 42, pass band width position 0.06, and transition band width is 0.02.At the receiving cable data sampling rate is F _SPrerequisite under, the corresponding relation that extracts control word and Data Receiving channel bandwidth is: the monolateral band bandwidth BW of-3dB _SS=0.06875F _S/ R.

By the grand caryogenic Matlab script of operation Altera CIC, under the condition that above-mentioned parameter is provided with, obtain the FIR compensating filter 121 rank coefficient sets of corresponding different CIC extraction yields.

The FIR compensating filter that adopts this method to realize, its passband has the frequency characteristic that upwarps, passband position at the passband position at fundamental frequency place and cic filter fundamental frequency place is consistent, and the passband position of its image frequency characteristic is just consistent with the stopband position of cic filter image frequency, like this, the junction filter that obtains by CIC and FIR, had good base band bandpass characteristics, suppressed simultaneously the image frequency of the two again effectively, made whole M RI radio frequency reception channel have Spurious Free Dynamic Range (SFDR) greater than 102dB.

In order to realize that carrying out data width with the wide data of 32 bit data output control interface is complementary, adopt that anti-direct current is anti-to overflow that cropper (IV) carries out anti-direct current to the output of 42 FIR compensating filters and anti-data convergence of overflowing is blocked.

G. the anti-overflow data cropper of anti-direct current

In order to reduce the data width of follow-up digital signal processing link, save the FPGA resource and prevent that data from overflowing, design has the anti-overflow data cropper of I type, II type, III type and the anti-direct current of IV type respectively in quadrature detection assembly, cic filter assembly and FIR compensating filter assembly.

The input data width of supposing the anti-overflow data cropper of anti-direct current is the n position, and the sign extended figure place of highest byte is the m position, and m 〉=1, and the data width of exporting behind the data truncation is the L position, and the workflow of the anti-overflow data cropper of then anti-direct current as shown in Figure 5.

At the anti-overflow data cropper of the anti-direct current of I type, m=2, n=33,1=17; At the anti-overflow data cropper of the anti-direct current of II type, m=1, n=92, l=18; At the anti-overflow data cropper of the anti-direct current of III type, m=2, n=35, l=17; At the anti-overflow data cropper of the anti-direct current of IV type, m=3, n=42,1=32.

H. export control interface

The input signal of output control interface comprises that reset signal (RESET), output mode select signal (DDC_mode), real part (I) channel clock output signal (ICLK), imaginary part (Q) channel clock output signal (QCLK), real part (I) channel data output signal I[31..0], imaginary part (Q) channel data output signal Q[31..0].Output mode selects the b0 position of signal (DDC_mode) to enable 16 DDC output modes; Output mode is selected the b1 position of signal (DDC_mode) to enable DDC and is forced output mode.

The output signal of output control interface comprises DDC output signal (IQ_Data[31/15..0]), real part (I) channel data synchronizing signal (WF1), imaginary part (Q) channel data synchronizing signal (WF2).

Output control interface protocol definition is as follows:

1) when the b0 position of DC_mode is low level, the output control interface is operated in 32 bit patterns, and the 1Q_Data bit wide is 32; When the b0 position of DDC_mode was high level, the output control interface was operated in 16 bit patterns, and the IQ_Data bit wide is 16;

2) when the b1 position of DDC_mode is high level, enable DDC and force output, WF1 and WF2 do not have synchronizing signal output during this period, forbid external unit reading the DDC data; When the b1 position of DDC_mode is low level, remove to enable DDC and force output, WF1 and WF2 have synchronizing signal output during this period, allow external unit reading the DDC data;

3) negative edge as the signal RESET that resets certainly begins, WF1 and WF2 time span be CIC extract control word * 3.275 μ s during in no synchronizing signal export, forbid external unit reading during this period to the DDC data;

4) take the real part channel data formerly, the imaginary part channel data after data output sequence;

5) when being operated in 16 bit patterns,, keep high 16 bit data of 32 real parts (I) and 32 imaginary parts (Q) respectively according to the anti-overflow data convergence of anti-direct current intercepting principle;

6) when being operated in 32 bit patterns, if the data of real part (I) passage and imaginary part (Q) passage arrive simultaneously, then export real part (I) channel data earlier, export imaginary part (Q) channel data then.If do not arrive simultaneously, then press the principle output channel data of output earlier of input earlier with a channel data;

7) the shared data bus IQ_Data of the output data of real part (I) passage and imaginary part (Q) passage.When WF1 or WF2 were low level, the data on the output data bus IQ_Data are corresponding real part (I) passage output data or imaginary part (Q) passage output data respectively.

According to above-mentioned DDC output control interface agreement, the output mode of output control interface control DDC, the control flow of output control interface is as shown in Figure 6.

The output control interface at first parses the output mode control word from command decoder, judges the b0 bit level state of output mode control word, determines whether to adopt still 16 bit data width output of 32 bit data width output.If the b0 position is a high level, then adopt the output of 16 bit data, needing that earlier 32 real part (I) channel datas of input and 32 imaginary parts (Q) channel data are carried out the anti-overflow data convergence of anti-direct current blocks, then export, go into simultaneously the principle that I goes out earlier earlier according to input earlier again, real part (I) channel data and imaginary part (Q) channel data are placed on the data bus IQ_Data, and use WF1 signal and WF2 signal Synchronization real part (I) channel data and imaginary part (Q) channel data respectively.

The output control interface is judged the b1 bit level state of output mode control word, determines whether to adopt the pressure output mode.If b1 is a high level, then enables DDC and force output.Forcing between period of output, DDC output control interface does not have the synchronizing signal WF1 and the WF2 output of real part (I) channel data and imaginary part (Q) channel data.

Export control interface at last and judge whether that reset signal RESET is effective.If the RESET signal is effective, then the RESET signal extension with a clock width is that CIC extracts control word * 3.275 μ s, and under the clock-driven situation of 40MHz, the width of RESET signal is expanded and is CIC extraction control word * 131 a clock length.In the RESET reset signal valid period of expansion, DDC output control interface does not have the synchronizing signal WF1 and the WF2 output of real part (I) channel data and imaginary part (Q) channel data.

Implementation of the present invention proposes at nuclear magnetic resonance digitizing radio frequency receiving signal, and its correctness and practicality have obtained checking in nuclear magnetic resonance imaging system.Apparatus of the present invention and method also can be applied in the modern current field, realize the downward conversion process of numeral of digital received signal.

Claims (21)

1. the magnetic nuclear resonance radio frequency receiving signal digital implement device of conversion downwards, realize based on the FPGA technology, it is characterized in that: comprise direct current offset rejector, command decoder, digital controlled oscillator, real part passage and imaginary part passage and output control interface, wherein:

The direct current offset rejector will suppress from the dc offset of the free induction decay signal of MRI RF receiving coil and the dc offset that produces in digital signal processing, and be sent to real part passage and imaginary part passage respectively;

Command decoder, reception is from the DDC control command of microprocessor, real time parsing goes out digital controlled oscillator control word, the relevant control word of CIC comb filter and DDC output control word, delivers to cic filter assembly and output control interface in digital controlled oscillator, real part passage and the imaginary part passage respectively;

Digital controlled oscillator, the digital controlled oscillator control word that goes out according to the command decoder real time parsing, from its in-phase signal output terminal and orthogonal signal output terminal identical, the quadrature in phase of output frequency, in-phase signal and the orthogonal signal represented with two's complement respectively, wherein in-phase signal is sent into the real part passage of DDC, and orthogonal signal are sent to the imaginary part passage of DDC;

Real part passage and imaginary part passage, finish the quadrature detection operation of digitized nuclear magnetic resonance free induction decay signal from the radiofrequency signal to the baseband signal, conversion operations from the High Data Rate to the low data rate, and to the inhibition of the dc offset that in digital signal processing, produces and the processing that data are overflowed;

The output control interface, the parallel data output channel by the output data of real part passage and imaginary part passage is formed realizes the data communication with follow-up digital signal processing module or data-carrier store.

2. by the implement device of the downward conversion of the described magnetic nuclear resonance radio frequency receiving signal digital of claim 1, it is characterized in that described real part passage and imaginary part passage are by quadrature detection assembly, cic filter assembly, FIR compensating filter assembly composition, wherein:

The quadrature detection assembly, comprise the anti-overflow data cropper of radio-frequency (RF) demodulator and the anti-direct current of I type, in the radio-frequency (RF) demodulator of real part passage and imaginary part passage, do the demodulation computing with homophase output signal and positive blending output signal respectively from digital controlled oscillator, obtain the demodulating data result; The anti-overflow data cropper of the anti-direct current of I type carries out anti-direct current and anti-overflow data convergence break-in operation to the result data of passage demodulation output separately;

The cic filter assembly, forms by the variable cic filter of extraction yield, CIC output adjuster, the anti-overflow data cropper of the anti-direct current of II type, CIC gain compensator, the anti-overflow data cropper of the anti-direct current of III type successively along the control flow path direction, be used for to the sampled data from the free induction decay signal of MRI RF receiving coil extract, CIC output adjustment, gain compensation and the anti-data truncation that overflows of anti-direct current operate;

FIR compensating filter assembly, overflow cropper and form by FIR compensating filter and the anti-direct current of IV type are anti-, be used to compensate the frequency characteristic that the cic filter passband curls downwards, realize that the anti-overflow data of direct current blocks, its output and the data width of output control interface are complementary.

3. the magnetic nuclear resonance radio frequency receiving signal digital implementation method of conversion downwards is characterized in that may further comprise the steps:

By the free induction decay signal of direct current offset rejector reception from the MRI RF receiving coil, command decoder receives from the DDC control of host computer by standard serial interface and imports data,

To the DDC of the above-mentioned serial control input data conversion operations that walk abreast, the concurrent control word that parses is sent into the cic filter assembly in corresponding digital controlled oscillator, real part passage and the imaginary part passage respectively and is exported control interface in command decoder;

The assigned frequency that the quadrature detection assembly transmits according to digital controlled oscillator, two mutually orthogonal local oscillation signals of phase place and frequency spectrum, to carry out the quadrature detection operation through D.C. suppressed free induction decay signal from the MRI RF receiving coil, the real part data of output and the imaginary data cic filter assembly of sending into the real part passage respectively and the cic filter assembly and the FIR compensating filter assembly of FIR compensating filter assembly and imaginary part passage are realized the sampled data from the free induction decay signal of MRI RF receiving coil is extracted, CIC exports adjustment, the CIC gain compensation, the break-in operation of FIR compensation filter and the anti-overflow data of anti-direct current;

By the output control interface real part data and imaginary data are integrated, be sent to follow-up digital signal processing module or data-carrier store.

4. by the implementation method of the downward conversion of the described magnetic nuclear resonance radio frequency receiving signal digital of claim 3, it is characterized in that: the concurrent three class control words that parse may further comprise the steps:

Definition serial communication interface agreement;

If after existing reset signal and reset operation to finish, under the CCLK clock drives, begin to intercept the level state of serial synchronous triggering signal, if high level, then begin to read serial data on the serial data bus constantly at the negative edge of thereafter first CCLK clock; According to the serial communication interface agreement, the digital controlled oscillator control word that from the serial data that serial data bus receives, parses, the relevant control word of CIC comb filter and DDC output control word, and deliver in the corresponding impact damper; According to the level state of the destination address lowest order of serial data, determining whether control word in each impact damper is loaded in the corresponding register upgrades content of registers.

5. by the implementation method of the downward conversion of the described magnetic nuclear resonance radio frequency receiving signal digital of claim 3, it is characterized in that: described direct current offset rejector suppresses to comprise from the DC component of the free induction decay signal of MRI RF receiving coil:

From the flip-flop of the simulation free induction decay signal of MRI RF receiving coil or because the non-linear flip-flop that causes of modulus switching device, the FIR High Pass Filter Cutoff Frequency satisfies following relational expression by the FIR Hi-pass filter filtering in the direct current offset rejector: $0<f_C\&le;\frac{1}{2}(f_{\mathrm{RF}}-\frac{1}{2}{\mathrm{BW}}_{\mathrm{FID}}),$ F wherein _CBe the cutoff frequency of FIR Hi-pass filter, f _RFBe the carrier frequency of nuclear magnetic resonance narrow radio frequency received signal, BW _FIDBandwidth for nuclear magnetic resonance narrow radio frequency received signal.

6. by the implementation method of the downward conversion of the described magnetic nuclear resonance radio frequency receiving signal digital of claim 3, it is characterized in that: described quadrature detection operation comprises:

Numerical value according to frequency control word, phase control words and the spectrum control word of command decoder from the digital controlled oscillator control word that the standard serial communication interface parses, the in-phase output end of digital controlled oscillator (NCO) and quadrature output terminal be the local oscillation signal of output phase quadrature respectively, and the frequency of the nuclear magnetic resonance free induction signal that its local oscillation signal frequency is all imported with system is consistent; Wherein the homophase local oscillation signal outputs to the real part passage, and orthogonal local oscillation signal outputs to the imaginary part passage;

The MRI free induction decay signal of input in the radio-frequency (RF) demodulator of real part passage and imaginary part passage, is done the demodulation computing with homophase output signal and positive blending output signal from digital controlled oscillator respectively, obtains data result;

In the anti-overflow data cropper of the anti-direct current of I type of real part passage and imaginary part passage, to the result data bit of the output of passage demodulation separately ₃₂Bit ₃₁Bit ₃₀～bit ₁Bit ₀Carry out anti-direct current and anti-overflow data convergence break-in operation.

7. by the implementation method of the downward conversion of the described magnetic nuclear resonance radio frequency receiving signal digital of claim 3, it is characterized in that: described CIC output is adjusted and is comprised:

Calculate the longest output data width B _Full

Extract control word according to reality and calculate displacement control word Shift_Factor, formula is as follows:

Shift_Factor＝(B _full-1)-ceilling(B _in-1+Nlog ₂RM)；

B wherein _InBe the input data width, R is actual extraction control word, and M is the CIC differential delay, and N is a CIC progression; Ceiling (X) is an operational symbol, if X is an integer, and Ceiling (X)=X then; If X is a decimal, then Ceiling (X) equals hithermost maximum integer;

According to displacement control word Shift_Factor to the longest output data width B of CIC _FullData are made logical shift left and are handled;

Data to CIC output adjuster output in the cic filter assembly are carried out the anti-overflow data break-in operation of the anti-direct current of II type, obtain the cic filter output data of desired data length.

8. by the implementation method of the downward conversion of the described magnetic nuclear resonance radio frequency receiving signal digital of claim 3, it is characterized in that: described CIC gain compensation comprises:

Calculated gains compensation control word, formula is as follows:

$\mathrm{Scale}\_\mathrm{Factor}=2^{\mathrm{Ceiling}\left(N\log 2^{\left(R\right)}\right)}/{\left(R\right)}^N$

Wherein Ceiling (X) is an operational symbol, if X is an integer, and Ceiling (X)=X then; If X is a decimal, then Ceiling (X) equals hithermost maximum integer, and N is a CIC progression; R is actual extraction control word;

Carry out the gain compensation multiplying, two multipliers are respectively the CIC gain compensation control word that parses from the output data of the anti-overflow data cropper of the anti-direct current of II type and command decoder;

By the anti-overflow data cropper of the anti-direct current of III type CIC gain compensation output data being carried out data truncation handles.

9. by the implementation method of the downward conversion of the described magnetic nuclear resonance radio frequency receiving signal digital of claim 3, it is characterized in that: described FIR compensation filter comprises:

The FIR wave filter adopts method for normalizing to carry out match exponents, coefficient width, input data width, output data width, receive data channel bandwidth, the setting of transitional zone bandwidth parameter, is F at the receiving cable data sampling rate wherein _SPrerequisite under, extract control word and be: the monolateral band bandwidth BW of-3dB with the corresponding relation that receives data channel bandwidth _SS=0.06875F _S/ R;

By the grand caryogenic Matlab script of operation CIC, under the condition that above-mentioned parameter is provided with, obtain the FIR compensating filter coefficient sets of corresponding maximum CIC extraction yield.

10. by the implementation method of the downward conversion of the described magnetic nuclear resonance radio frequency receiving signal digital of claim 3, it is characterized in that: the anti-data truncation operation of overflowing of described anti-direct current comprises:

Design has I type, II type and III type and the anti-overflow data cropper of the anti-direct current of IV type respectively in quadrature detection assembly, cic filter assembly and FIR compensating filter assembly, and the anti-overflow data cropper of various anti-direct current control procedure is as follows:

The anti-overflow data cropper of anti-direct current receives n bit width input data;

Whether the high m position of judging highest byte is identical, and wherein m is the sign extended figure place of highest byte;

In this way, then intercept the n-m-1 position to the data between the n-m-L position, wherein L is the data width of exporting behind the data cutout;

Judge that whether above-mentioned data are for being worth most;

As not being to be worth most, judge then whether above-mentioned data are negative;

If not negative, then judge whether to cut out data division greater than 0.5;

If then data intercept partly adds 1;

Whether step data is negative in the judgement;

If not negative, then export L bit width data;

Finish.

11. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 10 is changed downwards is characterized in that:

If when data were negative after data intercept partly added 1, these data became complement code, go to output L bit width data step.

12. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 10 is changed downwards is characterized in that:

Be not more than 0.5 if cut out data division, judge then whether cut out data division equals 0.5;

Judge then in this way whether the data intercept part is odd number;

If above-mentioned judged result is an odd number, then goes to data intercept and partly add 1 step; If above-mentioned judged result is an even number, then goes to and judge that data intercept adds partly whether 1 back data are to be the negative step;

13. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 10 is changed downwards is characterized in that:

Not that the data that are worth most are negative if be judged as, then negative data is become true form, go to judgement and whether cut out data division greater than 0.5 step.

14. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 10 is changed downwards is characterized in that:

Whether the result that is worth most when judgment data for being to judge then whether these data are positive number;

If, then export L position positive peak, go to output L bit width data step; If these data are non-positive number, then export L position negative peak, go to output L bit width data step.

15. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 10 is changed downwards is characterized in that:

Whether whether identical if judge the high m position of highest byte result for not, then going to judgement has been the positive number step for the data of value.

16. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 3 is changed downwards is characterized in that:

Described output control interface is realized by following steps:

Receive the output mode control word;

Judge which kind of bit width mode the output mode that above-mentioned control word is represented is;

If be 32 bit width modes, then receive the input data of 32 real part passages and imaginary part passage;

Whether the imaginary part channel data of judging input is prior to the real part channel data of input;

If the result is for being, two channel data common data bus then, by imaginary data preceding, real part data after order output;

Judge whether output data is to force output mode;

If, then judge whether to exist reset signal for not;

If there is not reset signal, the synchronizing signal of output data bus and real part data and imaginary data then;

Finish.

17. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 16 is changed downwards is characterized in that:

If there is reset signal, then the reset signal low level time expanded to the CIC extraction yield and multiply by time constant 3.275 μ s;

The synchronizing signal output of no real part channel data and imaginary part notice channel data between compulsory mode or reset signal low period;

Finish.

18. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 16 is changed downwards is characterized in that:

When judging that whether output data is the judged result of forcing output mode when being, go between compulsory mode or reset signal low period no real part channel data and imaginary part and notify the synchronizing signal of channel data to export step.

19. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 16 is changed downwards is characterized in that:

When the imaginary part channel data of judging input whether prior to the result of the real part channel data of input for not, two channel data common data bus then, press the real part data preceding, imaginary data after order output;

Go to and judge whether it is to force the output mode step.

20. the implementation method by the described magnetic nuclear resonance radio frequency receiving signal digital of claim 16 is changed downwards is characterized in that:

When judging that the represented output mode of above-mentioned output mode control word for the result of which kind of bit width mode is 16, then intercepts high 16 bit data of real part and imaginary part two passages;

Judge that whether above-mentioned data are for being worth most;

When above-mentioned judged result not when being worth most, the low 16 bit data convergence that is cut out is rounded on high 16 bit data of intercepting;

Go to judge input the imaginary part channel data whether prior to the real part channel data step of input.

21. the implementation method by the magnetic nuclear resonance radio frequency receiving signal digital of claim 20 is changed downwards is characterized in that:

When judging above-mentioned data when being worth most, go to imaginary part channel data the real part channel data step whether of judging input prior to importing.

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