CN201766581U - 16-way great dynamic digital receiver - Google Patents

Abstract

The utility model relates to a 16-way great dynamic digital receiver, an IF signal is directly sampled by a 16-chip AD converter to change into a digital signal firstly, a 16-way data signal is then divided into two groups to output to a first FPGA and a second FPGA, logic designs of the first and second FPGAs are completely identical, in the first FPGA, 8-way data and orthogonal local oscillation data generated by a numerical control oscillator with preplace frequency code generates an I-way signal and a Q-way signal containing baseband after two digital multipliers; the signal is performed by digital low pass filtering by a comb-shaped abstraction filter and a finite impulse response filter, after filtering, data bits of digital baseband I-way signal and Q-way signal from a 8-way receiving channel are supplied to a serial conversion unit in parallel, and then compressed into a 16-bit differential data signal by a LVDS high speed differential sender to send out, thereby, the first and second FPGAs send 32 bits differential data signal to a third FPGA together.

Description

16 tunnel big dynamic digital receivers

Technical field

The utility model relates to a kind of receiver, relates in particular to a kind of 16 tunnel big dynamic digital receivers.

Background technology

Along with developing rapidly of very high speed integrated circuit (VHIC) and very lagre scale integrated circuit (VLSIC) (VLSIC), radar, electronic warfare and communication control processor be common numbersization.The function of digital radar receiver is that the echo-signal of radar is carried out the A/D sampled digitalization, carries out quadrature demodulation and digital filtering then, then extracts (interpolation) data and passes to signal processing and carry out FFT and pulse pressure.The receiver that provides high speed high resolution, multichannel to handle is imperative.

The utility model content

Technical problem to be solved:

Provide a kind of at above problem the utility model and had that high speed high resolution, multichannel are handled, 16 tunnel big dynamic digital receivers by cpci bus control, high speed data transfer.

Technical scheme:

A kind of 16 tunnel big dynamic digital receivers comprise 16 AD converter, three FPGA, optical-electrical converter,

Intermediate-freuqncy signal is carried out Direct Sampling with 16 AD converter to it earlier makes it become digital signal, this 16 circuit-switched data signal being divided into two groups is input among first FPGA and second FPGA again, every FPGA will finish the Digital Down Convert conversion of 8 circuit-switched data signal receive paths, logical design among these two FPGA is identical, and two 8 circuit-switched data signals are input to respectively among first FPGA and second FPGA and do identical processing;

Dispose digital controlled oscillator, 16 * 16 digital multipliers, CIC pectination decimation filter, FIR finite impulse response filter and walk to serial conversion unit, LVDS high-speed-differential transmitter on first FPGA and second FPGA; The local oscillator data that the digital controlled oscillator of 8 circuit-switched data and predetermined frequency sign indicating number produces the two-way quadrature produce I road signal and the Q road signal that contains base band after through two 16 * 16 digital multipliers; I road signal and Q road signal carry out digital low-pass filtering through pectination decimation filter CIC and finite impulse response filter FIR, totally 256 of the digital baseband I road signal of 8 road receive paths that obtain after the filtering and the data of Q road signal, be positioned at and walk to the serial conversion unit, be compressed to 16 potential difference divided data signals by LVDS high-speed-differential transmitter and send, first FPGA and second FPGA send 32 potential difference divided data signals altogether and send to the 3rd FPGA and carry out high-speed data and string conversion;

The 3rd FPGA goes up configuration LVDS differential data receiver, FIFO; 32 potential difference divided data signals receive recovery through 16 LVDS differential data receivers, by 16 FIFO of a slice data-signal is sent to HSSI High-Speed Serial Interface again, serial line interface changes according to 8 finally to be exported by optical fiber after 10 bit protocols spread out of the outer optical-electrical converter of the 3rd FPGA with data-signal.

Beneficial effect:

The utility model adopts 16 AD to sample, and has realized the receiver great dynamic range, has arranged 16 AD, realizes the multipath receiver parallel processing; In FPGA, adopt CIC and FIR cascade digital filter design, compare have in the past that sideband roll-offs that performance is good, advantage little, that improve resource utilization in the sheet rises and falls in the band; Adopt Optical Fiber Transmission high speed baseband digital signal, it is compared with traditional cable transmission mode, has that bandwidth, transmission capacity are big, a good confidentiality, good, the long transmission distance of anti-electro permanent magnetic.

Description of drawings

Fig. 1 is the design frame chart of Digital Down Convert conversion of the present utility model;

Fig. 2 is the design frame chart of high-speed data serial conversion of the present utility model and opto-electronic conversion.

Embodiment

Below in conjunction with the drawings and specific embodiments the utility model is done explanation in further detail.

This 16 tunnel big dynamic digital receivers comprise 16 AD converter, three FPGA, optical-electrical converter, 16 AD converter and first FPGA, second FPGA finish the Digital Down Convert conversion, the 3rd FPGA finishes the high-speed data serial conversion, and optical-electrical converter is finished opto-electronic conversion;

After 16 road radar echo signals are reduced to intermediate-freuqncy signal through mixing, earlier with 16 AD converter (analog to digital converter) it being carried out Direct Sampling makes it become digital signal, this 16 circuit-switched data signal being divided into two groups is input among first FPGA and second FPGA again, every FPGA will finish the Digital Down Convert conversion of 8 circuit-switched data signal receive paths, logical design among these two FPGA is identical, and two 8 circuit-switched data signals are input to respectively among first FPGA and second FPGA and do identical processing (Digital Down Convert conversion).

As shown in Figure 1, dispose digital controlled oscillator, 16 * 16 digital multipliers, CIC pectination decimation filter, FIR finite impulse response filter on first FPGA (second FPGA) and walk to serial conversion unit, LVDS high-speed-differential transmitter;

The local oscillator data that the digital controlled oscillator of 8 circuit-switched data and predetermined frequency sign indicating number produces the two-way quadrature produce I road signal and the Q road signal that contains base band after through two 16 * 16 digital multipliers; I road signal and Q road signal carry out digital low-pass filtering through pectination decimation filter (CIC) and finite impulse response filter (FIR), spuious beyond filtering high order harmonic component and the passband, totally 256 of the digital baseband I road signal of 8 road receive paths that obtain after the filtering and the data of Q road signal, be positioned at and walk to the serial conversion unit, the data bit width of baseband I road signal and Q road signal is very big, for the ease of transmission, be compressed to 16 potential difference divided data signals by LVDS high-speed-differential transmitter and send, first FPGA and second FPGA send 32 potential difference divided data signals altogether and send to the 3rd FPGA and carry out high-speed data and string conversion;

As shown in Figure 2: the 3rd FPGA goes up configuration LVDS differential data receiver, FIFO;

32 potential difference divided data signals receive recovery through 16 LVDS differential data receivers, by 16 FIFO of a slice data-signal is sent to HSSI High-Speed Serial Interface again, serial line interface changes according to 8 finally to be exported by optical fiber after 10 bit protocols spread out of the outer optical-electrical converter of the 3rd FPGA with data-signal.

Though the utility model with preferred embodiment openly as above; but they are not to be used for limiting the utility model; anyly be familiar with this skill person; in the spirit and scope that do not break away from the utility model; can do various variations or retouching from working as, what therefore protection range of the present utility model should be defined with the application's claim protection range is as the criterion.

Claims (1)

1. one kind 16 tunnel big dynamic digital receiver is characterized in that: comprise 16 AD converter, three FPGA, optical-electrical converter; Dispose digital controlled oscillator, 16 * 16 digital multipliers, CIC pectination decimation filter, FIR finite impulse response filter and walk to serial conversion unit, LVDS high-speed-differential transmitter on first FPGA and second FPGA;

Intermediate-freuqncy signal is carried out Direct Sampling with 16 AD converter to it earlier makes it become digital signal, this 16 circuit-switched data signal being divided into two groups is input among first FPGA and second FPGA again, logical design among these two FPGA is identical, and the local oscillator data that the digital controlled oscillator of 8 circuit-switched data and predetermined frequency sign indicating number produces the two-way quadrature in first FPGA produce I road signal and the Q road signal that contains base band after through two 16 * 16 digital multipliers; I road signal and Q road signal carry out digital low-pass filtering through pectination decimation filter CIC and finite impulse response filter FIR, totally 256 of the digital baseband I road signal of 8 road receive paths that obtain after the filtering and the data of Q road signal, be positioned at and walk to the serial conversion unit, be compressed to 16 potential difference divided data signals by LVDS high-speed-differential transmitter and send, first FPGA and second FPGA send 32 potential difference divided data signals altogether and send to the 3rd FPGA and carry out high-speed data and string conversion;

The 3rd FPGA goes up configuration LVDS differential data receiver, FIFO; 32 potential difference divided data signals receive recovery through 16 LVDS differential data receivers, by 16 FIFO of a slice data-signal is sent to HSSI High-Speed Serial Interface again, serial line interface changes according to 8 finally to be exported by optical fiber after 10 bit protocols spread out of the outer optical-electrical converter of the 3rd FPGA with data-signal.

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