CN205507073U - Weather radar signal processing device based on FPGA - Google Patents
Weather radar signal processing device based on FPGA Download PDFInfo
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- CN205507073U CN205507073U CN201620254977.0U CN201620254977U CN205507073U CN 205507073 U CN205507073 U CN 205507073U CN 201620254977 U CN201620254977 U CN 201620254977U CN 205507073 U CN205507073 U CN 205507073U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02A—TECHNOLOGIES FOR ADAPTATION TO CLIMATE CHANGE
- Y02A90/00—Technologies having an indirect contribution to adaptation to climate change
- Y02A90/10—Information and communication technologies [ICT] supporting adaptation to climate change, e.g. for weather forecasting or climate simulation
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Abstract
The utility model discloses a weather radar signal processing device based on FPGA, including signal processing module and hardware timing and interface module, signal processing module includes that digital analog conversion module, FPGA circuit, data beat drape piece, transmission circuit and control interface, hardware timing and interface module are including the analytic module of order, timing circuit, optical coupling isolation circuit and peripheral interface circuit, the utility model relates to a weather radar signal processing device based on FPGA uses the weather radar signal processor of FPGA hardware as processing core, replace signal processor able to programme (DSP) or PC platform among traditional weather radar signal processor to accomplish functions such as weather radar signal processing algorithm and software control by FPGA hardware, the hardware design that can solve reason DSP or PC platform and bring is complicated, easily be out of order, the software debugging and the renewal of upgrading are difficult, it is miniaturized, problems such as portable.
Description
Technical field
This utility model relates to a kind of weather signal processing means, particularly relates to a kind of weather thunder based on FPGA
Reach signal processing apparatus.
Background technology
Doppler radar is one of important means of monitoring diastrous weather process at present, Aero-Space,
It is used widely in the fields such as military guarantee, meteorological disaster.Wherein radar signal processor is Doppler weather
The core component of radar, is to weigh whole Doppler Weather Radar System performance indications and the key of information retrieval
One of parts.Additionally, along with the development to meteorological disaster monitoring new demand, Doppler radar
Carrying platform, by the foundation platform of main flow, progressively develops into airborne, Space-borne.The development of new platform is by right
The performances such as the stability of weather radar signal processor, reliability are had higher requirement.
At present a kind of Doppler radar signal processor uses programmable signal processor plate (DSP), hard
The hardware such as part signal processor plate and clocked interface plate are constituted, and programmable signal processor plate is by single or multiple
Dsp processor forms, and the clutter having coordinated weather radar signal filters, compose parameter estimation and process data are defeated
Go out；Hardware signal processing plate complete radar transmitter, the generation of receiver timing signal, antenna data interface,
And various triggering, the generation of control signal.Clocked interface plate then completes radar transmitter, receiver, sky
The coupling of the interface level of line interface and circuit isolation etc..
Along with computer disposal speed and the development of bussing technique, above-mentioned based on programmable signal processor plate
(DSP) signal processor develops to the algorithm process direction of Based PC platform, i.e. by PC and data acquisition
Collection two hardware of plate replace programmable processor plate based on dsp processor；Data acquisition board completes weather thunder
Reaching echo-signal I/Q data, radar order and the transmission of state, the filtering of weather radar clutter, spectrum parameter are estimated
The transmission of meter, data is then completed by computer processor.
There is following shortcoming in above-mentioned processing method:
1, for reaching Doppler radar algorithm process requirement, programmable signal processes plate typically by multiple DSP
Processor is constituted, and adds the data storage of necessity, sequencing contro, signaling interface, Bus Interface Chip,
Making Hardware Design complicated, R&D cycle length, cost are high.Programmable signal processor is by dsp chip
Resource limit in processing speed and plate, it is impossible to meet the continuous renewal upgrading needs of algorithm；And signal processor
Chip is by producer's chip development restriction, and current dsp chip speed is relatively slow.Change whole process plate will lead
Cause the problems such as system cost, upgrade cycle, software adaptation again, therefore, it will cause HardwareUpgring
Difficult；
2, process the algorithm software of plate based on programmable signal, not only comprise algorithm process software, also include respectively
Planting bottom hardware to drive, software development difficulty is big, higher to exploitation personnel requirement.And depend on DSP process
Device type, the most a lot of producers dsp processor code cannot be compatible, mutually transplants more difficulty, causes place
After reason device change, software upgrading bothers, and difficulty is big.
3, it is too dependent on computer, when spaceborne or airborne or miniaturization or portable radar, its
Volume, power consumption etc. are required the highest, and in the case of computer cannot being used, therefore, Based PC platform
Processor then cannot use.
4, programmable signal processes in plate and the algorithm process of Based PC platform processor is realized by software, easily
By external interference, the faults such as processor deadlock, program fleet easily occur, cause whole signal processor without
Method work or misoperation, it is necessary to just can restart work by system reset.
Utility model content
The purpose of this utility model is that provides a kind of weather thunder based on FPGA to solve the problems referred to above
Reach signal processing apparatus.
This utility model is achieved through the following technical solutions above-mentioned purpose:
A kind of weather radar signal processing apparatus based on FPGA, including signal processing module and hardware timing and
Interface module:
Described signal processing module includes D/A converter module, FPGA circuitry, data packing block, transmission electricity
Road and control interface, the input of described D/A converting circuit is connected with the signal end of digital receiver, described
The outfan of D/A converting circuit is connected with the input of described FPGA circuitry, the output of described FPGA circuitry
End is connected with the input of described data packing block, and the outfan of described data packing block is by described biography
Transmission of electricity road output base data；
Described hardware timing and interface module include command analysis module, timing circuit, optical coupling isolation circuit and
Peripheral interface circuit, described command analysis module is by the signal end of described control interface Yu described FPGA circuitry
Connecting, the signal end of described command analysis module is connected with the signal end of described timing circuit, described timing electricity
Road is connected with described peripheral interface circuit by described optical coupling isolation circuit, described peripheral interface circuit respectively with
Described digital receiver, transmitter and antenna connect.
Specifically, described FPGA circuitry includes the FPGA1 chip processed for Digital Down Convert and for weather
The FPGA2 chip of Radar Signal Processing, the input of described FPGA1 chip is defeated with described digital to analog converter
Go out end to connect, the I/Q data output end of described FPGA1 chip and the data input pin of described FPGA2 chip
Connecting, the base data outfan of described FPGA2 chip is connected with the input of described data packing block.
Further, described signal processing module also includes clock circuit and data caching circuit, described clock electricity
The clock signal output terminal on road is connected with the clock signal input terminal of described D/A converting circuit, and described data are delayed
The buffered signal end of the signal end and described FPGA2 chip of depositing circuit is connected.
Specifically, described transmission circuit includes fiber-optic transfer circuit and network transmission circuit.
Specifically, described timing circuit includes receiver timing circuit, transmitter timing circuit and antennal interface
Circuit.
Preferably, described signal processing module and the timing of described hardware and interface module are arranged at by aluminium gold
Belong in the shielding box constituted.
The beneficial effects of the utility model are:
A kind of weather radar signal processing apparatus based on FPGA of this utility model is with FPGA hardware for processing core
The weather radar signal processor of the heart, is replaced compiling in tradition weather radar signal processor by FPGA hardware
Journey signal processor (DSP) or PC platform complete the function such as weather radar signal processing algorithm and software control,
Hardware designs complexity, easy break-down, software debugging and the upgrading that can solve reason DSP or PC platform and bring
Update difficulty, miniaturization, the problems such as portable so that it is have the advantage that
1, weather radar signal processing algorithm is realized with FPGA hardware, can be digital intermediate frequency and signal processor
Two hardware modules unite two into one, and compact conformation is more suitable for the field strict to volume requirement；
2, realized weather radar signal processing algorithm by FPGA hardware, do not rely on PC platform, make signal
Processor is standalone module, and condition of power supply is simple, is more suitable for the application in the fields such as portable, Aeronautics and Astronautics；
3, weather radar signal processing algorithm, relative DSP or PC processor, system are realized by FPGA hardware
Stability, reliability are higher, are difficult to the program mals such as processor deadlock, program fleet occur.
4, weather radar signal processing algorithm is realized by FPGA hardware, its HDL program code, do not rely on
Concrete FPGA producer and model, program code is transplanted, upgrading updates and is easier to.
5, being realized weather radar signal processing algorithm by FPGA hardware, its hardware designs is relatively easy, FPGA
Chip development speed is very fast, and hardware update is the most easier；
Accompanying drawing explanation
Fig. 1 is the structured flowchart of a kind of weather radar signal processing apparatus based on FPGA described in the utility model；
Fig. 2 is the workflow diagram of FPGA circuitry described in the utility model.
Detailed description of the invention
The utility model is described in further detail below in conjunction with the accompanying drawings:
As it is shown in figure 1, a kind of weather radar signal processing apparatus based on FPGA of this utility model, including letter
Number processing module and hardware timing and interface module, signal processing module and hardware timing and interface module are all provided with
Put in the shielding box being made up of aluminium metal.
Signal processing module include D/A converter module, FPGA circuitry, data packing block, transmission circuit,
Control interface, clock circuit and data caching circuit, the input of D/A converting circuit and digital receiver
Signal end connects, and the outfan of D/A converting circuit is connected with the input of FPGA circuitry, FPGA circuitry defeated
Going out end to be connected with the input of data packing block, the outfan of data packing block is exported by transmission circuit
Base data, the clock signal output terminal of clock circuit is connected with the clock signal input terminal of D/A converting circuit,
The signal end of data caching circuit is connected with the buffered signal end of FPGA2 chip, and FPGA circuitry includes for counting
The FPGA1 chip of word down-converted and the FPGA2 chip for weather radar signal processing, FPGA1 chip
Input be connected with the outfan of digital to analog converter, the I/Q data output end of FPGA1 chip and FPGA2 core
The data input pin of sheet connects, and the base data outfan of FPGA2 chip is connected with the input of data packing block,
Transmission circuit includes fiber-optic transfer circuit and network transmission circuit.
Hardware timing and interface module include command analysis module, timing circuit, optical coupling isolation circuit and periphery
Interface circuit, command analysis module is connected with the signal end of FPGA circuitry by controlling interface, command analysis mould
The signal end of block is connected with the signal end of timing circuit, and timing circuit passes through optical coupling isolation circuit and peripheral interface
Circuit connects, and peripheral interface circuit is connected with digital receiver, transmitter and antenna respectively, timing circuit bag
Include receiver timing circuit, transmitter timing circuit and antenna interface circuit.
The operation principle of a kind of weather radar signal processing apparatus based on FPGA of this utility model is as follows:
Signal processor module is by analog-digital conversion a/d circuit, clock circuit, FPGA circuitry, network transmission electricity
The main hardware circuit compositions such as road, fiber-optic transfer circuit, interface circuit, data caching circuit, power circuit.
Done shielding box by aluminium metal, SMA head, network RJ-45, optical fiber plug-in unit, DB9P, DB25S are externally provided
Plug-in unit is as signaling interface.
Hardware timing and interface module core be fpga chip, periphery connect low-voltage differential chip, 5V difference chip,
The hardware circuits such as RS232 interface, TTL, LVTTL interface and optical coupling isolation circuit.Shielded by aluminium metal
Box, externally provides DB9P, and the plug-in unit such as DB25S, DB62S is as signaling interface.
Analog to digital conversion circuit is by 16 high-performance A/D conversion chips of two-way, clock circuit when providing high-performance
Clock, wherein a road A/D chip is responsible for the analog intermediate frequency conversion to digital intermediate frequency, and is sent by 16 position digital signals
FPGA, another road is responsible for the sampling of transmitter sample signal, and transformation result also send FPGA；
FPGA circuitry is core processing circuit, including two pieces of Large Copacity fpga chips and the configuration chip of correspondence,
FPGA1 chip is responsible for Digital Down Convert algorithm process, and pulse compression algorithm is optional to be had or nothing, outside believe
Number controlling, final output I/Q data are to FPGA2 chip；FPGA2 chip is responsible at weather radar main signal
Reason algorithm process, filters including basic noise, composes parameter estimation and handling process control, base data packing etc.,
The final base data exporting certain format；Additionally FPGA2 chip is also responsible for and hardware timing and interface between
Parameter receives and sends, order control etc.；Network interface and optical fiber interface, can need to select according to user；
Network transmission main circuit is TCP/IP hardware protocol chip, it is only necessary to FPGA configures, and can complete TCP/IP
The packing of protocol package and transmission.
Hardware timing and interface module core are fpga chip, and main signal processing parameter of being responsible for receives, and launches
Machine, receiver and the reception of each state of antenna and transmission, and produce various control sequential according to parameter.
The hardware circuit such as peripheral interface and light-coupled isolation, is responsible for and transmitter, receiver and the electric level interface of antenna,
And carry out signal isolation by optocoupler, reduce interference.
The workflow of FPGA circuitry is as in figure 2 it is shown, the intermediate-freuqncy signal changed by A/D chip is directly sent to
FPGA1 chip, in FPGA1 chip, generates sinusoidal and cosine local oscillation signal according to IF signal frequency, by
Local oscillation signal carries out mixing and is converted into the output of orthogonal I/Q two-way with A/D signal, carries out anti-aliasing the most respectively
Filtering, filters the high-frequency signal after mixing, retains low frequency signal output, and wherein anti-aliasing filter comprises CIC
Filtering and Multilevel FIR filter；Then further according to signal bandwidth, signal is carried out extraction and obtains matched signal
The data transfer rate output of bandwidth.Pulse compression algorithm process is optional algoritic module, user determine as required,
Pulse compression algorithm is mainly matched filtering algorithm, and additional certain window function weights；Matched filtering coefficient is by A/D
The transmitting sample signal gathered, final FPGA1 chip output baseband I/Q data.
After I/Q data export FPGA2 chip, FPGA2 chip complete weather radar algorithm process, mainly
Filter including clutter, intensity, average speed and spectrum width calculating etc., wherein clutter filtering is main uses unlimited punching
Hitting response (IIR) elliptic filter, different according to filtering notch position, filter coefficient is different, coefficient by
Memorizer preserves, and uses and directly recalls from memorizer.After clutter filters, I/Q data one tunnel is through digital video
Integration (DVIP) processes and obtains echo strength, and range averaging determines according to distance by radar storehouse length, and according to thunder
Reaching constant and noise floor calculates reflectivity factor Z, average speed and spectrum width computational methods can be at time domain impulse pair
Between facture (PPP) and frequency domain fast Flourier facture (FFT) two kinds optional, algorithm completes into defeated
Go out average radial velocity and spectrum width, export by range bin.
The radar related data packets of data packing block includes data head and base data, and data head comprises data mark
Note symbol, antenna elevation angle, azimuth, noise level, pulse recurrence frequency, total range bin number, at signal
Reason pattern etc.；Base data is mainly reflectivity factor, average radial velocity and speed spectrum width, according to range bin
Sequencing arrangement, when being network interface output, this packet embeds in ICP/IP protocol, with standard
The packet output of ICP/IP protocol；When optical fiber interface exports, exporting without other agreements, packet is main
By beginning and the end of the data head each packet of marker character identification.
FPGA hardware is used to replace DSP or PC processor as weather radar signal processing core, it is achieved miscellaneous
The crucial weather radar signal processing algorithms such as ripple filters, spectrum process；
Existing data intermediate frequency module and signal processor module are synthesized one piece of hardware module, simple in construction,
One piece of FPGA hardware realizes Digital Down Convert algorithm and pulse compression algorithm, and another block fpga chip realizes sky
Gas radar clutter filters, composes Processing Algorithm；
Weather radar base datum (intensity, speed and spectrum width), with certain data protocol, by TCP/IP net
Network or optical fiber interface output, be suitable for the portable or field application of small size requirement；
Radar hardware timer and interface hardware module are united two into one, one piece of FPGA receives signal processor
Parameter and order control, and are responsible for producing various weather radars and control sequential, and receive various weather radar state,
Mail to signal processor module；Peripheral various interface chips are responsible for various level translation and insulation blocking.
The technical solution of the utility model is not limited to the restriction of above-mentioned specific embodiment, every new according to this practicality
The technology deformation that the technical scheme of type is made, within each falling within protection domain of the present utility model.
Claims (6)
1. a weather radar signal processing apparatus based on FPGA, it is characterised in that: include signal processing
Module and hardware timing and interface module:
Described signal processing module includes D/A converter module, FPGA circuitry, data packing block, transmission electricity
Road and control interface, the input of described D/A converting circuit is connected with the signal end of digital receiver, described
The outfan of D/A converting circuit is connected with the input of described FPGA circuitry, the output of described FPGA circuitry
End is connected with the input of described data packing block, and the outfan of described data packing block is by described biography
Transmission of electricity road output base data；
Described hardware timing and interface module include command analysis module, timing circuit, optical coupling isolation circuit and
Peripheral interface circuit, described command analysis module is by the signal end of described control interface Yu described FPGA circuitry
Connecting, the signal end of described command analysis module is connected with the signal end of described timing circuit, described timing electricity
Road is connected with described peripheral interface circuit by described optical coupling isolation circuit, described peripheral interface circuit respectively with
Described digital receiver, transmitter and antenna connect.
A kind of weather radar signal processing apparatus based on FPGA the most according to claim 1, it is special
Levy and be: described FPGA circuitry includes the FPGA1 chip processed for Digital Down Convert and for weather radar
The FPGA2 chip of signal processing, the input of described FPGA1 chip and the outfan of described digital to analog converter
Connecting, the I/Q data output end of described FPGA1 chip is connected with the data input pin of described FPGA2 chip,
The base data outfan of described FPGA2 chip is connected with the input of described data packing block.
A kind of weather radar signal processing apparatus based on FPGA the most according to claim 2, it is special
Levy and be: described signal processing module also includes clock circuit and data caching circuit, described clock circuit
Clock signal output terminal is connected with the clock signal input terminal of described D/A converting circuit, described data buffer storage electricity
The signal end on road is connected with the buffered signal end of described FPGA2 chip.
A kind of weather radar signal processing apparatus based on FPGA the most according to claim 2, it is special
Levy and be: described transmission circuit includes fiber-optic transfer circuit and network transmission circuit.
A kind of weather radar signal processing apparatus based on FPGA the most according to claim 1, it is special
Levy and be: described timing circuit includes receiver timing circuit, transmitter timing circuit and antenna interface circuit.
A kind of weather radar signal processing apparatus based on FPGA the most according to claim 1, it is special
Levy and be: described signal processing module and the timing of described hardware and interface module are arranged at by aluminium metal structure
In the shielding box become.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620254977.0U CN205507073U (en) | 2016-03-30 | 2016-03-30 | Weather radar signal processing device based on FPGA |
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| CN201620254977.0U CN205507073U (en) | 2016-03-30 | 2016-03-30 | Weather radar signal processing device based on FPGA |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106597449A (en) * | 2016-11-18 | 2017-04-26 | 陕西长岭电子科技有限责任公司 | FPGA based airborne weather radar |
| CN107132517A (en) * | 2017-05-31 | 2017-09-05 | 安徽四创电子股份有限公司 | The general Weather Channel signal processing apparatus of low-altitude surveillance radar and its processing method |
| CN107179529A (en) * | 2017-05-25 | 2017-09-19 | 成都锦江电子系统工程有限公司 | Double frequency moves back velocity ambiguity and range ambiguity method and system in a kind of arteries and veins |
| CN112558032A (en) * | 2020-11-30 | 2021-03-26 | 北京航天光华电子技术有限公司 | Digital signal processing assembly for ground warning radar |
| CN113391280A (en) * | 2021-06-15 | 2021-09-14 | 中国电子科技集团公司第二十九研究所 | Radar signal processor debugging method, device and medium based on FPGA |
-
2016
- 2016-03-30 CN CN201620254977.0U patent/CN205507073U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106597449A (en) * | 2016-11-18 | 2017-04-26 | 陕西长岭电子科技有限责任公司 | FPGA based airborne weather radar |
| CN106597449B (en) * | 2016-11-18 | 2019-06-18 | 陕西长岭电子科技有限责任公司 | Airborne weather radar based on FPGA |
| CN107179529A (en) * | 2017-05-25 | 2017-09-19 | 成都锦江电子系统工程有限公司 | Double frequency moves back velocity ambiguity and range ambiguity method and system in a kind of arteries and veins |
| CN107132517A (en) * | 2017-05-31 | 2017-09-05 | 安徽四创电子股份有限公司 | The general Weather Channel signal processing apparatus of low-altitude surveillance radar and its processing method |
| CN107132517B (en) * | 2017-05-31 | 2023-05-02 | 安徽四创电子股份有限公司 | Low-altitude monitoring radar universal weather channel signal processing device and processing method thereof |
| CN112558032A (en) * | 2020-11-30 | 2021-03-26 | 北京航天光华电子技术有限公司 | Digital signal processing assembly for ground warning radar |
| CN112558032B (en) * | 2020-11-30 | 2024-03-26 | 北京航天光华电子技术有限公司 | Digital signal processing assembly for ground warning radar |
| CN113391280A (en) * | 2021-06-15 | 2021-09-14 | 中国电子科技集团公司第二十九研究所 | Radar signal processor debugging method, device and medium based on FPGA |
| CN113391280B (en) * | 2021-06-15 | 2022-10-18 | 中国电子科技集团公司第二十九研究所 | Radar signal processor debugging method, equipment and medium based on FPGA |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160824 Termination date: 20170330 |