CN110208755B - Dynamic radar echo digital down conversion system and method based on FPGA - Google Patents
Dynamic radar echo digital down conversion system and method based on FPGA Download PDFInfo
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- CN110208755B CN110208755B CN201910512709.2A CN201910512709A CN110208755B CN 110208755 B CN110208755 B CN 110208755B CN 201910512709 A CN201910512709 A CN 201910512709A CN 110208755 B CN110208755 B CN 110208755B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/35—Details of non-pulse systems
- G01S7/352—Receivers
- G01S7/354—Extracting wanted echo-signals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
Abstract
The invention provides a dynamic radar echo digital down-conversion system and method based on an FPGA. The system comprises a band-pass filter, a dynamic bit-cutting device, an odd-even extraction device, a frequency mixing device and a low-pass filter, wherein the dynamic bit-cutting device comprises a first dynamic bit-cutting module, a second dynamic bit-cutting module and a third dynamic bit-cutting module, and whether bit-cutting operation is carried out or not is determined based on different input signals and bit widths of the maximum amplitude of the signals. By combining the dynamic truncation method, the digital down-conversion system can realize the down-conversion processing of radar echo signals with different intensities under different environments in a dynamic self-adaption mode.
Description
Technical Field
The invention relates to a radar echo digital down-conversion method, in particular to a dynamic radar echo digital down-conversion system and method based on fpga.
Background
In a conventional radar echo signal processing system, after an analog intermediate frequency real signal returned from a radio frequency front end is converted into a digital intermediate frequency real signal by an analog-to-digital conversion device, the signal is usually processed into a digital baseband complex signal by a digital down-conversion device and then input into a subsequent signal processing device. As a key step in a radar echo signal processing system, the processing performance of the digital down-conversion device directly affects the signal processing performance of the radar system.
Digital down-conversion typically consists of several steps, band-pass filtering, odd-even decimation, mixing, low-pass filtering. Due to the fixed-point operation characteristic of the FPGA, the bit width of the data can be expanded by the steps of band-pass filtering, frequency mixing and low-pass filtering with arithmetic operation. However, in order to save FPGA resources and increase the rate of signal processing, it is necessary to perform a bit truncation operation on the bit-width-extended data.
In the prior art, the truncation operation is generally performed by performing algorithm simulation or real-time testing to obtain a set of truncated values, and then writing the truncated values in a digital down-conversion module of the FPGA. First, the process is complex to operate, and the intercepted data may be located differently under different circumstances, which makes system maintenance very cumbersome. Second, the method is not adaptive to signals with too large or too small echoes, and for too large signals, the method has too few bits to intercept, resulting in data overflow. For too small a signal, the method can truncate too much, resulting in loss of valid information. Therefore, it is meaningful to design a dynamic radar echo digital down-conversion device based on the FPGA.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to design a dynamic radar echo digital down-conversion system and a dynamic radar echo digital down-conversion method based on an FPGA (field programmable gate array) to complete the digital down-conversion operation of a digital intermediate-frequency real signal. And according to the difference of echo intensities, when data truncation is needed, the truncation position can be dynamically selected, and useful information in the signal can be retained to the maximum extent.
According to an embodiment of the present invention, the present invention provides a dynamic radar echo digital down conversion system based on an FPGA, the system including:
the band-pass filter is used for filtering and sampling the received radar echo signals;
the dynamic bit cutting device is used for realizing the dynamic bit cutting of the data bit according to the intensity of the received echo signal and outputting a signal with fixed bit width and a scaling factor representing the scaling condition of each echo;
the odd-even extraction device is used for dividing the signals subjected to band-pass filtering into IQ two paths of signals according to the sampling sequence to perform signal extraction processing;
the frequency mixing device is used for respectively carrying out frequency mixing processing on the two paths of signals after the extraction processing;
and the low-pass filter is used for respectively filtering the high-frequency components in the two paths of signals subjected to frequency mixing and outputting a lower-frequency baseband signal.
Preferably, the dynamic truncation device comprises a first dynamic truncation module, a second dynamic truncation module and a third dynamic truncation module, wherein the first dynamic truncation module is used for realizing dynamic truncation of a signal after the radar echo signal is subjected to filtering sampling by a bandpass filter; and the second dynamic bit-cutting module and the third dynamic bit-cutting module respectively perform low-pass filtering on the IQ two-path signals to obtain signal dynamic bit-cutting.
Preferably, the dynamic truncation specifically includes, after receiving an echo signal, first inputting the signal into an FIFO module for caching, simultaneously calculating an amplitude maximum value in the echo signal of this time, setting a truncation policy for the echo according to the signal amplitude maximum value, then reading data from the FIFO module, performing dynamic truncation on the current echo signal according to the truncation policy, and finally outputting a truncated signal and a scaling factor.
Preferably, the bit-cutting strategy specifically includes that the relationship between the maximum value of the signal amplitude and the effective bit width is determined from the bit width corresponding to the maximum value of the signal amplitude, if the maximum value of the signal amplitude is greater than the effective bit width, the effective data bit is cut out and output as an effective signal, and meanwhile, the remaining low-bit data is discarded, otherwise, the bit-cutting operation is not performed, and the scaling factor is the bit width of the low-bit data.
Preferably, the coefficients of the band-pass filter are obtained by performing data fixed-point processing after floating-point coefficients are calculated by a fir1 function in matlab software.
Preferably, the parity extraction module is implemented based on an asymmetric I/O FIFO, and the output bit width is 2 times the input bit width.
Preferably, the frequency mixing device is configured to perform frequency mixing processing on the two extracted signals, specifically, when the I-path signal enters the frequency mixing device, the frequency mixing device generates a cosine signal, when the Q-path signal enters the frequency mixing device, the frequency mixing device generates a sine signal, and the cosine signal and the sine signal are multiplied by signals input to the frequency mixing device and then output, so as to obtain an output frequency mixing signal.
Preferably, the coefficient of the low-pass filter is obtained by performing data fixed-point processing after a floating-point type coefficient is calculated by a fir1 function in matlab software.
According to another embodiment of the present invention, the present invention further provides a dynamic radar echo digital down-conversion method based on an FPGA, including:
receiving a digital intermediate frequency real signal, and filtering and sampling the signal through a band-pass filter; separately inputting the signals subjected to band-pass filtering into IQ two signal processing branches according to a sampling sequence; mixing the IQ two paths of signals respectively; and filtering the high-frequency component of the signal subjected to the frequency mixing processing by a low-pass filter, and outputting a lower-frequency baseband signal.
Preferably, before separately inputting the band-pass filtered signals into the IQ two signal processing branches according to the sampling order, the method further includes performing dynamic bit-truncation processing on the signals filtered by the band-pass filter.
Preferably, after filtering the high-frequency component of the signal subjected to the frequency mixing processing by the low-pass filter and outputting the lower-frequency baseband signal, the method further includes performing dynamic truncation processing on the baseband signals output by the IQ two paths, and outputting the signal subjected to the dynamic truncation processing.
Preferably, the dynamic truncation processing process specifically includes, after receiving an echo signal, first inputting the signal into an FIFO module for caching, simultaneously calculating an amplitude maximum value in the echo signal of this time, setting a truncation policy for the echo according to the signal amplitude maximum value, then reading data from the FIFO module, performing dynamic truncation on the current echo signal according to the truncation policy, and finally outputting a truncated signal and a scaling factor.
Preferably, the bit-cutting strategy specifically includes that the relationship between the maximum value of the signal amplitude and the effective bit width is determined from the bit width corresponding to the maximum value of the signal amplitude, if the bit width of the maximum value of the signal amplitude is greater than the effective bit width, the effective data bit is cut out and output as an effective signal, and meanwhile, the remaining low-bit data is discarded, otherwise, the bit-cutting operation is not performed, and the scaling factor is the bit width of the low-bit data.
According to the invention, the dynamic truncation module is used for replacing the original fixed truncation module in the existing digital down-conversion process, so that the digital down-conversion device disclosed by the invention can adapt to radar echo signals under different environments.
Drawings
FIG. 1 is a block diagram of a dynamic radar echo digital down-conversion system based on FPGA according to the present invention;
FIG. 2 is a structural diagram of an asymmetric I/O bit width FIFO in the dynamic radar echo digital down-conversion system based on FPGA according to the present invention;
fig. 3 is a structural diagram of a dynamic truncating device in the dynamic radar echo digital down-conversion system based on the FPGA according to the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
An FPGA-based dynamic radar echo digital down-conversion system, as shown in fig. 1, includes a band-pass filter, a dynamic bit-cutting device, a parity extraction device, a frequency mixing device, and a low-pass filter.
The band-pass filter is used for filtering and sampling the received radar echo signals. The coefficient of the band-pass filter is obtained by calculating a floating point type coefficient through a fir1 function in matlab software and then performing data fixed-point processing. When the band-pass filter is realized in fpga, the fir ip core in the xilinx fpga development software vivado is only needed to be called and configured into a multi-item filtering structure, and then the filter coefficient obtained through data fixed-point processing is introduced. The band-pass filter based on the multi-item filtering structure completes the down-sampling function of the signal while realizing the filtering function, discards redundant sampling points in advance, improves the calculation efficiency and reduces the calculation amount of a post-stage signal processing module.
The odd-even extraction device is used for dividing the signals subjected to band-pass filtering into IQ two paths of signals according to the sampling sequence to perform signal extraction processing; the odd-even extraction device has the function of data division, and band-pass filtered data are separately input into two branches according to the odd-even sequence. The device is realized based on an FIFO with asymmetric I/O bit width, the FIFO structure is shown in figure 2, and the output bit width is 2 times of the input bit width, so that the device can complete the odd-even extraction function and simultaneously solve the problem of clock domain crossing data processing of the module.
The frequency mixing device is used for respectively carrying out frequency mixing processing on the two paths of signals after the extraction processing; as shown in fig. 1, the frequency mixing device includes a frequency mixing device 4 and a frequency mixing device 7, the frequency mixing device 4 generates a cosine signal when the I-path signal enters the frequency mixing device, and the frequency mixing device 7 generates a sine signal when the Q-path signal enters the frequency mixing device, and the cosine signal and the sine signal are multiplied by the signal input to the frequency mixing device and output, thereby obtaining an output frequency mixing signal. In the system of the present invention, the carefully chosen sampling rate allows both the cosine and sine mixing signal values to be +1 and-1, so that the mixing multiplication does not extend the data bit width.
And the low-pass filter is used for respectively filtering the high-frequency components in the two paths of signals subjected to frequency mixing and outputting a lower-frequency baseband signal. Low pass filtering is typically the last step in the down conversion to filter out the high frequency components of the mixed signal and preserve the desired baseband signal. The coefficient of the low-pass filter is obtained by calculating a floating point type coefficient through a fir1 function in matlab software and then performing data fixed-point processing. When the low-pass filter is realized in fpga, the fir ip core in the vivado of fpga development software of xilinx is called, and then the low-pass filter coefficient obtained through data fixed-point processing is imported.
In order to solve the problems in the prior art, the invention provides a dynamic bit-cutting device, which is used for realizing dynamic bit-cutting of data bits according to the strength of received echo signals and outputting signals with fixed bit width and scaling factors representing the scaling conditions of all echoes. The system is particularly applied to a dynamic truncation device in the system, and the dynamic truncation device in the system comprises a first dynamic truncation module, a second dynamic truncation module and a third dynamic truncation module, wherein the first dynamic truncation module is used for realizing the dynamic truncation of signals after radar echo signals are subjected to filtering sampling by a band-pass filter; and the second dynamic bit-cutting module and the third dynamic bit-cutting module respectively perform low-pass filtering on the IQ two-path signals to obtain signal dynamic bit-cutting. As shown in fig. 1.
The first truncation module is arranged between the band-pass filter and the odd-even extraction device, the second truncation module is arranged behind the low-pass filter of the I path signal, the third truncation module is arranged behind the low-pass filter of the Q path signal, and the function and the action of the three are the same, so that the same truncation strategy is adopted, and the specific objects of the specific truncation strategy adopted are different only aiming at different input signals. As for the dynamic truncation, after an echo signal is received, the signal is firstly input into an FIFO module for caching, and simultaneously, the amplitude maximum value in the echo signal of this time is calculated, an truncation strategy is set for the echo according to the signal amplitude maximum value, then data is read out from the FIFO module, dynamic truncation is performed on the current echo signal according to the truncation strategy, and finally, a truncated signal and a scaling factor are output. The bit interception strategy is specifically that the maximum value of the signal amplitude is corresponding to the bit width, the relation between the maximum value of the signal amplitude and the effective bit width is judged, if the maximum value of the signal amplitude is larger than the effective bit width, the effective data bit is intercepted and output as an effective signal, meanwhile, the rest low-bit data is discarded, otherwise, bit interception operation is not carried out, and the scaling factor is the bit width of the low-bit data. That is to say, the object faced by the dynamic truncation process in the first truncation module is the signal after being filtered and sampled by the band-pass filter, the object faced by the dynamic truncation process in the second truncation module is the signal after the I-path signal is low-pass filtered, the object faced by the dynamic truncation process in the third truncation module is the signal after the Q-path signal is low-pass filtered, and the specific dynamic truncation processes and strategies adopted by the three modules are the same.
As shown in fig. 3, although the three dynamic truncation modules are called at several positions in fig. 1, the implementation principles are consistent, and therefore are described herein. The dynamic bit-cutting module is realized based on fifo, firstly, the signal input into the module is input into fifo buffer memory, and meanwhile, the maximum amplitude value in the echo signal at this time is calculated. Then, the bit-cutting module sets a set of bit-cutting method for the echo according to the maximum amplitude value, reads out data from fifo, performs dynamic bit-cutting on the echo signal according to the bit-cutting method, and finally outputs the signal after bit-cutting and the scaling factor. Specifically, the bit cutting method is that a certain number of bits is reserved downwards from the maximum value of the signal amplitude corresponding to the bit width, the certain number of bits is used as effective signal output, the rest low-bit data is discarded, and the bit width of the low-bit data is the scaling factor output by the module. Taking 16 bits of the effective bit width as an example, the bit width of the maximum amplitude value of a certain echo signal is x1, and if x1 is greater than 16, the intercepted effective data bits are x1-1, x1-2, x1-3 … x 1-16. The scaling factor is x 1-16. If x1 is less than or equal to 16, the data is not truncated and the scaling factor is 0. In example 1, after band-pass filtering, if the maximum amplitude value is 100000, the effective bit width is 18 bits, the truncated effective data bits are 17, 16, 15 … 2, and the scaling factor is 2. In example 2, after band-pass filtering, if the maximum amplitude value is-10000, the effective bit width is 16 bits, no bit truncation operation is performed, and the scaling factor is 0.
Obviously, after each echo signal is reprocessed by the digital down-conversion device, a digital baseband complex signal which furthest retains effective information and a scaling factor which characterizes the signal scaling condition are obtained. Therefore, if a plurality of echoes are to be processed uniformly later, a uniform scaling factor is required so that the echo signals are scaled to the same degree. Specifically, the maximum value of the scaling factor of each echo signal is counted, and then the scaling operation is performed on the rest of the signals by taking the order as a standard. For example, after processing 4 echo signals, the scaling factors are 7, 6, 5, and 3, respectively. The maximum scaling factor is 7, then the second echo needs to be scaled down 2^ (7-6), the third echo needs to be scaled down 2^ (7-5), and the fourth echo needs to be scaled down 2^ (7-3). Since the scaling factor of each echo is determined dynamically, the final scaling factor is also determined dynamically. Therefore, the digital down-conversion device can dynamically adapt to echo signals with different intensities in different environments.
According to another embodiment of the present invention, the present invention further provides a dynamic radar echo digital down-conversion method based on an FPGA, which is characterized in that the method includes:
receiving a digital intermediate frequency real signal, and filtering and sampling the signal through a band-pass filter; separately inputting the signals subjected to band-pass filtering into IQ two signal processing branches according to a sampling sequence; mixing the IQ two paths of signals respectively; and filtering the high-frequency component of the signal subjected to the frequency mixing processing by a low-pass filter, and outputting a lower-frequency baseband signal.
Before separately inputting the signals subjected to band-pass filtering into the IQ two signal processing branches according to the sampling sequence, the method also comprises the step of carrying out dynamic bit-cutting processing on the signals subjected to band-pass filtering.
After the low-pass filter filters the high-frequency component of the signal after the frequency mixing processing and outputs the lower-frequency baseband signal, the method further comprises the steps of respectively carrying out dynamic bit-cutting processing on the baseband signals output by the IQ two paths and outputting the signal after the dynamic bit-cutting processing.
The dynamic bit-cutting processing process specifically comprises the steps of inputting a signal into an FIFO module for caching after receiving an echo signal, calculating the maximum amplitude value in the echo signal at this time, setting a bit-cutting strategy for the echo according to the maximum signal amplitude value, reading data from the FIFO module, implementing dynamic bit-cutting on the current echo signal according to the bit-cutting strategy, and finally outputting a signal after bit-cutting and a scaling factor.
The bit interception strategy is specifically that the maximum value of the signal amplitude is corresponding to the bit width, the relation between the maximum value of the signal amplitude and the effective bit width is judged, if the bit width of the maximum value of the signal amplitude is larger than the effective bit width, the effective data bit is intercepted and output as an effective signal, meanwhile, the rest low-bit data is discarded, otherwise, bit interception operation is not carried out, and the scaling factor is the bit width of the low-bit data.
The invention fully utilizes the data buffer function of fpga fifo according to the digital down-conversion principle, calculates the maximum amplitude value of each signal while buffering data, and then completes the dynamic bit-cutting of the secondary echo signal while retaining the useful signal to the maximum extent according to the specific data bit-cutting method. By combining the dynamic truncation method, the digital down-conversion system can realize the down-conversion processing of radar echo signals with different intensities under different environments in a dynamic self-adaption mode.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention and not for limiting, and although the embodiments of the present invention are described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the embodiments of the present invention without departing from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (5)
1. An FPGA-based dynamic radar echo digital down conversion system, the system comprising:
the band-pass filter is used for filtering and sampling the received radar echo signals;
the dynamic bit cutting device is used for realizing the dynamic bit cutting of the data bit according to the intensity of the received echo signal and outputting a signal with fixed bit width and a scaling factor representing the scaling condition of each echo;
the odd-even extraction device is used for dividing the signals subjected to band-pass filtering into IQ two paths of signals according to the sampling sequence to perform signal extraction processing;
the frequency mixing device is used for respectively carrying out frequency mixing processing on the two paths of signals after the extraction processing;
the low-pass filter is used for respectively filtering high-frequency components in the two paths of signals subjected to frequency mixing and outputting a lower-frequency baseband signal;
the dynamic truncation specifically comprises the steps of inputting a signal into an FIFO module for caching after receiving an echo signal, simultaneously calculating the maximum amplitude value in the echo signal at this time, setting a truncation strategy for the echo according to the maximum signal amplitude value, reading data from the FIFO module, implementing dynamic truncation on the current echo signal according to the truncation strategy, and finally outputting a truncated signal and a scaling factor;
the bit interception strategy is specifically that the maximum value of the signal amplitude is corresponding to the bit width, the relation between the maximum value of the signal amplitude and the effective bit width is judged, if the maximum value of the signal amplitude is larger than the effective bit width, the effective data bit is intercepted and output as an effective signal, meanwhile, the rest low-bit data is discarded, otherwise, bit interception operation is not carried out, and the scaling factor is the bit width of the low-bit data.
2. The FPGA-based dynamic radar echo digital down conversion system of claim 1, wherein the dynamic truncation means comprises a first dynamic truncation module, a second dynamic truncation module and a third dynamic truncation module, wherein the first dynamic truncation module is configured to implement dynamic truncation of a signal after the radar echo signal is filtered and sampled by a bandpass filter; and the second dynamic bit-cutting module and the third dynamic bit-cutting module respectively perform low-pass filtering on the IQ two-path signals to obtain signal dynamic bit-cutting.
3. The FPGA-based dynamic radar echo digital down conversion system of claim 1, wherein the frequency mixing device is configured to perform frequency mixing processing on the two extracted signals, specifically, when the I-channel signal enters the frequency mixing device, the frequency mixing device generates a cosine signal, when the Q-channel signal enters the frequency mixing device, the frequency mixing device generates a sine signal, and the cosine signal and the sine signal are multiplied by the signal input to the frequency mixing device and output, respectively, to obtain the output frequency mixed signal.
4. A dynamic radar echo digital down-conversion method based on an FPGA is characterized by comprising the following steps:
receiving a digital intermediate frequency real signal, and filtering and sampling the signal through a band-pass filter; carrying out dynamic bit-cutting processing on the signal filtered by the band-pass filter; separately inputting the signals subjected to band-pass filtering into IQ two signal processing branches according to a sampling sequence; mixing the IQ two paths of signals respectively; filtering the high-frequency component of the signal subjected to the frequency mixing processing through a low-pass filter, and outputting a lower-frequency baseband signal;
the dynamic bit-cutting processing process specifically comprises the following steps: after receiving an echo signal, firstly inputting the signal into an FIFO module for caching, simultaneously calculating the maximum amplitude value in the echo signal at this time, setting an interception strategy for the echo according to the maximum signal amplitude value, then reading out data from the FIFO module, implementing dynamic interception on the current echo signal according to the interception strategy, and finally outputting an intercepted signal and a scaling factor;
the bit interception strategy is specifically that the maximum value of the signal amplitude is corresponding to the bit width, the relation between the maximum value of the signal amplitude and the effective bit width is judged, if the bit width of the maximum value of the signal amplitude is larger than the effective bit width, the effective data bit is intercepted and output as an effective signal, meanwhile, the rest low-bit data is discarded, otherwise, bit interception operation is not carried out, and the scaling factor is the bit width of the low-bit data.
5. The FPGA-based dynamic radar echo digital down-conversion method of claim 4, wherein after filtering the high frequency component of the signal after frequency mixing processing by a low pass filter and outputting a lower frequency baseband signal, the method further comprises performing dynamic truncation processing on the baseband signals outputted by the IQ two paths respectively and outputting a signal after the dynamic truncation processing.
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