CN102971841A - 在柔性基板中组装芯片的方法 - Google Patents

在柔性基板中组装芯片的方法 Download PDF

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Publication number
CN102971841A
CN102971841A CN2011800334295A CN201180033429A CN102971841A CN 102971841 A CN102971841 A CN 102971841A CN 2011800334295 A CN2011800334295 A CN 2011800334295A CN 201180033429 A CN201180033429 A CN 201180033429A CN 102971841 A CN102971841 A CN 102971841A
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China
Prior art keywords
chip
zone
substrate
board
flexible base
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J.布鲁恩
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
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Abstract

根据本发明，提供有涂有电绝缘材料的导线（3）的基板浸灌有可聚合材料（4）。用于芯片（2）的容放区域（5）通过变形形成在基板（1）的表面上。容放区域（5）采用可聚合材料（4）硬化。芯片（2）设置在容放区域（5）中，并且芯片（2）的电连接区域（8）电连接到基板（1）的导线（3）。

Description

在柔性基板中组装芯片的方法
发明内容
本发明涉及在基板上组装电子芯片的方法。
背景技术
为了占有新的市场，电子部门已经改良了传统的电子芯片，从而使它们能经受住日益严酷的环境。然而，柔性支撑物领域仍是存在众多问题的领域。
在诸如织物的柔性基板上并入电子功能的领域中，问题主要源自于基板自身的柔性。
迄今，芯片不能直接生产在柔性基板上，而是电子芯片分开生产，然后组装在该特定的基板上。
再者，当试图连接一个或多个电子芯片到基板时，传统的组装方法因要求基板具有一定刚度和/或一定的耐热性是低效的。此外，在连接芯片到另外的装置，例如另一个芯片或无源元件时，制造起来较为复杂。
将电子芯片与提供有螺旋状导线的织物相结合的方案有很多。织物用作柔性基板，并且导线能使芯片与外部元件连接。
生产的示例描述在文件US 2004/0074660中和文件US 2006/0258205中。在这两个文件中，芯片或适配器连接到织物，这引起芯片（适配器）和织物之间不同连接处的对准问题。在文件US 2004/0074660中，一旦已经建立连接，则注入树脂，以便将织物和芯片密封起来。
已经提出通过沿着芯片的侧壁布置的横向凹槽将芯片连接到导线。该方法执行起来非常困难，并且还要求凹槽的尺寸在制作时要匹配导线的直径。
在文件WO 2005/067042中，刚性基板上形成的若干芯片放置为与包括电线的织物连接。在该实施例中，由于在组装时连接不同芯片的基板最终是刚性的，导电柔性基板的优点也就失去了。在文件JP 04290478中，通过将织物粘合到支撑板而形成刚性基板。织物包括导线以用于为发光二极管供电。但同样，由于是刚性支撑板而失去了柔性基板的优点。
发明内容
可确定存在对芯片与基板提供组装方法的需求，使该方法易于执行且能良好地控制基板和芯片之间的对准。
该需求可通过根据随附的权利要求的方法满足，特别是通过包括如下步骤的方法满足：
提供柔性基板，该柔性基板提供有至少一个导线并提供有可聚合材料，
使可聚合材料在基板的第一区域中反应，从而硬化基板的第一区域并且用以在基板的表面上形成芯片的容放区域，容放区域表示基板的更刚性的区域，
将芯片设置在容放区域中，并且将导线电连接芯片的电连接区域。
附图说明
其它的优点和特征通过下面对本发明特定实施例的描述将更加清楚易懂，本发明的实施例仅用于非限定示例的目的，且表示在所附的附图中，其中：
图1以示意性俯视图的方式示出了安装在基板上的两个芯片；
图2至4以示意性截面图的方式示出了在基板上组装芯片的方法；
图5和6以示意性截面图的方式示出了在基板上组装芯片的第二方法；
图7以示意性截面图的方式示出了组装方法的选择性实施例的一步骤；
图8和9以示意性截面图的方式示出了组装方法的另一个选择性实施例的步骤；
图10和11以示意性截面图的方式示出了组装方法的第三选择性实施例的步骤；
图12以示意性俯视图的方式示出了在基板上安装两个芯片的另一个实施例。
具体实施方式
如图1所示，需组装芯片2于其上的基板1是柔性基板，该柔性基板包括至少一个导线3。在某些实施例中，导线3全部或部分地涂有电绝缘材料。在其它实施例中，导线3不涂有电绝缘材料。
在特定实施例中，基板1包括多个导线3。导线3可包含在基板内的一个平面中，但还可想到的是将线缆3设置在若干平行的平面中。为了示例的目的，基板1包括两组线缆，表示在基板1内的两个平行平面中。
在可与前述实施例结合的选择性实施例中，基板1还包括多个非导电线。根据所用的实施例，所用的线缆为编织的或不编织的。导线可全部定向在相同的方向上。也可想到将导线设置在几个方向上，例如排列成矩阵。
为了示例的目的，基板1是织物，该织物包括编织在一起的线缆3，在该织物内具有至少一个导线。在另一个示例中，基板1包括覆盖有导线3的支撑膜。基板1还可为由电绝缘材料制作的膜，在该膜内埋入一个或多个线缆3。线缆（导电或不导电的）之间的机械固定可通过支撑膜或借助于不同线缆之间存在的不同机械连接件实现。
根据所用的实施例，导线3可包覆在电绝缘材料中，由组合件保持线缆的形状，或者导线3可在绝缘材料层中。
当导线3涂有绝缘材料且保持线缆的形状时，与其它线缆电绝缘的导线可用在编织结构中用作纬线或经线。
导线例如被电绝缘体覆盖。也可想到将覆盖有绝缘层的导线结合在自身为电绝缘的基板内。在没有绝缘体的情况下集成导线时，由基板的结构获得绝缘。
于是，容放区域5形成在基板上以容纳芯片2。用于芯片2的容放区域5表示基板1的更刚性区域。更大的刚度能使芯片更容易放置在容放区域中，由此防止基板和导线相对于芯片的变形过大。通过这种方式，容易使芯片对准基板。当芯片集成在柔性基板上时，这特别有效。
可采用不同技术来硬化基板的一部分以形成容放区域，例如通过可聚合材料4，该可聚合材料4通过反应来硬化容放区域。也可采用外部加固物来硬化基板，以防止放置芯片时基板变形过大。也可想到通过光、磁和/或电刺激以临时或永久方式改变容放区域的机械特性。
这样，如所示的，柔性基板包括刚性区域，该刚性区域相邻于柔性区域或由柔性区域围绕。两个区域呈现不同的机械性质。该特性的差异例如源自于形成刚性容放区域的材料和形成相邻的柔性基板的材料间杨氏模量的差异。容放区域的杨氏模量高于柔性基板其他区域的杨氏模量。因此，刚性区域便于芯片相对于导线的精确定位，并且柔性区域能将原基板的优点保留下来。
在特定的实施例中，容放区域5与基板的变形相关。该变形便于芯片相对于其周围物定位，例如相对于一个或多个线缆3定位。
如果基板1变形以便为电子芯片2形成容放区域5，则该容放区域5可相对于基板1的其他区域下沉或凸起。根据该实施例，下沉或凸起的容放区域5等于芯片2的面积，或者大于芯片2的面积以便于其定位或能将两个芯片并排组装起来。如果容放区域是凸起的，则容放区域也可等于比芯片更小的面积。
基板1的变形可通过任何适当的技术获得。如图2所示，通过模压两个半模具6之间的基板可实现变形。
根据半模具6中形成的图案，基板1的相对表面可呈现为具有任何形状的凸起或下沉区域。凸起或下沉的容放区域5的变形根据传统的模压技术以传统的方式实现。
根据所用的半模具，基板1呈现为下沉区域，两个下沉区域在基板的每一侧上彼此面对，或者下沉区域面对凸起区域。在图3所示的示例中，两个下沉区域彼此面对。
当基板1是柔性基板时，很难使基板保持容放区域5的预定形状。于是，有利的是采用包括可聚合材料4或任何可局部硬化基板的其它材料的基板。可聚合材料可为基板的固有成分，或者将其添加给基板，例如，通过在基板上浸灌或沉积可聚合材料。该浸灌或沉积可遍及芯片或仅局限在芯片的未来容放区域。在可聚合材料发生聚合时，聚合后材料的机械特性发生了改变以使其更加刚性。可聚合材料的转变能使基板刚硬。对于其它可采用的材料也是一样。
根据基板1的孔隙度及其与可聚合材料4的亲和性，基板1可在其化学成分及其机械强度上有局部改变。如果没有，则可聚合材料4可在柔性基板1的表面上形成刚性层以防止随后的变形。
如图3所示，一旦容放区域5形成，则对可聚合材料4进行处理以使其发生反应。于是，基板1至少在芯片2的容放区域5的位置硬化。可聚合材料4的聚合可由任何合适的技术实现，例如，通过热处理或者借助于在电磁或电子辐射下的照射。
容放区域5的硬化优选在容放区域5变形后尽快执行，以避免形状的变化。在优选方式中，在执行压靠或模压时至少部分地执行了可聚合材料4的转变，以便保持足印尽可能接近于在基板1中所需要的。
如图4所示，在特定实施例中，一旦基板1在容放区域5的位置硬化，则芯片2设置在容放区域5上。将芯片2的主表面置为与基板接触，之后将彼此固定。芯片2与基板1的固定通过任何合适的技术执行，例如，通过粘合、通过埋设芯片在其容放区域中或者通过在芯片和设置在基板的相对表面上的配合件之间的机械固定。
在图5和6所示的另一个实施例中，也可借助于芯片2直接压靠基板1。将芯片2的主表面置为与基板1的主表面接触且施加压力。然后，基板1变形为与芯片2的形状完全相同。有利的是，采用相对板7以更好地控制容放区域5的变形。该变形可为最终的或临时的。施加的压力有利地保证了基板1和芯片2之间有效的机械接触。
关于模压，其可在基板1的一个或两个表面上实现各种形式的足印。在该特定的情况下，容放区域5的变形以及芯片2的放置同时进行。在选择性实施例中，基板1由可聚合材料4或者由另外的技术至少局部硬化，以便一旦结束压靠步骤就保留住容放区域5的形状。
在其它实施例中，容放区域的硬化涉及使用相对板7。于是，不必采用可聚合材料。相对板7与基板相关，具有限定更刚性区域（容放区域5）的作用。然后，芯片设置在基板上容放区域5的位置。芯片2和相对板7由基板1分隔。
芯片2电连接到基板1。设置在芯片2的主表面上的电连接区域8与基板1的导线3电接触。芯片2的电接触区域8例如为从芯片2的主表面凸起的区域，或者相反，为该同一表面的下沉区域。电接触区域8可通过微型插入物、或通过由可熔金属材料制造的凸块或通过柱形凸块（即特定形状的块）实现。电连接也可由导电胶制作，优选为各向异性导电胶。基板1的导线3能提供芯片2与电连接到基板1的另一元件（芯片或无源元件）的供电和/或通信。
在放置芯片2到容放区域5中时，芯片施加在基板上的压力能够保证导线3和电连接区域8之间的电接触。
因此，凸起连接区域能穿透涂在导线上的绝缘材料从而至少部分地裸露出导线。在优选的方式中，从芯片的主表面凸起的电连接区域具有尖头形状和/或小于或等于30微米的直径，从而便于凸起区域8穿透至导线3。
根据另一个实施例，执行附加的化学、离子或机械的蚀刻步骤以便形成接触区域而不裸露出线缆3。
下沉连接区域，即位于芯片内部的，还可采用由相对板7导致导线变形来连接导线3。
为了获得电连接区域8和导线3之间的接触，容放区域5必须根据芯片的导线和电连接区域设置。
在图7所示的另一个实施例中，可借助于附加步骤实现直至导线的通路，该附加步骤是化学蚀刻和/或离子蚀刻和/或机械蚀刻绝缘材料，该绝缘材料面向未来的电连接区域。在所示的实施例中，直至导线3的通路穿过基板且终止在相对板7处。也可不采用相对板7，或者也可蚀刻相对板7以获得穿透式接触。
取决于所采用的蚀刻技术，导线与基板1的其余部分同时去除，然后，用连接区域8填充所产生的空白区域。电接触借助于电线的侧表面获得，并且连接区域保证了信号在电线的其余部分的连续性。在另一个选择性实施例中，导线3在去除基板1时不去除或不完全去除。涂镀导线的绝缘层大部分被去除。
芯片2可包括一个或多个附加电连接区域8（图1）。两个有效电连接区域8之间的间距是没有限制的，并且是线缆间的间距的函数。
相反，如果基板1包括若干导线3，则两个平行或基本上平行的导线3之间的距离必须与两个电连接区域8之间的距离一致。
在若干电连接区域8连接到单一导线3的情况下，导线3可在两个芯片之间或者在同一芯片的两个连接区域之间切断，以便防止任何短路（图1）。线缆通过任何适当的技术切断，例如，通过冲压或通过激光束。
在某些实施例中，相对板7仅用在基板变形步骤中，在此情况下，它不呈现在最终的装置中。在其它实施例中，它也可用作芯片2和/或基板1的机械加固物，然后，相对板7固定到电子芯片。相对板7和芯片2设置在基板1的任何一侧上。
在选择性实施例中，相对板7由机械地连接到基板1或第一芯片2的附加电子芯片2形成。在优选方式中，两个芯片2彼此电连接。该电连接可由彼此面对的具有互补形状的电连接区域8直接实现。在此情况下，对于两个芯片之间的连接不通过线缆3。该电连接也可通过一个或多个导线3实现。于是，两个芯片2之间的电连接优选设置在两个芯片2的相面对的表面中。
电子芯片2和相对板7之间的机械连接可以以任何适当的方法实现，例如，借助于粘合物或有强制结合力的结构。
在图8和9所示的且可与前述实施例结合的另一个实施例中，芯片2的容放区域5借助于相对板7，通过将相对板压在基板上而形成。基板变形，并且相对板在另一表面（即与具有相对板的表面相对的表面）上限定了凸起区域（图8）。也可想到相对板包括一个或多个凸起图案。凸起的容放区域可为任何形状。凸起的容放区域可具有与相对板相同的图案。还可想到，使相对板的凸起图案穿透基板1或在容放区域5上印出高起的图案，是为了在随后组装芯片2的位置或方位时用作防误差装置（图9）。
如图9和10所示，芯片2与相对板7的对准可用从基板1凸起的容放区域（图9）实现或者通过在基板体内的容放区域（图10）实现。相对板也可用于形成与相邻两个芯片相关的容放区域。相对板7可有益地将两个芯片2彼此间对准且相对于线缆3对准。
一旦芯片2与柔性基板的线缆3对准且固定到基板，则相对板7可通过任何适当的技术去除。相对板7也可保留。
因此，通过将带有防误差装置的相对板7对准导线3，芯片2相对于导线3的对准是自动的。防误差装置也可形成一电连接区域。
压靠相对板导致基板的变形以形成容放区域或者使一个或多个防误差装置穿透基板。
为了保证导线3和电连接区域8之间的电连接，优选执行芯片2相对于导线3的对准。该对准可在限定容放区域5时或在将芯片置于容放区域5中时执行。
在图1所示的特定实施例中，每一个都具有若干连接区域8的两个芯片2集成在基板1上。为了获得这两个芯片之间的方便且有效的通信，这两个芯片的电连接区域连接到单一导线。另一方面，为了防止不必彼此通信但连接到相同的线缆3的两个区域8之间的任何短路，导线仅仅必须进行局部蚀刻。
通过这样方式，容易在柔性基板上组装不同的芯片，且根据芯片和切割区域之间共享的线缆将它们组合以形成特定功能。
在图8至11所示的实施例中，导线3和电连接接触区8没有表示在截面图中。它们可以以类似于前面的视图的方式表示，但是所示的连接也可发生在没有示出的另外的平面中。在后者的情况下，容放区域5中呈现的变形用作防误差装置。
在图12所示的另一个实施例中，导线3设置成矩阵，即具有至少两组不同取向的线缆，优选在正交方向上。一个或多个芯片呈现多个电连接区域8。一些连接区域8与在第一方向上取向的线缆电相关，而同一芯片的其它连接区域与在第二方向上取向的线缆电相关。
根据要实现的关联性，面对芯片2的导线3可被连接或留下来空闲。同一个线缆3可连接到芯片2的若干连接区域8。如果不同的信号必须在同一线缆的不同区域中传输，则切断线缆以防止产生寄生信号。为了示例的目的，如果通过第一区域8输入到芯片的信号由相同的线缆3上的第二区域8处理后在另一个芯片的方向上重新注入，则电线缆在芯片于两个连续连接区域8之间的位置切断。
在特定实施例中，基板包括设置在两个平行的平面中的多个导线。线缆可以以任何方式设置在每个平面中。每组线缆可定向在单一方向上，这两个方向平行或不平行。也可想到每个平面具有矩阵结构的线缆3。
当芯片2电连接到基板1时，连接可在线缆3的平面之一或线缆3的两个平面实现。在特定实施例中，芯片2的电连接区域8同时连接了呈现在两个不同平面的重叠区域处的两个线缆3。
在可与前述实施例结合的另一个实施例中，芯片包括用于使两个叠置的线缆之间互连的装置。互连可借助于作用在两个叠置线缆上的压力实现，以便实现二者的电连接。互连也可借助于源自于芯片的并且直接接触两个导线3的电接触实现。
两个线缆3之间的互连可电连接到芯片2或不电连接到芯片2。
该方法在采用织物类型的基板的情况下特别有利，因为当放置芯片时，织物对变形特别敏感。容放区域的硬化能减小变形，因此控制了芯片相对于导线的对准。

Claims (14)

1.一种将电子芯片（2）组装在柔性基板（1）上的方法，其特征在于，其包括如下步骤：
提供柔性基板，该柔性基板提供有至少一个导线（3）并提供有可聚合材料（4），
使该可聚合材料（4）在该柔性基板（1）的第一区域中反应以硬化该柔性基板（1）的该第一区域且在该柔性基板（1）的表面上形成该电子芯片（2）的容放区域（5），该容放区域（5）表示该柔性基板（1）的更加刚性的区域，
将该芯片（2）设置在该容放区域（5）中，并且电连接该导线（3）与该芯片（2）的电连接区域（8）。
2.根据权利要求1所述的方法，其特征在于，其包括在形成该容放区域（5）前由该可聚合材料（4）浸灌该柔性基板（1）的步骤。
3.根据权利要求1和2之一所述的方法，其特征在于，该可聚合材料（4）是环氧树脂。
4.根据权利要求1至3任何一项所述的方法，其特征在于，其包括切割该电子芯片（2）的该电连接区域（8）和附加连接区域（8）之间的该导线（3）。
5.根据权利要求4所述的方法，其特征在于，通过冲压或激光束执行切割。
6.根据权利要求1至5任何一项所述的方法，其特征在于，硬化该基板（1）的该第一区域通过将该芯片压靠且固定到相对板（7）而获得。
7.根据权利要求1至6任何一项所述的方法，其特征在于，在该容放区域（5）硬化前，该容放区域（5）通过该柔性基板（1）的变形获得。
8.根据权利要求7所述的方法，其特征在于，通过将该芯片（2）压靠在该柔性基板（1）上而获得变形。
9.根据权利要求7和8之一所述的方法，其特征在于，通过用该相对板（7）压靠而获得变形。
10.根据权利要求6至9任何一项所述的方法，其特征在于，该相对板（7）是附加电子芯片。
11.根据权利要求1至10任何一项所述的方法，其特征在于，该电连接区域（8）从该芯片（2）的主表面凸起。
12.根据权利要求1至11任何一项所述的方法，其特征在于，该柔性基板（1）是织物。
13.根据权利要求1至12任何一项所述的方法，其特征在于，该基板（1）包括设置在两个平行平面中的多个导线（3），并且该芯片电连接到每个平面的一个导线。
14.根据权利要求13所述的方法，其特征在于，该芯片包括用于在两个叠置导线（3）上施加压力以形成互连的装置。
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JP5951602B2 (ja) 2016-07-13
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US9179586B2 (en) 2015-11-03

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