CN102884520B - 在集成电路器件中求解线性矩阵 - Google Patents
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Abstract
一种用于求解线性矩阵方程的电路,这些线性矩阵方程涉及结式矩阵、未知矩阵和乘积矩阵,该乘积矩阵是结式矩阵与未知矩阵的乘积,该电路包括:矩阵分解电路,用于三角化输入矩阵以创建结式矩阵,该结式矩阵在对角线上具有多个结式矩阵矩阵元并且具有在对角线上的结式矩阵矩阵元以下的列中布置的另外的多个结式矩阵矩阵元。矩阵分解电路包括计算结式矩阵的对角线矩阵元的平方根倒数乘法路径,该平方根倒数乘法路径具有平方根倒数模块,并且所述平方根倒数模块计算对角线矩阵元的倒数用于在取代与对角线矩阵元相除的乘法中使用。可以通过在多个矩阵的任何第(n+1)行之前对每个第n行运算来隐藏延时。
Description
技术领域
本发明涉及在集成电路器件中求解线性矩阵,并且具体地涉及在诸如可编程逻辑器件(PLD)之类的可编程集成电路器件中求解线性矩阵。
背景技术
某些线性矩阵方程可以采用形式RW=Z,其中R、W和Z中的每项是矩阵并且W包含未知数。这一问题分解成线性方程组,这些线性方程包括W的矩阵元与R的矩阵元相乘。求解W的矩阵元因此需要与R的矩阵元相除。然而对于一些矩阵(比如在LTE应用中通常发现的4×4矩阵)而言,在电路中实施除法运算可能消耗与组合的数据路径的其余部分一样多的资源。另外,经过除法器的延时可能大于经过数据路径的其余部分的延时。
发明内容
本发明涉及用于通过将前述除法转变成乘法来求解某些线性矩阵问题的简化电路。这消除对消耗资源、增加延时的除法电路的需要。可以通过一次求解多个矩阵来进一步减少延时。可以在固定逻辑器件中提供或者可以向可编程集成电路器件(诸如可编程逻辑器件(PLD))中配置该电路。
如在2008年2月25日提交、共同未决的、共同转让的第12/072,144号美国专利申请中说明的那样,可以使用Cholesky分解对矩阵因式分解(factor)、继而为前向或者后向代入来求解某些线性矩阵。Cholesky分解的结果可以是“三角化”矩阵——即在对角线上方无值的矩阵。
仅作为一个例子,以下方程序列示出利用下三角矩阵R的前向代入例子。
RW=Z
由于R是下三角矩阵,所以第一行产生一个方程一个未知数,该未知数在对角线上。求解每行将后续行简化成一个方程一个未知数,每个未知数在对角线上。因此,每次求解需要与对角线上的项相除。
在Cholesky分解中,为了对矩阵a因式分解,在合成三角化矩阵l中的每列的最高处的第一矩阵元ljj可以计算为:
其中ajj是原矩阵a的第jj个矩阵元,并且Lj是矢量,该矢量代表矩阵l的第j行上至第(j-1)列。第j列中的后续矩阵元可以计算为:
其中aij是原矩阵a的第ij个矩阵元,并且Li是矢量,该矢量代表矩阵l的第i行上至第(j-1)列的部分。
如在2009年9月11日提交、共同未决的、共同转让的第12/557,846号美国专利申请中公开的那样,如果向上述两个方程中的第二方程中代入第一方程,则结果如下:
当这一方式计算任何lij项时,如果如下数量在结构上与分子相同(虽然具有不同值):针对ljj项取得该数量的平方根,则计算分母中的ljj项中的延时对lij项计算具有很少或者无影响。分母项(在取得平方根之前)和所有后继分子项可以在分母项被锁存并且用作向第二数据路径的输入之时被填入相同数据路径中。第二数据路径将数据路径输出与锁存的值的平方根倒数相乘。并且如果计算被恰当流水线化(pipeline),则一旦填充流水线,就可以在每个时钟周期上输出新项。
即使剩余项是复数,合成下三角矩阵的对角线仍然具有所有实项ljj。因此,存在向对角线的每项分配的打算用来存储不存在的虚部的未用存储器。这一未用存储器可以用来存储对角线的每项的倒数,从而将用于求解每个未知数的上述所需除法转变成比除法消耗更少资源的乘法。另外,对角线的每项的形式是与x0.5相等的ljj=x/(x0.5),这意味着1/ljj等于在计算ljj中已经计算的x-0.5。因此,在计算或者存储1/ljj项中不使用附加的资源。
因此根据本发明,提供一种用于求解线性矩阵方程的电路,这些线性矩阵方程包括结式矩阵(resultantmatrix)、未知矩阵(unknownmatrix)和乘积矩阵,该乘积矩阵是结式矩阵与未知矩阵的乘积。该电路包括:矩阵分解电路,用于三角化输入矩阵以创建结式矩阵,该结式矩阵在对角线上具有多个结式矩阵矩阵元并且具有在对角线上的结式矩阵矩阵元以下的列中布置的更多多个结式矩阵矩阵元。矩阵分解电路包括计算结式矩阵的对角线矩阵元的平方根倒数乘法路径。用于求解线性矩阵方程的电路还包括用于分别存储结式矩阵、未知矩阵和乘积矩阵的第一矩阵存储器、第二矩阵存储器和第三矩阵存储器。平方根倒数乘法路径具有平方根倒数模块,并且所述平方根倒数模块计算对角线矩阵元的倒数。当线性矩阵方程的求解涉及与对角线矩阵元相除时,可以代之以使用与该对角线矩阵元的倒数相乘。
也提供一种配置可编程集成电路器件作为这样的电路的方法和一种这样被编程的可编程集成电路器件。此外还提供一种用机器可执行指令编码的机器可读数据存储介质,这些指令用于这样配置可编程集成电路器件。
最后提供一种操作该电路以隐藏延时的方法,其中在第一矩阵存储器和第三矩阵存储器中的相应矩阵存储器中存储结式矩阵和乘积矩阵中的至少一种矩阵的相应多个矩阵。第一矩阵存储器和第三矩阵存储器中的每个矩阵的每行具有行索引,而行索引从各个相应多个矩阵中的一个矩阵到该相应多个矩阵中的另一矩阵重复。对于每个行索引,在处理相应多个矩阵中的至少一个矩阵中的任何矩阵的具有任何其它行索引的任何行之前,处理相应多个矩阵中的该至少一个矩阵中的每个矩阵中的具有该行索引的所有行。
附图说明
将在考虑与附图结合进行的下文具体描述时清楚本发明的更多特征及其性质和各种优点,在附图中,相似标号全篇指代相似部分,并且在附图中:
图1示出了用于Cholesky分解的数据路径布置的一个实施例;
图2示出了在执行Cholesky分解时使用的电路布置的、根据本发明的一个实施例;
图3示出了用于使用后向/前向代入来求解矩阵的、可以在电路中实施的、数据路径布置的根据本发明的一个实施例;
图4是用机器可执行指令集编码的磁数据存储介质的横截面图,该指令集用于执行根据本发明的方法;
图5是用机器可执行指令集编码的光学可读数据存储介质的横截面图,该指令集用于执行根据本发明的方法;并且
图6是运用包含本发明的可编程逻辑器件的示例系统的简化框图。
具体实施方式
以维度为6×6的下三角矩阵l为例,对角线上的矩阵元是l11、…、l66。在每个第j列中,在ljj之下的矩阵元是lij,i=j+1、…、imax(在这一情况下imax=6)。矩阵可以视为在对角线上方为空,或者在对角线上方的矩阵元可以视为零。
可以使用两个数据路径来计算每个矩阵元lij。第一数据路径计算以下结果:
lx=ax-<Lx,Lx>
其中对于l和a而言,x=ij;对于L个矢量而言,x分别=i或者j;并且<Lx,Lx>表示L个矢量的内积。
在计算实际ljj的第二数据路径的输入处锁存第一数据路径的第一输出(x=jj)。列(ljj)的第一矩阵元计算为输入(ajj-<Lj,Lj>)的平方根倒数与输入相乘,从而产生输入的平方根。使用平方根倒数而不是直接计算平方根,因为可以使用比除法更易于实现的乘法将它重用于列中的后继矩阵元。
为了计算列中的所有后续值,锁存的第一数据路径输出用于平方根倒数输入,该输入是第一乘法器输入,而另一乘法器输入对于每个后续项而言是第一数据路径的对应输出。因此可以计算整列而无需等待完成任何单独的矩阵元。
图1示出了可以将矩阵值如何存储用于快速访问。每个aij值是可以在单个时钟周期中寻址的单个数,但是每个Li或者Lj行矢量是如下的j-1个数:如果所有值存储于单个存储器中,则该j-1个数将需要j-1个时钟周期来寻址。然而根据本发明的一个实施例,矩阵a可以存储于单个存储器201中,而矩阵l的每列可以存储于多个imax个单独存储器202之一中。可以同时对每个单独列存储器的第i个矩阵元寻址,从而允许在单个时钟周期内读出整个行矢量。这可以称为“按列”的存储器架构。
例如从SanJose,California的AlteraCorporation可用的可编程逻辑器件可以具有更小数目的更大存储器块(例如144kb存储器块)——可以使用其中之一作为用于存储矩阵a的存储器201——和更大数目的更小存储器块(例如9kb存储器块)——可以使用其中的imax个作为用于单独存储矩阵l的列的存储器202。当然不必将不同存储器尺寸用于存储器201、202;如果充分数目的更大存储器可用,则作为用于单独存储矩阵l的列的存储器202而使用的存储器中的任何一个或者多个存储器可以与作为用于存储矩阵a的存储器201而使用的存储器相同大小(或者甚至更大)。
因此,在单个时钟周期中,可以向存储器201施加地址输入211以在221处读出矩阵元aij用于向计算数据路径300输入,而可以向路径203上的适当j-1个存储器202施加地址输入212以读出矢量Li,并且可以向路径213上的适当j-1个存储器202施加地址输入222以读出矢量Lj。可以向结合图2更具体描述的计算路径300的输入的输出221、203、213,该计算数据路径在204处输出单独的lij值,并且也在205处向相应的第j个列存储器202中反馈每个值。
可以在固定或者可编程逻辑中实现的数据路径300包括内积数据路径301和平方根倒数数据路径302。
内积数据路径301包括内积生成器311和用于将aij与内积相减的减法器321。内积生成器311可以包括用于将imax对值同时相乘、然后将那些乘积一起相加的充分多个乘法器和加法器。对于复矢量而言,内积生成器311可以包括用于将2(imax)对值同时相乘的充分个乘法器和加法器,并且也可以包括用于在值是复数的情况下计算用于Lj的复共轭值的必需部件。Lj项在列处理开始时锁存于寄存器331中并且在下一列开始之前不变。
始于第二列,向寄存器312中锁存内积数据路径301的用于每列的第一输出——即每个ljj——作为向平方根倒数数据路径302的输入持续该列的计算持续时间。平方根倒数数据路径302包括用于计算ljj的平方根倒数的平方根倒数模块322和用于将平方根倒数与当前lij相乘的乘法器332。向寄存器312中锁存ljj将它的向乘法器332的输入延迟一个时钟周期。因此,寄存器342也延迟向乘法器332输入lij,从而延时对于两个输入而言相同。
对于第一列而言,使用简单除法来生成项。最高项l11是all -0.5,并且用于第一列的所有后续输入也与a11相除——即li1=ai1/a11 -0.5。这使用乘法器350来实现以允许aij个输入351绕过内积数据路径301。
除了如上文讨论的那样增加内积生成器311中的乘法器和加法器的数目之外,还将对其中输入是复数的数据路径300进行一些其它相对少量添加(未示出)。在这样的情况下,Li、Lj个矢量值将是复数。这将需要生成寄存器331中锁存的矢量值的复共轭。这可以通过提供用于反转每个值的虚部的符号位的逻辑来完成。在平方根倒数数据路径302中需要的改变因矩阵l的性质而简化。
如上文讨论的那样,对角线值——即在Cholesky分解中的每列的最高处的第一个值——总是实数,这意味着平方根倒数计算322将总是为实数。因此,尽管在乘法器332处的其它被乘数是复数,但是相乘将是复值与实标量值相乘,因而仅需两个乘法器——即一个附加乘法器。另外,用于每个对角线值ljj的虚部的存储器位置将未被使用,并且可用于存储1/ljj。无论何时i=j都可以在323处从平方根倒数计算322提取该值,并且该值可以在333处与乘法器332的输出一起复用用于存储取代ljj的虚部。
如上文讨论的那样,对于上文给出的RW=Z矩阵计算例子的任何给定行而言,w矩阵元计算可以描述为:
这可以改写如下:
从而将除法转变成乘法。
图3示出了根据本发明的代入数据路径/电路的一个实施例400的架构。可以按列存储R矩阵而按列提供一个存储器并且一行包含每列存储器的一个条目。可以存储多个矩阵,并且优选地一起处理多个矩阵。无需初始化W存储器402。可以向Z存储器403加载存储器401中的每个R矩阵的一个Z矢量。取而代之,一个Z矢量可以用于多个R矩阵,或者反之亦然。
可以通过将来自R列存储器401中的每个列存储器的相似编索引的矩阵元与来自存储器402的整个W矢量一起加载并且加载来自Z存储器403的具有相同行索引的单个矩阵元来加载R矩阵的行。向矢量芯404中读取的来自R行和W矩阵二者的矩阵元的数目是行索引-1(其余矩阵元可以归零)。
在复用器405从第R行的行索引矩阵元选择适当反转对角线值时,芯404的乘法器414、求和器424和减法器434计算上文针对W的每个矩阵元阐述的方程。AND门444可以用来归零当前行中未使用的列。例如,如果在每个三角化矩阵中有四行,则第一行将具有一个矩阵元、第二行将具有两个矩阵元、以此类推。如果对于行1取消列2、3、4,对于行2取消列3、4,以此类推,则不必用零初始化R存储器401的上半部,而是仅用三角化矩阵R的值初始化下半部。
优选地,先处理用于R存储器中的R矩阵中的每个矩阵的第一行索引,然后是第二行索引,然后是第三行索引,以此类推。如果在任何给定时间处理的R矩阵的数目大于数据路径和存储器延时(该延时对于图3中所示基于乘法器的计算——该计算使用来自SanJose,California的AlteraCorporation的STRATIX系列FPGA的数字信号处理块的乘法器和加法器——而言可以通常约为14个时钟周期),则一起处理所有第n行将隐藏数据路径延时。通过比较,如果使用除法器,则数据路径延时将约为30个时钟周期,从而由于需要更大数目的矩阵来隐藏数据路径延时而需要更大矩阵存储器并且造成更长处理延时。
可以从W存储器卸载W个矢量。取而代之,可以向W输出存储器(未示出)写入可以从输出406依次加载的W个值,这将在卸载时节省针对W个存储器的输出上的复用器的要求。
可以例如使用在2007年1月22日提交、共同未决的、共同转让的第11/625,655号美国专利申请中描述的技术在可编程器件中配置用于上述计算的各种算符。
本发明的一个潜在使用可以是在诸如可编程逻辑器件之类的可编程集成电路器件中,其中可以提供编程软件以允许用户配置可编程器件以执行矩阵运算。结果将是将消耗可编程器件的更少逻辑资源。并且当可编程器件具有用于算术函数的某一数目的专用块(用于免却用户必须从通用逻辑配置算术函数)时,可以减少需要提供的专用块的数目(这可以是以附加专用逻辑为代价来提供)(或者可以提供用于更多运算的充分专用块,而未进一步减少通用逻辑数量)。
用于实现根据本发明的、用于对可编程器件编程以执行矩阵分解的方法的指令可以编码于机器可读介质上,以由适当计算机或者相似设备执行以实现本发明的用于编程或者配置PLD或者其它可编程器件以执行如上文描述的加法和减法运算的方法。例如,个人计算机可以配备有PLD可以连接到的接口,并且个人计算机可以由用户用来使用适当软件工具(比如从SanJose,California的AlteraCorporation可用的QUARTUSII软件)对PLD编程。
图4呈现可以用机器可执行程序编码的磁数据存储介质800的横截面,该机器可执行程序可以由系统(比如前述个人计算机或者其它计算机或者相似设备)执行。介质800可以是具有可以是常规的适当衬底801和可以是常规的适当涂层802的软盘或者硬盘或者磁带,该涂层在一面或者两面上包含磁畴(不可见),可以机械地变更这些磁畴的极性或者定向。介质800除了在它是磁带的情况之外也可以具有用于接收盘驱动或者其它数据存储设备的主轴的开口(未示出)。
介质800的涂层802的磁畴被极性化或者定向成以可以是常规的方式对机器可读程序编码用于由具有插口或者外围附件——待编程的PLD可以插入于该插口或者外围附件中——的编程系统、比如个人计算机或者其它计算机或者相似系统执行以根据本发明配置PLD的适当部分——如果有则包括它的专门化处理块。
图5示出了也可以用这样的机器可执行程序编码的光学可读数据存储介质810的横截面,该机器可读程序可以由系统、比如前述个人计算机或者其它计算机或者相似设备执行。介质810可以是常规光盘只读存储器(CD-ROM)或者数字视频盘只读存储器(DVD-ROM)或者可重写介质、比如CD-R、CD-RW、DVD-R、DVD-RW、DVD+R、DVD+RW或者DVD-RAM或者光学地可读取和磁光学地可重写的光磁盘。介质810优选地具有可以是常规的适当衬底811和通常在衬底811的一面或者两面上的可以是常规的适当涂层812。
在基于CD或者基于DVD的介质的情况下,众所周知,涂层812有反射性并且印刻有布置于一层或者多层上用于对机器可读程序编码的多个凹点813。通过从涂层812的表面反射激光来读取凹点布置在涂层812上面提供优选地基本上透明的的保护涂层814。
在光磁盘的情况下,众所周知,涂层812无凹点813、但是具有多个磁畴,在激光(未示出)加热这些磁畴至某一温度以上时可以机械地改变这些磁畴的极性或者定向。可以通过测量从涂层812反射的激光的极化来读取域的定向。域的布置对如上文描述的程序编码。
根据本发明编程的PLD90可以使用于许多种类的电子设备中。一个可能使用是在图6中所示数据处理系统900中。数据处理系统900可以包括以下部件中的一个或者多个部件:处理器901;存储器902;I/O电路903;以及外围设备904。这些部件由系统总线905耦合在一起并且填充于终端用户系统907中的电路板906上。
系统900可以使用于广泛多种应用、比如计算机联网、数据联网、仪器使用、视频处理、数字信号处理或者任何其它如下应用中,在这些应用中希望有使用可编程或者可重编程逻辑的优点。PLD90可以用来执行多种不同逻辑功能。例如PLD90可以配置为与处理器901配合工作的处理器或者控制器。PLD90也可用作仲裁器,该仲裁器用于仲裁对系统900中的共享资源的访问。在又一例子中,PLD90可以配置为在处理器901与系统900中的其它部件之一的接口。应当注意系统900仅为示例并且本发明的真实精神实质和范围应当由所附权利要求指示。
各种技术可以用来实施如上文描述的并且结合本发明的PLD90。
将理解前文仅举例说明本发明的原理并且本领域技术人员可以进行各种修改而未脱离本发明的范围和精神实质。例如可以按照任何所需数目和/或布置在PLD上提供本发明的各种单元。本领域技术人员将理解除了出于示例而非限制的目的来呈现的描述的实施例之外的实施例可以实现本发明,并且本发明仅由所附权利要求限制。
Claims (10)
1.一种用于求解线性矩阵方程的电路,所述线性矩阵方程涉及结式矩阵、未知矩阵和乘积矩阵,所述乘积矩阵是所述结式矩阵与所述未知矩阵的乘积,所述电路包括:
矩阵分解电路,用于三角化输入矩阵以创建结式矩阵,所述结式矩阵在对角线上具有多个结式矩阵矩阵元并且具有在所述对角线上的所述结式矩阵矩阵元以下的列中布置的另外的多个结式矩阵矩阵元,所述矩阵分解电路包括计算所述结式矩阵的对角线矩阵元的平方根倒数乘法路径;以及
第一矩阵存储器、第二矩阵存储器和第三矩阵存储器,用于分别存储所述结式矩阵、所述未知矩阵和所述乘积矩阵;其中:
所述平方根倒数乘法路径包括平方根倒数模块;
所述平方根倒数模块计算所述对角线矩阵元的倒数;
所述第一矩阵存储器将所述结式矩阵的每个矩阵元存储为实部和虚部;
每个所述对角线矩阵元仅有实部;并且
存储所述对角线矩阵元的所述倒数中的相应倒数以取代所述对角线矩阵元中的相应对角线矩阵元的不存在的虚部。
2.根据权利要求1所述的电路,还包括:
乘法器和求和电路,用于形成所述结式矩阵和所述未知矩阵的对应行的内积;
减法器,用于分别将所述乘积矩阵的相应矩阵元与所述内积相减以产生相应差值;以及
另外的乘法器,用于将每个相应差值与所述对角线矩阵元的所述倒数中的相应倒数相乘以确定所述未知矩阵的相应矩阵元。
3.一种操作用于求解线性矩阵方程的电路的方法,所述线性矩阵方程涉及结式矩阵、未知矩阵和乘积矩阵,所述乘积矩阵是所述结式矩阵与所述未知矩阵的乘积,所述电路包括:矩阵分解电路,用于三角化输入矩阵以创建结式矩阵,所述结式矩阵在对角线上具有多个结式矩阵矩阵元并且具有在所述对角线上的所述结式矩阵矩阵元以下的列中布置的另外的多个结式矩阵矩阵元,所述矩阵分解电路包括计算所述结式矩阵的对角线矩阵元的平方根倒数乘法路径,所述电路还包括:第一矩阵存储器、第二矩阵存储器和第三矩阵存储器,用于分别存储所述结式矩阵、所述未知矩阵和所述乘积矩阵;其中所述平方根倒数乘法路径包括平方根倒数模块,并且所述平方根倒数模块计算所述对角线矩阵元的倒数;所述方法包括:
在所述第一矩阵存储器和所述第三矩阵存储器中的相应矩阵存储器中存储所述结式矩阵和所述乘积矩阵中的至少一种矩阵的相应多个矩阵,所述第一矩阵存储器和所述第三矩阵存储器中的每个矩阵的每行具有行索引,其中行索引从各个相应多个矩阵中的一个矩阵到所述相应多个矩阵中的另一矩阵重复;并且
对于每个行索引,在处理所述相应多个矩阵中的至少一个矩阵中的任何矩阵的具有任何其它行索引的任何行之前,处理所述相应多个矩阵中的所述至少一个矩阵中的每个矩阵中的具有所述行索引的所有行。
4.根据权利要求3所述的方法,其中:
每个所述对角线矩阵元仅有实部;
所述方法还包括
配置所述第一矩阵存储器以将所述结式矩阵的每个矩阵元存储为实部和虚部;并且
存储所述对角线矩阵元的所述倒数中的相应倒数以取代所述对角线矩阵元中的相应对角线矩阵元的不存在的虚部。
5.一种配置可编程集成电路器件作为用于求解线性矩阵方程的电路的方法,所述线性矩阵方程涉及结式矩阵、未知矩阵和乘积矩阵,所述乘积矩阵是所述结式矩阵与所述未知矩阵的乘积,所述方法包括:
配置所述可编程集成电路器件的逻辑作为矩阵分解电路,所述矩阵分解电路用于三角化输入矩阵以创建结式矩阵,所述结式矩阵在对角线上具有多个结式矩阵矩阵元并且具有在所述对角线上的所述结式矩阵矩阵元以下的列中布置的另外的多个结式矩阵矩阵元,包括配置所述可编程集成电路器件的逻辑作为计算所述结式矩阵的对角线矩阵元的平方根倒数乘法路径;并且
配置所述可编程集成电路器件的存储器作为用于分别存储所述结式矩阵、所述未知矩阵和所述乘积矩阵的第一矩阵存储器、第二矩阵存储器和第三矩阵存储器;其中:
所述平方根倒数乘法路径包括平方根倒数模块;
所述平方根倒数模块计算所述对角线矩阵元的倒数;
每个所述对角线矩阵元仅有实部;
所述方法还包括
配置所述第一矩阵存储器以将所述结式矩阵的每个矩阵元存储为实部和虚部;并且
存储所述对角线矩阵元的所述倒数中的相应倒数以取代所述对角线矩阵元中的相应对角线矩阵元的不存在的虚部。
6.根据权利要求5所述的方法,还包括:
配置所述可编程集成电路器件的逻辑作为乘法器和求和电路,所述乘法器和求和电路用于形成所述结式矩阵和所述未知矩阵的对应行的内积;
配置所述可编程集成电路器件的逻辑作为用于分别将所述乘积矩阵的相应矩阵元与所述内积相减以产生相应差值的减法器;并且
配置所述可编程集成电路器件的逻辑作为用于将每个相应差值与所述对角线矩阵元的所述倒数中的相应倒数相乘以确定所述未知矩阵的相应矩阵元的另外的乘法器。
7.一种配置为用于求解线性矩阵方程的电路的可编程集成电路器件,所述线性矩阵方程涉及结式矩阵、未知矩阵和乘积矩阵,所述乘积矩阵是所述结式矩阵与所述未知矩阵的乘积,所述可编程集成电路器件包括:
配置为矩阵分解电路的逻辑,所述矩阵分解电路用于三角化输入矩阵以创建结式矩阵,所述结式矩阵在对角线上具有多个结式矩阵矩阵元并且具有在所述对角线上的所述结式矩阵矩阵元以下的列中布置的另外的多个结式矩阵矩阵元,包括配置为平方根倒数乘法路径的逻辑,所述平方根倒数乘法路径计算所述结式矩阵的对角线矩阵元;并且
配置为第一矩阵存储器、第二矩阵存储器和第三矩阵存储器的逻辑,所述第一矩阵存储器、所述第二矩阵存储器和所述第三矩阵存储器用于分别存储所述结式矩阵、所述未知矩阵和所述乘积矩阵;其中:
所述平方根倒数乘法路径包括平方根倒数模块;
所述平方根倒数模块计算所述对角线矩阵元的倒数;
每个所述对角线矩阵元仅有实部;
所述第一矩阵存储器被配置成将所述结式矩阵的每个矩阵元存储为实部和虚部;并且
存储所述对角线矩阵元的所述倒数中的相应倒数以取代所述对角线矩阵元中的相应对角线矩阵元的不存在的虚部。
8.根据权利要求7所述的配置为用于求解线性矩阵方程的电路的可编程集成电路器件,还包括:
配置为乘法器和求和电路的逻辑,所述乘法器和求和电路用于形成所述结式矩阵和所述未知矩阵的对应行的内积;
配置为减法器的逻辑,所述减法器用于分别将所述乘积矩阵的相应矩阵元与所述内积相减以产生相应差值;以及
配置为另外的乘法器的逻辑,所述另外的乘法器用于将每个相应差值与所述对角线矩阵元的所述倒数中的相应倒数相乘以确定所述未知矩阵的相应矩阵元。
9.一种用于配置可编程集成电路器件作为用于求解线性矩阵方程的电路的设备,所述线性矩阵方程涉及结式矩阵、未知矩阵和乘积矩阵,所述乘积矩阵是所述结式矩阵与所述未知矩阵的乘积,所述设备包括:
用于配置所述可编程集成电路器件的逻辑作为矩阵分解电路的装置,所述矩阵分解电路用于三角化输入矩阵以创建结式矩阵,所述结式矩阵在对角线上具有多个结式矩阵矩阵元并且具有在所述对角线上的所述结式矩阵矩阵元以下的列中布置的另外的多个结式矩阵矩阵元,包括用于配置所述可编程集成电路器件的逻辑作为平方根倒数乘法路径的装置,所述平方根倒数乘法路径计算所述结式矩阵的对角线矩阵元;并且
用于配置所述可编程集成电路器件的存储器作为用于分别存储所述结式矩阵、所述未知矩阵和所述乘积矩阵的第一矩阵存储器、第二矩阵存储器和第三矩阵存储器的装置;其中:
所述平方根倒数乘法路径包括平方根倒数模块;
所述平方根倒数模块计算所述对角线矩阵元的倒数;
每个所述对角线矩阵元仅有实部;
所述用于配置所述可编程集成电路器件的存储器的装置包括用于配置所述第一矩阵存储器以将所述结式矩阵的每个矩阵元存储为实部和虚部的装置;并且
存储所述对角线矩阵元的所述倒数中的相应倒数以取代所述对角线矩阵元中的相应对角线矩阵元的不存在的虚部。
10.根据权利要求9所述的设备,其中所述设备还包括:
用于配置所述可编程集成电路器件的逻辑作为乘法器和求和电路的装置,所述乘法器和求和电路用于形成所述结式矩阵和所述未知矩阵的对应行的内积;
用于配置所述可编程集成电路器件的逻辑作为用于分别将所述乘积矩阵的相应矩阵元与所述内积相减以产生相应差值的减法器的装置;以及
用于配置所述可编程集成电路器件的逻辑作为用于将每个相应差值与所述对角线矩阵元的所述倒数中的相应倒数相乘以确定所述未知矩阵的相应矩阵元的另外的乘法器的装置。
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EP2550604A2 (en) | 2013-01-30 |
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US8539014B2 (en) | 2013-09-17 |
CN102884520A (zh) | 2013-01-16 |
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