CN102881656A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN102881656A
CN102881656A CN2011101976760A CN201110197676A CN102881656A CN 102881656 A CN102881656 A CN 102881656A CN 2011101976760 A CN2011101976760 A CN 2011101976760A CN 201110197676 A CN201110197676 A CN 201110197676A CN 102881656 A CN102881656 A CN 102881656A
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depression
semiconductor device
decrystallized layer
sigma shape
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CN102881656B (zh
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何永根
吴兵
刘焕新
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Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明公开一种半导体器件及其制造方法，涉及半导体工艺技术领域。该方法包括：在衬底中形成凹陷；对凹陷底部进行注入以在凹陷底部下方预定深度形成非晶化层；以非晶化层作为对于湿法刻蚀的阻挡层对凹陷进行晶向选择性湿法刻蚀从而形成Sigma形凹陷。通过注入形成非晶化层作为后面湿法刻蚀的阻挡层，避免了形成具有尖的底部的Sigma凹陷，从而形成满足条件的Sigma凹陷，进一步提高半导体器件的性能。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体工艺技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
在先进CMOS技术中，提出嵌入式硅锗(Embedded SiGe，eSiGe)工艺，以增大PMOS器件沟道区的压缩应力，增强其载流子迁移率；其中使用嵌入式硅锗来形成源区或漏区，从而对沟道区施加应力。进一步提出了形成Sigma(“∑”)(或称为钻石(diamond))形凹陷以填充硅锗的技术方案，增强施加应力的效果，提高PMOS器件性能。
图1A至图1C示意性地示出现有技术中形成Sigma形凹陷的工艺各个阶段的截面图。
如图1A所示，提供形成有栅极的衬底，可以选择衬底的表面的晶面方向为(100)。
如图1B所示，例如通过干法蚀刻在衬底中形成“U”形凹陷(通过A、B、C、D点确定该凹陷)；“U”形凹陷底部的晶面方向也是(100)，“U”形凹陷侧壁的晶面方向可以是(110)。在随后的湿法蚀刻过程中，在<111>晶向上的蚀刻速度小于在其它晶向上的蚀刻速度。
如图1C所示，采用具有晶向选择性的湿法蚀刻剂，例如包含四甲基氢氧化铵(TMAH)的蚀刻剂，通过“U”形凹陷对衬底进行蚀刻以形成Sigma形凹陷。
然而，由于在<100>晶向和<110>晶向上的蚀刻速度比在<111>晶向上的蚀刻速度大，所以凹陷底部很容易被过度蚀刻，从而使得凹陷两侧侧壁的下半部分相交。于是，该各向异性蚀刻的结果往往导致凹陷的底部是尖的，而不是平的。图2示出现有技术中形成的Sigma形凹陷的图片。
此外，对于目前在干法刻蚀后进行后湿法刻蚀的实践，湿法刻蚀导致在不同CD区域上严重的微负载效应(micro loading effect)。
发明内容
鉴于以上问题，本发明的一个目的是提供一种半导体器件的制造方法，能够避免形成的Sigma形凹陷具有尖的底部。
根据本发明的第一方面，提供了一种半导体器件制造方法，包括：在衬底中形成凹陷；对凹陷底部进行注入以在凹陷底部下方预定深度形成非晶化层；以非晶化层作为阻挡层对凹陷进行晶向选择性湿法刻蚀从而形成Sigma形凹陷。
优选地，采用Ge、Si、BF2、C、Xe、或者Sb进行所述注入。
优选地，注入的能量为3～10KeV，剂量(Dosage)为5×1013～5×1015原子/平方厘米，注入倾斜角度(Implant Tilt Angle)为0～5度。
优选地，该方法还包括：在Sigma形凹陷内生长SiGe或SiGe:B(原位掺杂B的SiGe)。
优选地，该方法在Sigma形凹陷内生长SiGe或SiGe:B前包括：对非晶化层进行热处理工艺用于SiGe或SiGe:B外延生长。其中，对非晶化层进行热处理工艺包括：通过尖峰退火(Spike Anneal)对非晶化层进行修复；或者通过固相外延再生长(Solid Phase EpitaxyRegrowth，SPER)对非晶化层进行修复；或者通过MSA(long pulseFLA or longer dwell time LSA)对非晶化层进行修复。优选地，尖峰退火的温度为900～1100℃。
优选地，半导体衬底上形成有栅极，生长有SiGe或SiGe:B的所述Sigma形凹陷被用作源/漏区。
优选地，所述在衬底表面形成凹陷包括：通过干法刻蚀在衬底表面形成凹陷。
根据本发明的第二方面，提供了一种半导体器件，其中，半导体器件的衬底表面形成有Sigma形凹陷，所述Sigma形凹陷的底面为非晶化层。
优选地，非晶化层的材料包括Ge、Si、BF2、C、Xe、或者Sb。
优选地，Sigma形凹陷中生长有SiGe或SiGe:B。
优选地，半导体器件的半导体衬底上形成有栅极，生长有SiGe或SiGe:B的所述Sigma形凹陷被用作源/漏区。
根据本发明的半导体器件的制造方法，通过注入形成非晶化层，作为后面湿法刻蚀的阻挡层，避免了形成的Sigma凹陷具有尖的底部。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1A至图1C示意性地示出现有技术中形成Sigma形凹陷的工艺各个阶段的截面图。
图2示出现有技术中形成的Sigma形凹陷的图片。
图3示出根据本发明的半导体器件制造方法的一个实施例的流程图。
图4A至图4D示意性地示出根据本发明的半导体器件制造方法的一个实施例的各个阶段的截面图。
图5A至图5F示意性地示出根据本发明的半导体器件制造方法的另一个实施例的各个阶段的截面图。
图6示出包括Sigma形凹陷的半导体器件的照片。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
下面参考图3所示的工艺流程图以及图4A至4D所示出的各个阶段的截面图，描述根据本发明的制造半导体器件的方法。
图3示出根据本发明的半导体器件制造方法的一个实施例的流程图。
如图3所示，在步骤S302，例如通过干法刻蚀在衬底中形成凹陷。
衬底表面的晶面方向可以是(100)。例如，如图4A所示，在衬底400上形成“U”形凹陷410。衬底400的材料例如是硅(Si)，可以通过公知的干法蚀刻工艺来形成“U”形凹陷410。
在步骤S304，对凹陷底部进行注入以在凹陷底部下方预定深度形成非晶化层。非晶化层通常是从凹陷底部的表面到一定的深度。
本领域的技术人员可以根据源漏区的设计来确定非晶化层的深度，通过控制注入的条件可以控制形成的非晶化层的深度。注入的杂质例如为Ge、Si、BF2、C、Xe、或者Sb。如图4B所示，在凹陷410的底部进行例如预非晶化注入(Pre-amorphous implantation，PAI)，从而在凹陷410底部下方预定深度形成非晶化层420。
在步骤S306，以非晶化层作为阻挡层对凹陷进行晶向选择性湿法刻蚀，非晶化层作为对于湿法刻蚀的阻挡层，从而形成Sigma形凹陷。
可以采用本领域常用的具有晶向选择性的湿法蚀刻。如图4C所示，凹陷410经过晶向选择性湿法刻蚀后，在半导体衬底400上形成Sigma形凹陷，Sigma形凹陷的底面为非晶化层420，非晶化层可以包括Ge、Si、BF2、C、Xe、或者Sb。由于非晶化层作为湿法刻蚀的阻挡层，避免了Sigma凹陷形成尖的底部。
上述实施例中，通过注入形成非晶化层，作为后面湿法刻蚀的阻挡层，能够形成底部平坦的Sigma凹陷，避免了形成具有尖的底部的Sigma凹陷，从而形成的Sigma凹陷满足对器件的性能要求，进一步提高半导体器件的性能。
根据本发明半导体器件制造方法的一个实施例，对凹陷底部进行注入以形成非晶化层采用如下条件：注入的能量为3～10KeV，剂量(dosage)为5×1013～5×1015原子/平方厘米，注入倾斜角度(implant tilt angle)为0～5度。通过控制杂质注入的条件，可以控制形成的非晶化层的深度以及分布情况。
根据本发明半导体器件制造方法的一个实施例，在形成Sigma形凹陷后，在Sigma形凹陷内生长SiGe或SiGe:B。例如，通过外延生长从Sigma形凹陷410的底部生长硅锗(SiGe)或者掺杂B的SiGe(SiGe:B)。图4D示出凹陷410内生长有SiGe或SiGe:B 470的图示。生长有SiGe的Sigma形凹陷可以作为半导体器件PMOS的源/漏区。
可选地，在Sigma形凹陷内生长SiGe或SiGe:B前对非晶化层进行进行热处理工艺，使得非晶化层再结晶成单晶Si衬底，便于随后的SiGe或SiGe:B外延生长。例如，可以通过尖峰退火(SpikeAnneal)对非晶化层进行修复，尖峰退火的温度例如为900～1100℃；或者可以通过固相外延再生长(solid phase epitaxy regrowth，SPER)对非晶化层进行修复；或者可以通过MSA(long pulse FLAor longer dwell time LSA)对非晶化层进行修复。通过对非晶化层采用热处理工艺进行修复，可以更好地在非晶化层上生长SiGe或者SiGe:B。
半导体器件中往往既有NMOS器件，也有PMOS器件。在CMOS器件中尤其如此。
使用嵌入式硅锗形成的源区或漏区往往用于PMOS器件。因此，在执行下面描述的各个步骤之前，可以用掩模遮蔽要形成NMOS器件的部分，而暴露要形成PMOS器件的部分，从而只在要形成PMOS器件的部分中形成凹陷，并填充嵌入式硅锗。
下面参考图5A至图5F介绍根据本发明的半导体器件制造方法的另一个实施例。
如图5A所示，在半导体衬底400上形成栅极440。在栅极440的两侧可以形成间隔物。
如图5B所示，通过干法刻蚀在半导体衬底400的PMOS区域形成凹陷410。该凹陷410通常为“U”形凹陷。
如图5C所示，在凹陷410的底部进行预非晶化注入，从而在半导体衬底400中在凹陷410底部下方的预定深度处形成非晶化层420。注入的杂质例如是P型杂质Ge、Si、或BF2。
如图5D所示，对凹陷410进行晶向选择性湿法刻蚀到非晶化层420，非晶化层420作为对于湿法刻蚀的阻挡层，从而形成Sigma形凹陷410。
如图5E所示，对凹陷410底部的非晶化层420通过尖峰退火进行修复，，以便非晶化层420再结晶成单晶Si衬底，便于进一步的SiGe或者SiGe:B外延生长。
如图5F所示，在Sigma形凹陷中外延生长SiGe或者SiGe:B，作为PMOS的源/漏区。
上述实施例中，通过各个工艺步骤在PMOS区域形成满足条件的Sigma形凹陷，并且消除了微负载效应；外沿生长有SiGe或者SiGe:B后作为PMOS的源/漏区，增大PMOS器件沟道区的压缩应力，增强其载流子迁移率，提高半导体器件的性能。
图6示出包括Sigma形凹陷的半导体器件的照片。在Sigma形凹陷410的底部为非晶化层420，Sigma形凹陷410中可以进行SiGe或者SiGe:B外延生长。
至此，已经详细描述了根据本发明的制造半导体器件的方法和所形成的半导体器件。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
可能以许多方式来实现本发明的方法和半导体器件。用于所述方法的步骤的上述顺序仅是为了进行说明，本发明的方法的步骤不限于以上具体描述的顺序，除非以其它方式特别说明。
本发明的描述是为了示例和描述起见而给出的，而并不是无遗漏的或者将本发明限于所公开的形式。很多修改和变化对于本领域的普通技术人员而言是显然的。选择和描述实施例是为了更好说明本发明的原理和实际应用，并且使本领域的普通技术人员能够理解本发明从而设计适于特定用途的带有各种修改的各种实施例。

Claims (13)

1.一种半导体器件制造方法，其特征在于，包括：
在衬底中形成凹陷；
对所述凹陷底部进行注入以在所述凹陷底部下方预定深度形成非晶化层；
以所述非晶化层作为阻挡层对所述凹陷进行晶向选择性湿法刻蚀从而形成Sigma形凹陷。
2.根据权利要求1所述的方法，其特征在于，采用Ge、Si、BF2、C、Xe、或者Sb进行所述注入。
3.根据权利要求1所述的方法，其特征在于，所述注入的能量为3～10KeV，剂量为5×1013～～5×1015原子/平方厘米，注入倾斜角度为0～5度。
4.根据权利要求1所述的方法，其特征在于，还包括：
在所述Sigma形凹陷内生长SiGe或原位掺杂B的SiGe。
5.根据权利要求4所述的方法，其特征在于，在所述Sigma形凹陷内生长SiGe或原位掺杂B的SiGe前包括：
对所述非晶化层进行热处理工艺以便SiGe或原位掺杂B的SiGe外延生长。
6.根据权利要求5所述的方法，其特征在于，对所述非晶化层进行热处理包括：
通过尖峰退火对所述非晶化层进行修复；
或者
通过固相外延再生长对所述非晶化层进行修复；
或者
通过MSA对所述非晶化层进行修复。
7.根据权利要求6所述的方法，其特征在于，所述尖峰退火的温度为900～1100℃。
8.根据权利要求4所述的方法，其特征在于，所述半导体衬底上形成有栅极；
生长有SiGe或原位掺杂B的SiGe的所述Sigma形凹陷被用作源/漏区。
9.根据权利要求1所述的方法，其特征在于，所述在衬底表面形成凹陷包括：
通过干法刻蚀在衬底表面形成凹陷。
10.一种半导体器件，其中，所述半导体器件的衬底表面形成有Sigma形凹陷，所述Sigma形凹陷的底面为非晶化层。
11.根据权利要求10所述的半导体器件，其特征在于，所述非晶化层的材料包括Ge、Si、BF2、C、Xe、或者Sb。
12.根据权利要求10所述的半导体器件，其特征在于，所述Sigma形凹陷中生长有SiGe或原位掺杂B的SiGe。
13.根据权利要求12所述的半导体器件，其特征在于，所述半导体衬底上形成有栅极，生长有SiGe或原位掺杂B的SiGe的所述Sigma形凹陷被用作源/漏区。
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