CN102859681B - 用于形成集成半导体结构的方法和结构 - Google Patents
用于形成集成半导体结构的方法和结构 Download PDFInfo
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- CN102859681B CN102859681B CN201180007701.2A CN201180007701A CN102859681B CN 102859681 B CN102859681 B CN 102859681B CN 201180007701 A CN201180007701 A CN 201180007701A CN 102859681 B CN102859681 B CN 102859681B
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本发明提供了用于制造半导体结构的方法和结构,并且特别地提供了用于形成具有改进的平坦度以实现包括已处理半导体结构和多个键合半导体层的键合半导体结构的半导体结构。用于形成半导体结构的方法包括:在已处理半导体结构的非平坦表面上方形成介电层,对介电层的与已处理半导体结构相反的一侧上的表面进行平坦化,以及将半导体结构附接到介电层的平坦化表面。半导体结构包括:覆盖在已处理半导体结构的非平坦表面上方的介电层,以及在介电层的与已处理半导体结构相反的一侧上覆盖介电层的掩蔽层。掩蔽层包括:位于已处理半导体结构的非平坦表面的导电区上方的多个掩蔽开口。
Description
优先权声明
本申请要求2010年2月4日提交的标题为“Methods and Structure for FormingIntegrated Semiconductor Structures”的美国临时专利申请No.61/301476的申请日的权益。
技术领域
本发明的各种实施方式总体上涉及用于形成半导体结构的方法和结构,更具体地涉及在半导体结构上形成平坦表面以便附接额外的半导体结构的方法和结构。
背景技术
两个或者更多个半导体结构的三维(3D)集成在微电子应用中可以是有益的。例如,微电子器件的3D集成可以减小整体器件占用面积并且改善电气性能和功耗。例如,参见the publication of P.Garrou et al.,2008,entitled“The Handbook of 3DIntegration,”Wiley-VCH。
可以通过多种方法实现半导体结构的3D集成,这些方法包括:例如将一个或者更多个半导体结构附接到包括多个器件结构的已处理半导体结构。可以通过多种方法实现将半导体结构附接到已处理半导体结构。当将半导体结构附接到已处理半导体结构时,该半导体结构可以经过一些额外处理,并且该半导体结构本身也可以作为用于后续半导体结构的附接的接收衬底。应当注意的是,可以通过将半导体裸片附接到一个或者更多个额外的半导体裸片(即,裸片到裸片(D2D))、将半导体裸片附接到一个或者更多个额外的半导体晶圆(即,裸片到晶圆(D2W))以及将半导体晶圆附接到一个或者更多个额外的半导体晶圆(即,晶圆到晶圆(W2W))或者上述方式的组合来进行半导体结构的3D集成。
然而,要彼此附接的结构中的每一个结构(例如,已处理半导体结构和半导体结构的附接表面)的光滑度和平坦度可能影响完成的3D集成半导体结构的质量。例如,当结构的3D集成包括其中已经形成了半导体器件的已处理半导体结构时,用于形成半导体器件的处理可能导致粗糙的非平坦表面。半导体结构到该已处理半导体结构的粗糙的非平坦表面的后续的附接可能导致半导体结构和已处理半导体结构之间的较差的粘合,这会导致半导体结构在后续处理期间从已处理半导体结构不希望地分离。
发明内容
本发明的各种实施方式总体上提供用于形成半导体结构的方法和结构,具体地提供了用于在半导体结构上形成光滑的平坦表面以附接额外的半导体结构的方法和结构。现在根据本发明的实施方式简要描述本发明的方法。本发明内容用于以简化的形式介绍概念的选择,这些概念在本发明的具体实施方式中进一步描述。发明内容不旨在标识出要求保护的主题的关键特征或者本质特征,也不旨在用于限制要求保护的主题的范围。
因此,在本发明的一些实施方式中,形成半导体结构的方法包括:在已处理半导体结构的非平坦表面上方形成介电层。已处理半导体结构的所述非平坦表面可以包括多个导电区和多个非导电区。在所述介电层上方形成掩蔽层,并且设置延伸穿过直接位于所述已处理半导体结构的所述非平坦表面的所述多个导电区中的至少一些导电区上方的所述掩蔽层的多个掩蔽开口。可以对位于所述介电层的与所述已处理半导体结构的所述非平坦表面相反的一侧的表面进行平坦化以形成平坦化表面。对所述介电层的表面进行平坦化的步骤可以包括:蚀刻通过所述多个掩蔽开口露出的所述介电层的区域,以及在蚀刻所述介电层的所述区域之后对所述介电层的表面进行抛光。然后,半导体结构可以附接到所述介电层的平坦化表面。
本发明的各个实施方式还可以包括用此处描述的方法形成的结构。例如,在一些实施方式中,半导体结构包括:覆盖在已处理半导体结构的非平坦表面上方的介电层。所述非平坦表面包括多个导电区和多个非导电区。所述半导体结构可以还包括:在介电层的与已处理半导体结构相反的一侧上覆盖介电层的掩蔽层,所述掩蔽层可以包括延伸穿过直接位于所述已处理半导体结构的所述非平坦表面的所述多个导电区中的至少一些导电区上方的所述掩蔽层的多个掩蔽开口。
本发明的其它方面、细节以及另选组合将从下面的详细描述中变得明显,并且也在本发明范围内。
附图说明
通过参照以下在附图中示出的本发明的示例性实施方式的详细描述可以更充分地理解本发明,在附图中:
图1A-图1C示意地例示将半导体结构附接到已处理半导体结构的现有技术;
图2A-图2C示意地例示将半导体结构附接到已处理半导体结构的另一现有技术;
图3A-图3F示意地例示用于形成3D集成的半导体结构的本发明的实施方式;
图4A-图4F示意地例示用于形成3D集成的半导体结构的本发明的额外的实施方式。
具体实施方式
此处呈现的附图并非任何特定结构、材料、装置、系统或者方法的实际视图,而仅仅是用来描述本发明的实施方式的理想化表示。
标题在此处使用仅是为了描述的清楚,并不旨在限制所附的权利要求的范围。此处引用了若干参考文献,通过引用将其整体并入这里。此外,不管在此如何描述所引用的参考文献,引用的参考文献均不被承认是相对于此处要求保护的主题的发明的现有技术。
如此处所用的,术语“半导体结构”是指并且包括包含半导体材料的任何结构,所述半导体材料包括诸如半导体晶圆(自己或者与其上包含的其它材料组合)这样的体半导体材料;和半导体材料层(单独的或者与其上包含的诸如金属和绝缘体的其它材料组合件)。另外,术语“半导体结构”还包括任何支撑结构,所述支撑结构包括但不局限于上面所述的半导体结构。术语“半导体结构”也可指包括半导体器件的有源或者可操作部分的一个或者更多个半导体层或者结构以及处理过程中的半导体结构(并且可以包括在其上制造的诸如绝缘体上硅(SOI)等的其它层)。
如此处所用的,术语“已处理半导体结构”是指并且包括已应用了各种工艺处理的半导体结构。
如此处所用的,术语“器件结构”是指并且包括包含用于并入半导体器件中的有源或者无源器件部件的任何结构。
如此处所用的,术语“键合结构”是指并且包括通过附接工艺彼此键合的两个或者更多个半导体结构。
通过对本发明的实施方式的介绍,图1A-图1C和图2A-图2C例示将半导体结构附接到已处理半导体结构的现有技术的方法,以及在这样的方法期间形成的半导体结构。
图1A例示包括已处理半导体结构102的半导体结构100。已处理半导体结构可以包括多个导电区104、介电层106、器件层108和器件衬底110。多个导电区104可以包括若干子区,这些子区包括例如屏障子区、电极子区和通孔子区。多个导电区104可以包括一种或者更多种材料,诸如,例如,钴、钌、镍、钽、氮化钽、氧化铟、钨、氮化钨、氮化钛、铜和铝。
介电层106是电气绝缘的,并且可以包括一种或者更多种介电材料,诸如,例如,聚酰亚胺、苯并环丁烯(BCB)、硼氮化物、硼碳氮化物、多孔硅酸盐、硅氧化物、硅氮化物及其混合物。此外,介电层106可以包括多个介电材料层,其中的一些层可以具有与形成介电层106的一个或者更多个其它介电材料层不同的材料成分。
器件层108可以包括多个器件结构,诸如,例如,开关结构(例如,晶体管等)、发光结构(例如,激光二极管、发光二极管等)、光接收结构(例如,波导、分束器、混频器、光电二极管、太阳能电池单元、太阳能电池子单元等)以及微电子机械结构(例如,加速度计、压力传感器等)中的一种或者更多种。在本发明的一些实施方式中,器件层108可以包括金属氧化物半导体(CMOS)集成电路、晶体管-晶体管逻辑集成电路和NMOS逻辑集成电路中的一种或者更多种。
器件衬底110可以包括多种材料中的任意一种,诸如,例如,硅、锗、碳化硅、III族砷化物、III族磷化物、III族氮化物、III族锑化物、蓝宝石、石英和氧化锌中的一种或多种。此外,器件衬底110可以包括多层上述材料,其中的一些层可以具有不同的材料成分。
图1B例示可以通过从图1A的半导体结构100去除器件衬底110的部分110`(在图1B中部分110`用虚线表示)而形成的半导体结构115。去除器件衬底110的部分110`可以减薄器件衬底110,并将多个导电区104`通过器件衬底110露出。导电区104`可以是或者包括本领域中所谓的“贯穿硅通孔”或者“贯穿衬底通孔”(TSV),并且可以提供器件层108通过器件衬底110到将后续附接到半导体结构115的另外半导体结构的电气连接。可以通过诸如,例如,抛光、研磨、蚀刻方法以及这些方法的组合(例如化学机械抛光)来去除器件衬底110的部分110`。
如图1B所示,去除器件衬底110的部分110`可以导致多个破损区112,其包括位于器件衬底110的材料中的谷。破损区112会导致已处理半导体结构102具有非平坦表面114。已处理半导体结构102的区间116包括已处理半导体结构102的非平坦表面114。如图1B所示,已处理半导体结构的非平坦表面114包括由器件衬底110的区域限定并且包括器件衬底110的区域的多个导电区104`和多个非导电区。在一些实施方式中,导电区104`可以包括金属区,并且非导电区可以包括非金属区。
图1C例示可以通过将另一个半导体结构122附接到图1B的半导体结构115的非平坦表面114形成的半导体结构120。半导体结构122可以沿着已处理半导体结构102的非平坦表面114和半导体结构122的相邻表面之间的键合界面124经键合附接到已处理半导体结构102。由于非平坦表面114,键合界面124会是不连续的。换句话说,键合界面124可以包括键合区和未键合区。另外,在用于去除器件衬底110的部分110`的处理中可能导致的多个破损区112可能导致多个未键合区。由于在半导体结构122和已处理半导体结构102之间存在未键合区域,因此它们之间的键合强度对于例如诸如装卸和补充处理的额外的操作而言可能是不充分的。
图2A-图2C例示用于将半导体结构附接到已处理半导体结构的另一现有技术。图2A例示包括已处理半导体结构202的半导体结构200。已处理半导体结构202可以包括导电区204、介电层206、器件层208和器件衬底210。已处理半导体结构202及其组成元件可以包括以上关于图1A-1C所描述的全部材料和结构。
图2B例示可以通过从图2A中的半导体结构200去除导电区204的部分204`(在图2B中部分204`用虚线表示)而形成的半导体结构215。导电层204的部分204`可以被去除以产生多个导电区204。多个导电区204可以提供到器件衬底208内存在的多个器件结构的电气连接。可以通过诸如,例如,抛光、研磨、蚀刻以及这些处理的组合(例如化学机械抛光)来去除导电层204的部分204`。在一些实施方式中,可以通过本领域中一般称为“镶嵌(Damascene)”的方法形成多个导电区204。这种方法例如在Joshi et al.,“A new Damascene structure for submicrometer wiring”,IEEEElectron Device Letters,Volume 14,No.3,pages 129-132,1993中有进一步详细描述。
如图2B所例示,去除导电层204的部分204`会导致介电层206的部分的去除。介电层206的部分的去除或者“破损”可以产生多个破损区212,并可以导致已处理半导体结构具有非平坦表面214。已处理半导体结构202的区间216包括非平坦表面214。非平坦表面214可以包括多个导电区204和多个非导电区206。在一些实施方式中,这些多个导电区204可以包括多个金属区,并且这些多个非导电区206可以包括多个非金属区。
图2C例示可以通过将另一半导体结构222附接到图2B的半导体结构215的已处理半导体结构202的非平坦表面214而形成的半导体结构220。半导体结构222可以在已处理半导体结构202的非平坦表面214和半导体结构222的相邻表面之间的键合界面224处经键合附接到已处理半导体结构202。如上所述,已处理半导体结构202的非平坦表面214可以导致不连续的键合界面224,这会不利地影响已处理半导体结构202和半导体结构222之间的键合强度,并且会使键合强度不足以用于将在半导体结构220上进行的额外的操作。
本发明的实施方式可以包括为了允许附接半导体结构而改进已处理半导体结构的表面的平坦性的用于形成半导体结构的方法和结构。这些方法和结构可以用于各种目的,诸如,例如,生产3D集成处理和3D集成结构。
以下参照图3A-图3F描述本发明的示例性实施方式。图3A例示半导体结构300,其包括已处理半导体结构316的非平坦表面314。非平坦表面314可以包括多个导电区304(例如,金属区)和多个非导电区306(例如,非金属区)。作为非限制性示例,半导体结构300可以包括图1B的区间116或者图2B的区间216。因此应指出的是半导体结构300可以包括已处理半导体结构316,其包括为了清楚而从图中省略的多个已处理半导体结构元件。
多个非导电区306可以是诸如,例如图1B的示例中的器件衬底110的器件衬底的部分。器件衬底可以包括一个或者更多个同质或异质的半导体层,并且可以包括多种材料中的任意一种。例如,器件衬底可以包括硅、锗、碳化硅、III族砷化物、III族磷化物、III族氮化物、III族锑化物、蓝宝石、石英和氧化锌中的一种或者更多种。如前文所述,器件衬底还可以包括多个器件结构。例如,这些器件结构可以包括例如金属氧化物半导体(CMOS)集成电路、晶体管-晶体管逻辑集成电路和NMOS逻辑集成电路中的一种或者更多种。
半导体结构300的多个非导电区306可以是诸如,例如图2B的示例中的介电层206的介电层的部分。介电层可以包括一个或者更多个介质材料层,并且可以包括下述若干材料中的任意一种,例如,聚酰亚胺、苯并环丁烯(BCB)、硼氮化物、碳化硼氮化物、多孔硅酸盐、硅氧化物、硅氮化物及其混合物。
半导体结构300的多个导电区304可以包括若干子区,这些子区可以包括例如屏障子区和电极子区。此外,导电区304可以包括若干材料中的任意一种,诸如,例如钴、钌、钽、氮化钽、氧化铟、氮化钨、氮化钛、铜和铝中的一种或者更多种。
如图3A的虚线区域所示地并且如前文详细描述地去除半导体结构300的已处理半导体结构316的部分316`可以导致形成多个破损区312。例如,在一些实施方式中,去除已处理半导体结构316的部分316`可以涉及去除诸如图1B中例示的器件衬底110的器件衬底的部分。在本发明的其它实施方式中,去除已处理半导体结构316的部分316`可以涉及去除诸如图2B中例示的导电层204的导电层的部分。与被从已处理半导体结构316去除的材料无关,去除可以导致形成多个破损区312,这可以导致形成非平坦表面314。在本发明的特定实施方式中,可以通过诸如,例如化学机械抛光处理这样的抛光处理来形成已处理半导体结构的非平坦表面314。
非平坦表面314的拓扑包括多个峰区326和多个谷区328。多个破损区312可以包括或者限定多个谷区328(即,非平坦表面314的下面的区),并且不包括多个破损区312的非平坦表面区314可以包括或者限定所述多个峰区326。最大峰谷距离可以被定义为最下面的谷区328与最高的峰区326之间的最大竖直距离。例如,图3A的小图例示非平坦表面314的最下面的谷区328`与最高的峰区326`。峰区326`与谷区328`之间的竖直距离可以被定义为最大峰谷距离PVmax。
图3B例示可以通过在图3A的已处理半导体结构316上方设置介电层330而形成的半导体结构310。介电层330覆盖非平坦表面314,并且具有平均层厚度D1。介电层330可以包括一种或者更多种介电材料,诸如,例如氧化硅、硅氮化物及其混合物。在一些实施方式中,介电层330可以包括多个介电材料层。在这些实施方式中,层的介电材料可以具有类似或者不同的成分。
可以利用多种方法形成介电层330,以覆盖非平坦表面314的全部或者部分。例如,可以利用沉积法,诸如,例如化学气相沉积(CVD)来形成介电层330。本领域已知若干种CVD法,并且可以用来产生介电层330。这些CVD法包括例如,大气压力CVD(APCVD)、低压CVD(LPCVD)和超高真空CVD(UHCVD)。在本发明的一些实施方式中,可以利用低温CVD法来形成介电层330,这些方法可以包括例如,等离子辅助CVD法,诸如,例如,次大气CVD(SACVD)、微波等离子辅助CVD(MPCVD)、等离子增强CVD(PECVD)和远程等离子增强CVD(RPECVD)。在本发明的一些实施方式中,可以利用用于沉积介电层330的等离子辅助CVD法来提供低温沉积处理。可以利用低温沉积处理,以防止已处理半导体结构316中可能存在的多个器件结构的劣化。
更具体地说,已处理半导体结构316可以包括多个器件结构,如果介电层330的沉积温度高于器件劣化开始的临界温度,则这些器件结构可能损坏。因此,在本发明的一些实施方式中,可以在低于约600℃的温度、低于约500℃的温度或者低于约400℃的温度形成介电层330。
如图3B所例示,介电层330可以共形地沉积在已处理半导体结构316的非平坦表面314上方。可以利用介电层330的共形沉积,以塞入(即,填充或者密封)多个破损区312,即,填充非平坦表面314的破损区312。然而,由于共形膜可以具有在介电层330范围内基本上均匀的厚度,因此采用共形沉积处理来插入多个破损区312可以导致介电层330具有非平坦表面332。也就是说,介电层330的材料可以基本上保留下面的非平坦表面314的拓扑。
在本发明的一些实施方式中,介电层330可以具有大于最大峰谷距离PVmax的平均层厚度D1。平均层厚度D1可以被选择为大于PVmax,从而破损区312可以基本上被介电层330塞住。
图3C例示可以通过在图3B的半导体结构310的介电层330上设置蚀刻掩蔽层334而形成的半导体结构320。蚀刻掩蔽层334可以包括一个或者更多个蚀刻掩蔽区336以及多个延伸通过蚀刻掩蔽层334的蚀刻掩蔽开口338。多个蚀刻掩蔽开口338可以覆盖在已处理半导体结构316的非平坦表面314的多个导电区304上。也就是说,蚀刻掩蔽开口338可以对准非平坦表面314的导电区304,并且被直接布置在非平坦表面314的导电区304上。相反地,多个蚀刻掩蔽区336可以直接位于非平坦表面314的多个非导电区306上。
更具体地,如图3C所例示,当形成介电层330时,可以利用蚀刻掩蔽层334选择性地掩蔽介电层330的非平坦表面332。可以利用本领域中已知的工艺产生蚀刻掩蔽层334。例如,诸如利用光敏化学制品和光刻的技术,以及掩蔽材料的沉积和掩蔽材料的图案化蚀刻的技术。用于形成蚀刻掩蔽层334(即,多个蚀刻掩蔽区336)的掩蔽材料可以包括例如感光聚合物(例如,聚甲基丙烯酸甲酯、邻叠氮萘醌等)、电介质(例如,硅氧化物、硅氮化物等)和金属材料(例如,钨、镍、铬等)。
对蚀刻掩蔽层334进行构图从而多个蚀刻掩蔽开口338覆盖导电区304(例如,对准导电区304并且被直接布置在导电区304上方)的步骤可以包括:在蚀刻掩蔽层334的掩蔽材料中形成多个导电区304的负像。可以用多种方法来在蚀刻掩蔽层334中形成多个导电区304的负像。例如,可以使用光刻来形成蚀刻掩蔽层334。在这种实施方式中,可以采用感光聚合物形成蚀刻掩蔽层334。如本领域中已知的,感光聚合物层可以在未聚合/或未交联的状态下进行沉积,通过光学掩模选择性地暴露于电磁辐射以使感光聚合物层的选择的区域聚合和/或交联,然后进行显影以去除感光聚合物层的部分。如本领域中已知的,感光聚合材料可以包括正光刻胶材料或者负光刻胶材料,并且基于光刻胶材料是正光刻胶材料还是负光刻胶材料来选择光学掩模的图案(即,正图案和负图案)。此外,如本领域中已知的,光刻胶材料可以具有图像反转能力(例如,能够在正图像和负图形之间进行转换)。这样的技术可以用来将蚀刻掩蔽层334形成或者构图为包括在至少基本上对应于下面的多个导电区304的位置的位置处在其中包括多个蚀刻掩蔽开口338。换句话说,蚀刻掩蔽开口338的图案可以至少基本上对应于下面的多个导电区304的图案,并且蚀刻掩蔽开口338可以对准导电区304并且直接位于导电区304上方。
蚀刻掩蔽层334可以用于在蚀刻处理期间保护介电层330的选择区域免受蚀刻剂,同时将介电层330的其它区域通过多个蚀刻掩蔽开口338暴露于蚀刻剂。结果,可以从通过蚀刻掩蔽开口338暴露的介电层330的区域去除材料,这些区域可以包括多个峰区326。因而,由于在蚀刻处理期间蚀刻峰区326,并且通过蚀刻掩蔽层334保护谷区328免受蚀刻处理,所以介电层330的平坦性可以得到改善。图3C例示对介电层结构330的选择性蚀刻,其中,虚线340表示在蚀刻前的介电层330的初始位置,并且线342表示选择性蚀刻处理期间或者之后的介电层330的位置。
可以利用诸如,例如湿法化学蚀刻技术或者干法蚀刻技术的多种方法来实现通过多个掩蔽开口338对介电层330的选择性蚀刻。在本发明的特定实施方式中,如图3C中的等离子蚀刻箭头344所指示的,可以利用各向异性等离子蚀刻处理的干法蚀刻技术。这些等离子蚀刻技术可以例如包括反应离子蚀刻(RIE)、电感耦合等离子蚀刻(ICP)和电子回旋谐振蚀刻(ECR)中的一种或者更多种。
用于去除介电层330的部分的蚀刻剂的具体化学成分可以被选择为等离子蚀刻剂344对介电层330比对蚀刻掩蔽区336更有选择性。换句话说,等离子蚀刻剂344可以在比等离子蚀刻剂344蚀刻掉蚀刻掩蔽区336的材料的任何速率显著更高的速率来蚀刻掉介电层330的材料。这样的选择可以基于蚀刻掩蔽区336的材料和介电层330的材料的成分。作为非限制性示例,介电层330可以包括氧化硅、氮化硅或者其混合物,其是在利用从包括相对于包括例如通过利用从包括含氟物质(例如,CHF4、SF6和CF4)的气体化学物产生的等离子的情况下相对于包括例如感光聚合物的掩蔽材料具有蚀刻选择性的材料。
图3D例示可以在如上所述通过蚀刻掩蔽开口338蚀刻介电层330之后从图3C的半导体结构320去除蚀刻掩蔽层334的蚀刻掩蔽区336而形成的半导体结构331。当去除蚀刻掩蔽区336时,介电层330可以在与已处理结构316相反的一侧具有基本平坦的表面332`。相对于关于图3C描述的蚀刻处理之前的介电层330的表面332(图3B)的平坦度,基本上平坦的表面332`的平坦度可以得到实质上的改进。介电层330的表面332`的平坦度可能对于键合到后续附接的其它半导体结构是足够的。然而,在本发明的特定实施方式中,介电层330的表面332`可以被进一步处理以实现具有足够平坦度的表面,以便实现与后续附接的其它半导体结构的适当的键合强度。
图3E示出了可以通过使图3D的半导体结构331的介电层330的表面332`进行一个或者更多平坦化处理以进一步改进介电层330的表面的平坦度而形成的半导体结构340。该一个或更多平坦化处理可以用于产生介电层330的至少基本上平坦的表面332``,其可以具有适合于后续附接到其它半导体结构的平坦度。
更具体地,本领域已知用于产生介电层结构340的平坦化表面332``的若干方法。例如,可以利用蚀刻处理、研磨处理和抛光处理中的一个或者更多个来进行平坦化处理。在本发明的一些实施方式中,平坦化处理可以是或者包括化学机械抛光(CMP)处理。诸如浆研磨剂和化学的组成的CMP处理条件可以被选择为第一介电层330的表面332`(图3D)被进一步平坦化,从而得到平坦表面332``。
平坦表面332``可以进行进一步的处理以获得足够的表面光滑度以便实现与附接的半导体结构的高的键合强度。
可以利用等离子处理对表面332``进行进一步的平坦化。此外,这样的等离子处理还可以按照可以改进将在平坦表面332``与后续附接的另一半导体结构之间获得的键合强度的方式通过改变表面化学来“活化”平坦表面332``。借助于非限制性示例,可以通过将半导体结构340暴露到氧等离子346来进行对介电层330的平坦表面332``的等离子平滑和活化。在例如Choi et al,“The analysis of Oxygen Plasma Pretreatmentfor Improving Anodic Bonding”,Journal of the Electrochemical Society,149 1 G8-G11(2002)中进一步详细描述了这种处理。
在本发明的方法的特定实施方式中,平坦表面332``可以具有小于约100小于约10或者甚至小于约3的均方根(rms)表面粗糙度。
图3F例示可以通过将另一半导体结构322附接到图3E的半导体结构340的介电层330的表面332``(或者附接到图3D的半导体结构331的介电层330的表面332`)而形成的半导体结构360。半导体结构322可以包括可以直接或者间接键合到介电层330的表面332``的键合表面348。如图3F中的小图3中所示,在本发明的一些实施方式中,可以在半导体结构322和介电层330之间设置键合辅助层350。键合辅助层350可以包括若干种材料中的任意一种。在一些实施方式中,键合辅助层350可以包括一种或者更多种介电材料,诸如,例如,氧化硅、氮化硅及其混合物中的一种或者多种。此外,在一些实施方式中,键合辅助层350本身可以包括多个单独的层,这些层可以具有类似或者不同的材料成分。
半导体结构322可以包括多种结构和材料中的任意一种。例如,半导体结构322可以包括器件结构和键合结构中的至少一种。
更具体地,半导体结构322可以至少包括单一半导体材料的基本同质层。一些这样的半导体结构包括本领域中被称为自支撑衬底(FS衬底)。同质材料可以包括例如基本材料或者复合材料,并且可以是导体(例如,金属)、半导体或者绝缘体。在一些实施方式中,同质材料可以包括硅、锗、碳化硅、III族砷化物、III族磷化物、III族氮化物、III族锑化物、II-VI族化合物、金属、金属合金、蓝宝石、石英和氧化锌中的一种或更多种。此外,在一些实施方式中,同质材料可以至少基本上由同质材料的单晶体构成。
在本发明的另外的实施方式中,半导体结构322可以包括异质结构,其包括包含两个或更多不同材料的层的结构。这些异质半导体结构可以包括例如基础衬底上的模板结构(诸如,例如,半导体材料层)。在这些实施方式中,模板结构和基础衬底可以包括之前提到的材料。此外,半导体结构可以包括在彼此顶部上生长、沉积或者放置以形成层堆叠的两种或更多种材料。同样地,这些半导体结构可以包括之前提到的材料。
在本发明其它实施方式中,半导体结构322可以包括器件结构。器件结构可以包括有源部件、无源部件以及其混合。器件结构可以包括例如开关结构(例如,晶体管等)、发光结构(例如,激光二极管、发光二极管等)、光接收结构(波导、分束器、混频器、光电二极管、太阳能电池单元、太阳能电池子单元等)以及微电子机械结构(例如,加速度计、压力传感器等)中的一种或者更多种。在本发明的一些实施方式中,半导体结构322可以包括利用本发明的方法处理的已处理半导体结构。例如,半导体结构322可以包括如图3D的半导体结构311或者图3E的半导体结构340那样的半导体结构。
在本发明的其它实施方式中,半导体结构332可以包括键合结构,其中两个或者更多元件被附接并且键合在一起。在本发明的一些实施方式中,可以利用本发明的方法来制造键合结构。
可以通过分子粘附产生半导体结构322和已处理半导体结构316通过介电层330的键合(即,不使用胶、蜡、焊料或其它键合剂的键合)。例如,键合操作可以要求键合表面332``和键合表面348足够光滑,无颗粒和污染,并且能够被充分彼此接近地放置以允许进行接触(通常在小于5nm的距离)。当达到这样接近度时,键合表面332``和表面348之间的吸引力将足够高从而引起分子粘附(由两个表面的原子或者分子间电子相互作用得到的全部吸引力(例如,范德华力)引起的键合)。
通常可以通过例如使用TEFLON探针在与另一个元件紧密接触的元件上施加局部压力以触发键合波从触发点开始传播来实现分子粘附的触发。术语“键合波”是指从起始点扩展并且与吸引力从启动点起在键合表面332``和键合表面348之间的整个界面的散播相对应的键合或分子粘附的前部。例如,参考the journal publications ofTong et al.,Materials,Chemistry and Physics 37 101 1994,entitled“Semiconductor waferbonding:recent developments,”和Christiansen et al.,Proceedings of the IEEE 94 12 20602006,entitled“Wafer Direct Bonding:From Advanced Substrate Engineering to FutureApplications in Micro/Nanoelectronics.”。
当已处理半导体结构316键合到半导体结构322时,可以进行进一步的键合后处理。例如,可以在100-600℃之间的温度对半导体结构360退火,以增加已处理半导体结构316和半导体结构322之间的键合强度。可以执行增加已处理半导体结构316和半导体结构322之间的键合强度的步骤以降低半导体结构322从已处理半导体结构316不希望地分离(例如,在后续处理期间可能出现分离)的可能性。
半导体结构360的进一步处理可以包括多个其它操作和过程中的任意一个。例如,在本发明的一些实施方式中,可以利用本领域中已知的方法对半导体结构322减薄。在其它实施方式中,结构360可以附接到一个或者更多个其它半导体结构。在本发明的其它实施方式中,可以在半导体结构360的表面上和/或中(例如,在半导体结构322的表面上和/或中)制造多个器件,因而形成额外的已处理半导体结构。用于进一步处理半导体结构360的一种或多种方法可以被执行一次或者更多次,并且还可以利用本发明的方法的实施方式来产生用于附接额外的半导体结构的光滑的平坦表面。
现在参照图4A-图4F描述本发明的其它实施方式。这些其它实施方式类似于以上描述的实施方式,不同之处在于,在图4A-图4F的实施方式中,介电层包括三个或者更多层。因此,为简洁起见,此处省略了对图4A的半导体结构400的制造方法和结构元件的完整描述,因为前面已经参照图3C的半导体结构320进行了描述。将在下文中详细描述与介电层330和后续的平坦化和附接方法有关的不同。此外,用相同的附图标记标识了图4A-图4F中与图3A-图3F的相应元件非常类似的元件。
图4A的半导体结构400包括已处理半导体结构316的非平坦表面314、介电层330和蚀刻掩蔽层334。在本发明的一些实施方式中,介电层330可以包括三个或者更多介电材料层。例如,如图4A所例示,介电层330可以包括第一层330a、第二层330b和第三层330c。这种多层介电结构可以辅助形成具有足以获得介电层330和后续附接的半导体结构之间的足够的键合强度的足够的平坦度的平坦表面的介电层330。
介电材料层330a、330b和330c中的每一个都可以包括一种或多种材料,诸如,例如,硅氧化物、硅氮化物及其混合物。第二介电材料层330b可以具有被选择为使得第二层330b是并且用作第一介电材料层330a和第三层介电材料330c之间的蚀刻停止层的组成。
此外,如之前关于图3B所讨论的,介电层330(由全部三个层330a、330b和330c组成)可以具有大于PVmax的平均总厚度D1。然而,另外,介电层330的第一层330a可以具有本身大于PVmax的平均层厚度D2,即,第一层330a的平均厚度D2可以大于非平坦表面314的最大峰谷距离。在本发明的特定实施方式中,第二层330b(即,蚀刻停止层)可以具有大约大于100nm的平均层厚度,而第三介电材料层330c可以具有大约大于100nm的平均层厚度。
在本发明的特定实施方式中,第三层330c和第一层330a可以由本质上相同的材料(即,具有至少基本类似的成分的材料)组成。作为非限制性示例,第一层330a和第三层330c可以包括氧化硅(例如,二氧化硅),并且第二层330b(蚀刻停止层)可以包括不同于第一层330a和第三层330c中的每一层的材料。作为非限制性示例,第二层330b可以包括氮化硅。
可以利用先前关于图3B所讨论的沉积方法形成介电层330。例如,可以在低于约400℃的温度利用等离子辅助化学气相沉积形成介电材料层330a、330b和330c。如图4A所例示,沉积顺序可以执行为在第一介电材料层330a与第三介电材料层330c之间沉积第二层330b(蚀刻停止层)。
图4A的半导体结构400还可以包括掩蔽层334。如先前所讨论的,掩蔽层334可以包括与多个导电区304对准并且直接位于多个导电区304上方的多个蚀刻掩蔽开口338。换句话说,蚀刻掩蔽开口338的图案可以至少基本上对应于下面的多个导电区304的图案。
图4B例示可以通过蚀刻掉通过蚀刻掩蔽层334中的蚀刻掩蔽开口338暴露的介电层330的区域而形成的半导体结构410。介电层330的被蚀刻发部分在图4B中用虚线例示。
更具体地,例如可以使用蚀刻处理去除介电层330的部分,以辅助介电层330的表面的平坦化。例如,如图4B的箭头344所例示,可以采用各向同性或者各向异性等离子蚀刻处理进行蚀刻。在特定实施方式中,可以利用反应离子蚀刻或者电感耦合等离子蚀刻进行等离子蚀刻处理。
蚀刻处理可以包括选择性地蚀刻第三层330c的暴露部分330c`直至第二层330b的部分330b`露出为止,接下来选择性地蚀刻第二层330b(蚀刻停止层)的暴露部分330b`直至第一介电材料层330a的部分330a`露出为止。介电材料层330a、330b和330c的成分以及蚀刻化学物质可以被选择为允许选择性地蚀刻各介电材料层330a、330b和330c(即,优选地去除一个层同时下面的层被较不明显地蚀刻)。
在本发明的特定实施方式中,第一介电材料层330a和第三介电材料层330c可以包括氧化硅,并且第二层(蚀刻停止层)可以包括氮化硅。本领域已知的是,通过对蚀刻工艺和蚀刻化学过程的选择,氧化硅可以相对于氮化硅优先被等离子蚀刻,并且反之亦然。对于选择性蚀刻处理的更详细描述,例如可以参见the publication of VanRoosmalen et al.,1991,entitled“Dry etching for VLSI,”Plenum Press,New York。对于湿法化学过程,已知特定的基于氢氟酸(HF)的蚀刻溶液相对于氮化硅选择性地蚀刻氧化硅,而已知特定的基于磷酸(H3PO4)的蚀刻溶液相对于硅氧化物选择性地蚀刻硅氮化物。当去除介电层330的被选择的暴露部分时,可以采用本领域已知的方法去除蚀刻掩蔽层334的剩余部分。
图4C例示可以通过抛光穿过第三介电材料层330c的厚度直至露出剩余的第二层330b(蚀刻停止层)而形成的半导体结构420。在特定实施方式中,可以利用化学机械抛光(CMP)处理来进行第三介电材料层330c的抛光。可以如本领域已知的那样来选择包括浆研磨剂的组成和化学过程的CMP处理条件,从而可以选择性地去除第三介电材料层330c,从而使得暴露第二层330b。
当抛光穿过第三层330c的厚度直至第二层330b(蚀刻停止层)露出为止时,也可以通过例如利用选择性的蚀刻处理去除第二层330b的剩余部分。在本发明的特定实施方式中,如图4C中箭头344`所示,可以通过等离子蚀刻处理选择性地蚀刻第二层330b。这样的等离子蚀刻处理可以包括,例如,先前描述的选择性反应离子蚀刻处理或者电感耦合等离子蚀刻工艺。如前所述,第二层330b(蚀刻停止层)可以包括氮化硅,而第一介电材料层330a可以包括氧化硅。因此,用来去除第二层330b的等离子蚀刻处理可以对具有硅氧化物具有对于硅氮化物的选择性,从而相对于第一介电材料层330a的硅氧化物材料优先去除第二层330b的硅氮化物材料。
如图4D-图4F所示,后续处理可以以类似于先前参照图3D-图3F描述的方式进行。简而言之,图4D例示可以通过抛光穿过剩余的第三介电材料层330c的厚度直至第二层330b(蚀刻停止层)露出为止,并且接下来选择性地蚀刻剩余的第二层330b直至第一介电材料层330a(基本上类似于图3D的介电层330)露出而形成的半导体结构430。图4E例示可以通过进一步平坦化第一介电材料层330a的表面332`以产生进一步平坦化的介电表面332``而从图4D的半导体结构430形成的半导体结构440。可以执行如图4E中的箭头346所示的包括等离子平滑化和活化的进一步的处理以实现平坦表面332``的想要的表面化学性质和平滑度。如图4F中所示,可以通过如以上参考图3F所详细描述地将另一半导体结构322附接(例如,键合)到半导体结构316而形成半导体结构460。
示例
现在描述非限制性示例以示出本发明的具体实施方式。应当理解的是,在下述示例中,参数、材料、结构等只是为了示出性目的而提供的,并且不限制本发明的实施方式。
参照图3A,提供了已处理半导体结构316,其包括互补金属氧化物半导体器件衬底306,其包括多个器件结构,该多个器件结构例如包括场效应晶体管。导电区304包括:诸如钽的屏障材料以及包括例如铜的电极材料。通过用于去除已处理半导体结构316的部分316`(如图3A中虚线所示)的CMP形成多个破损区312。
参照图3B,在非平坦表面314上方共形地沉积介电层330。介电层330包括在150-400℃之间的温度通过等离子增强化学气相沉积(PECVD)沉积的二氧化硅(SiO2)。用于PECVD沉积的前驱物可以包括硅烷(SiH4)、正硅酸乙酯(TEOS)、氧(O2)、氢(H2)和一氧化二氮(N2O)。介电层330的平均厚度D1大于非平坦表面314的最大峰谷距离PVmax。在本发明的一些实施方式中,D1可以大于大约100nm。在本发明的其它实施方式中,D1可以大于大约1μm。
参照图3C,介电层330涂覆有包括正对比度感光聚合物的蚀刻掩蔽层334。使用利用多个导电区304的图案的负像构图的光刻掩模对蚀刻掩蔽层334进行构图。当曝光和显影时,直接在多个导电区304的上方形成多个掩蔽开口338。接下来,在反应离子蚀刻处理中,介电层330的通过掩蔽开口338暴露的部分被暴露到基于氟的蚀刻等离子334,以去除介电层330的通过掩蔽开口338暴露的部分。然后可以去除蚀刻掩蔽层334。
参照图3D,通过CMP处理抛光介电层330的表面332`,以提供图3E的进一步平坦化的表面332``。除了CMP抛光处理之外,介电层330的表面332``暴露于氧等离子中,以提供具有适于后续被附接到半导体结构的rms粗糙度的表面332``。可以通过将半导体结构340放到反应离子蚀刻器(RIE)中并且让表面332``经受氧等离子来进行等离子平滑处理。RIE室可以被设定为大约50mTorr的压力,同时可以使用氧气作为氧的来源。进入RIE室的氧气的流量可以是大约30sccm。等离子自偏压可以在-60V到-360V之间变化。
参照图3F,半导体结构322包括硅衬底,其包括包含二氧化硅(SiO2)的键合辅助层350。将具有SiO2键合辅助层350的硅衬底322与半导体结构340的表面332``(图3E)紧密接触。在SiO2键合辅助层350和介电层330的键合表面332``之间形成键合界面352。
由于这些实施方式仅是本发明实施方式的示例,所以以上描述的本发明的实施方式并不限制本发明的范围,本发明的范围由所附的权利要求及其法律上的等同物限定。任何等同实施方式均旨在位于本发明的范围内。事实上,根据说明书,除了这些在此示出和描述的,诸如所描述的要素的替选的有用组合的对本发明的各种修改对于本领域技术人员而言将是明显的。这些修改也旨在落入所附的权利要求的范围内。此处所用的标题和图例仅是为了清楚和方便。
Claims (21)
1.一种用于形成半导体结构的方法,所述方法包括以下步骤:
在已处理半导体结构的非平坦表面上方形成介电层,所述非平坦表面包括多个导电区和多个非导电区,所述已处理半导体结构的非平坦表面通过去除所述多个导电区的一部分以露出多个导电区的处理而形成;
在所述介电层上方形成掩蔽层,并且设置延伸穿过直接位于所述已处理半导体结构的所述非平坦表面的所述多个导电区中的至少一些导电区上方的所述掩蔽层的多个掩蔽开口;
对所述介电层的与所述已处理半导体结构的所述非平坦表面相反的一侧上的表面进行平坦化以形成平坦化表面,其中,对所述介电层的表面进行平坦化的步骤包括:
蚀刻通过延伸穿过所述掩蔽层的所述多个掩蔽开口暴露的所述介电层的区域,以及
在蚀刻所述介电层的所述区域之后对所述介电层的所述表面进行抛光;以及
将半导体结构附接到所述介电层的所述平坦化表面。
2.根据权利要求1所述的方法,其中,形成所述掩蔽层的步骤还包括:将所述多个掩蔽开口构图为至少对应于所述已处理半导体结构的所述非平坦表面的所述多个导电区的图案。
3.根据权利要求1所述的方法,所述方法还包括:对所述已处理半导体结构的表面进行抛光以形成所述已处理半导体结构的所述非平坦表面。
4.根据权利要求1所述的方法,其中,形成所述介电层的步骤还包括:在所述已处理半导体结构的所述非平坦表面上方沉积一层或多层硅氧化物、硅氮化物及其混合物中的至少一种。
5.根据权利要求1到4中任意一项所述的方法,其中,形成所述介电层的步骤还包括:
在所述已处理半导体结构的所述非平坦表面上方设置第一介电材料;
在所述第一介电材料上方设置蚀刻停止层;以及
在所述蚀刻停止层上方设置第二介电材料,使得所述蚀刻停止层位于所述第一介电材料层和第二介电材料层之间。
6.根据权利要求5所述的方法,其中,对通过所述多个掩蔽开口暴露的所述介电层的区域进行蚀刻的步骤还包括:
选择性地蚀刻所述第二介电材料的暴露部分,并且暴露所述蚀刻停止层的多个部分;以及
选择性地蚀刻所述蚀刻停止层的暴露部分,并且暴露所述第一介电材料的多个部分。
7.根据权利要求5所述的方法,其中,对所述介电层进行平坦化以形成所述平坦化表面的步骤还包括:
抛光穿过所述第二介电材料的剩余部分,并且暴露所述蚀刻停止层的剩余部分;以及
选择性地蚀刻所述蚀刻停止层的所述剩余部分。
8.根据权利要求5所述的方法,其中,对所述介电层的表面进行抛光的步骤包括对所述第一介电材料的表面进行抛光。
9.根据权利要求1到4中任意一项所述的方法,其中,形成所述介电层的步骤包括在低于400℃的温度使用等离子辅助化学气相沉积处理来沉积所述介电层。
10.根据权利要求1到4中任意一项所述的方法,其中,形成所述介电层的步骤还包括将所述介电层选择为具有大于所述已处理半导体结构的所述非平坦表面的最大峰谷值的平均层厚度。
11.根据权利要求1到4中任意一项所述的方法,其中,对所述介电层的区域进行蚀刻的步骤包括使用等离子蚀刻处理来蚀刻所述介电层的所述区域。
12.根据权利要求1到4中任意一项所述的方法,其中,对所述介电层的所述表面进行抛光的步骤包括对所述介电层的所述表面进行化学机械抛光。
13.根据权利要求1到4中任意一项所述的方法,其中,将半导体结构附接到所述介电层的所述平坦化表面的步骤还包括将所述半导体结构直接分子键合到所述介电层的所述平坦化表面。
14.一种半导体结构,所述半导体结构包括:
覆盖在已处理半导体结构的非平坦表面上方的介电层,所述非平坦表面包括多个导电区和多个非导电区,并且所述已处理半导体结构的非平坦表面通过去除所述多个导电区的一部分以露出多个导电区的处理而形成,以及
覆盖在所述介电层上的掩蔽层,所述掩蔽层包括延伸穿过直接位于所述非平坦表面的所述导电区中的至少一些导电区的上方的所述掩蔽层的多个掩蔽开口。
15.根据权利要求14所述的半导体结构,其中,所述介电层包括三层或者更多层介电材料,所述介电材料包括第一介电材料、蚀刻停止层和第二介电材料。
16.根据权利要求15所述的半导体结构,其中,所述蚀刻停止层被布置在所述第一介电材料和所述第二介电材料之间。
17.根据权利要求15所述的半导体结构,其中,所述蚀刻停止层包括硅氮化物,所述第一介电材料和所述第二介电材料包括硅氧化物。
18.根据权利要求15所述的半导体结构,其中,所述第一介电材料具有大于所述已处理半导体结构的所述非平坦表面的最大峰谷距离的平均厚度。
19.根据权利要求14到18中任意一项所述的半导体结构,其中,所述已处理半导体结构包括多个半导体器件,所述多个半导体器件包括电子器件。
20.根据权利要求19所述的半导体结构,其中,所述电子器件包括光电子器件和微电子机械器件中的一种或更多种。
21.根据权利要求14到18中任意一项所述的半导体结构,其中,所述介电层具有大于所述已处理半导体结构的所述非平坦表面的最大峰谷距离的平均厚度。
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