CN102842547A - 用于改善布线和减小封装应力的接合焊盘设计 - Google Patents
用于改善布线和减小封装应力的接合焊盘设计 Download PDFInfo
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Abstract
接合焊盘设计包括:多个接合焊盘,位于半导体芯片上方;和多个凸块下金属(UBM)层,形成在多个接合焊盘的相应接合焊盘的上方。接合焊盘中的至少一个具有包括伸长部和收缩部的伸长形状,伸长部大体上沿着从芯片的中心辐射到外围的应力方向定向。本发明公开了用于改善布线和减小封装应力的接合焊盘设计。
Description
技术领域
本发明大体上涉及半导体封装,更具体地来说,涉及改善布线和减小封装应力的接合焊盘设计。
背景技术
现在,晶圆级芯片封装(WLCSP)由于其低成本和相对简单的工艺而被广泛使用。在典型的WLCSP中,在金属化层上形成互连结构,然后形成凸块下金属(UBM),并且安装焊料球。图1为发明人已知的和用在WLCSP中的互连结构的横截面图。芯片(或者晶圆)20包括衬底30,在该衬底上形成有源电路32。互连结构40包括:多个金属化层,该金属化层具有金属线和通孔(未示出)。金属化层包括顶部介电层,在该顶部介电层中形成金属焊盘52。金属焊盘52可以通过通孔48、布线或者重新分布层(RDL)46电连接至接合焊盘38。在衬底30的上方,并且也在互连结构40的上方形成钝化层34和36。在钝化层34的上方形成接合焊盘38,并且UBM层41与接合焊盘38接触。在UBM层41的上方形成凸块球42,并且该凸块球电连接至并且可能与UBM层41接触。接合焊盘38具有水平尺寸L1,在与衬底的前面(在图1中面朝上的表面)平行的平面上测量该水平尺寸。UBM层41具有尺寸L2,在与水平尺寸L1的方向相同的方向上测量该尺寸。为了降低在芯片20中的翘曲并且因此产生的分层的不利影响,接合焊盘38的尺寸L1通常大于UBM层41的尺寸L2。在图2中示出了图1中所示的结构的接合焊盘设计22的俯视图。
因为其尺寸,接合焊盘38占用了芯片表面的相当大的比例。因为接合焊盘38具有圆形,并且具有越来越高的半导体器件的密度,圆形接合焊盘38的尺寸可能限定布线或者用于布线的RDL 46的数量。如果在每一给定区域上的布线太多,则存在桥接或导致短路的危险。
通过减小圆形接合焊盘38的尺寸,设计者可以将在相邻接合焊盘38之间的更大间距提供用于布线。图3示出了接合焊盘设计22的实例,其中,接合焊盘38的尺寸L1小于UBM层41的尺寸L2。与在图2中所示的设计相比较,这种设计允许有在相邻接合焊盘38之间的额外布线。然而,具有这种设计的芯片易于由翘曲和/或热循环应力导致的分层。可以通过接合焊盘38将应力传递给互连结构40,潜在导致低k介电层在互连结构40中分层。当接合焊盘38的尺寸减小时,因为减小了用于UBM层41的支撑,所以将更大的应力传递给互连结构40;因此生成的封装件的可靠性下降。分层在芯片20的角部15处尤其严重。为了减小分层的危险,接合焊盘38的尺寸L1通常大于UBM层41的尺寸L2的预定数量。
由于阅读以下详细描述时显而易见的这些原因和其他原因,需要提供额外布线同时减小封装应力的改善的接合焊盘设计。
发明内容
为了解决现有技术所存在的问题,根据本发明的一个方面,提供了一种接合焊盘设计,包括:多个接合焊盘,所述多个接合焊盘位于半导体芯片的上方,其中,所述接合焊盘中的至少一个具有伸长形状,该伸长形状具有伸长部和收缩部,所述伸长部大体上沿着从所述芯片的中心向所述芯片的外围辐射的应力方向定向;以及多个凸块下金属(UBM)层,所述多个凸块下金属层被形成在所述多个接合焊盘的相应接合焊盘的上方。
所述接合焊盘设计进一步包括:一条或多条布线,所述一条或多条布线位于任意两个相邻接合焊盘之间的间隙中。
在所述接合焊盘设计中,所述多个接合焊盘中的至少一个具有伸长的圆形;或者所述接合焊盘中的至少一个具有伸长的椭圆形;或者所述多个UBM层中的至少一个的直径大于所述多个接合焊盘中的一个的所述收缩部的长度;或者所述多个UBM层中的至少一个的直径小于所述多个接合焊盘中的一个的所述伸长部的长度。
在所述的接合焊盘设计中,所述多个接合焊盘中的至少一个具有伸长部,以相对于所述芯片的角部呈基本上45度夹角定向,并且至少一个接合焊盘具有伸长部,以相对于所述芯片的边缘呈基本上90度夹角定向。
根据本发明的另一方面,提供了一种接合焊盘结构,包括:一个或多个接合焊盘,所述一个或多个接合焊盘位于半导体器件的上方,其中,所述接合焊盘具有包括较窄部分和较宽部分的伸长的椭圆形,所述较宽部分大体上与应力方向平行,所述应力方向从所述半导体器件的中心向外辐射;以及一个或多个凸块下金属(UBM)层,所述一个或多个凸块下金属层形成在所述一个或多个接合焊盘的相应接合焊盘上。
所述的接合焊盘结构进一步包括:一条或多条布线,所述一条或多条布线位于任意两个相邻接合焊盘之间的间隙中。
在所述的接合焊盘结构中,所述UBM层之一的直径大于所述接合焊盘之一的所述较窄部分的长度;或者所述UBM层之一的直径小于所述接合焊盘之一的所述较宽部分的长度;或者以相对于所述半导体器件的角部呈约45度定位所述一个或多个接合焊盘之一的所述伸长部;或者以相对于所述半导体器件的边部呈约90度定位所述一个或多个接合焊盘之一的所述伸长部。
根据本发明的又一方面,提供了一种接合焊盘设计,包括:多个接合焊盘和多个UBM层,所述多个接合焊盘和多个UBM层以所述接合焊盘具有包括伸长部和收缩部的形状的方式分别形成在芯片的表面上,并且其中,所述接合焊盘被配置为从所述芯片的中心向外延伸至所述芯片的外围的阵列。
所述的接合焊盘设计进一步包括:一条或多条布线,所述一条或多条布线位于任意两个相邻接合焊盘之间的间隙中。
在所述的接合焊盘设计中,所述接合焊盘沿着应力方向被配置在所述芯片中;或者所述接合焊盘具有椭圆形,所述接合焊盘具有伸长的椭圆形;或者所述UBM层之一的直径大于所述接合焊盘之一的所述收缩部;或者所述UBM层之一的直径小于所述接合焊盘之一的所述伸长部。
附图说明
通过以下详细描述、所附权利要求、以及附图可以使本发明的特征、各个方面、和优点变得更加显而易见。
图1为示出在半导体制造的阶段过程中的芯片(或晶圆)的横截面图。
图2为图1的芯片的接合焊盘设计的俯视图,其中,接合焊盘的尺寸大于UBM的尺寸。
图3为图1的芯片的接合焊盘设计的俯视图,其中,接合焊盘的尺寸小于UBM的尺寸。
图4为根据本发明的一个实施例的接合焊盘设计的俯视图。
图5为根据本发明的另一个实施例的接合焊盘设计的俯视图。
具体实施方式
在以下描述中,许多特定的细节被阐述用于提供对本发明实施例的全面理解。然而,本领域的普通技术人员应意识到没有这些特定的细节也可实施本发明的实施例。在一些实例中,没有详细描述公知的结构和工艺,从而避免了使本发明的实施例不必要地变得模糊。
整个说明书中所提及的“一个实施例”或“某个实施例”指的是本发明的至少一个实施例包括关于实施例所描述的特定部件、结构或特征。因此,在整个本说明书的各个位置出现的短语“在一个实施中”或“在某个实施例中”不一定指同一个实施例。而且,在一个或多个实施例中可以以任何合适的方式组合特定部件、结构或特征。应当理解,以下附图没有按比例绘制,这些附图只是为了说明的目的。
图4为根据本发明的一个实施例的接合焊盘设计24的俯视图。接合焊盘设计24包括:多个接合焊盘39,位于半导体芯片或晶圆20的上方。在多个接合焊盘39的各个接合焊盘上形成多个UBM层41。应该注意到,图4和图5仅示出了具有接合焊盘设计的相应UBM层41的16个接合焊盘,该接合焊盘设计可以包括具有相应UBM层的几百个这种接合焊盘。仅是为了清晰示出本发明的各种实施例的各个方面而限定本文所示的接合焊盘数量和UBM层。本发明不仅限于任何特定数量的接合焊盘或UBM层。
接合焊盘39具有通常伸长的形状,该形状具有如测量为长度L的较宽部或者伸长部以及如测量为宽度W的较窄部或收缩部。根据本发明的一个实施例,UBM层41的直径大于结合焊盘39的宽度W。根据另一实施例,UBM层41的直径小于接合焊盘39的长度L。在本发明的其他实施例中,多个接合焊盘39中的每个具有伸长的圆形。在又一实施例中,多个接合焊盘39中的每个具有伸长的椭圆形。然而,应该理解,只要每种形状具有伸长部和收缩部,接合焊盘39就可以具有任何多种形状。
根据本发明的方面,通过非圆形的形状,接合焊盘39的较窄部或收缩部提供了位于相邻接合焊盘39之间的更大间距,从而允许在钝化层36中的相邻接合焊盘39之间的更多布线或RDL 46。提供更多布线的这种设计尤其可应用于更高密度的半导体器件。
当接合焊盘的尺寸显著地影响倒装芯片封装件的可靠性时,根据本发明的另一方面,较宽部或伸长部为下层UBM层41提供更大支撑,使封装件不易由于翘曲和/或热循环应力所导致的分层。例如,在将芯片20接合至封装衬底(未示出)以后,由于在芯片20的热膨胀系数(CTE)和封装衬底的CTE之间的偏差而生成应力。虽然接合焊盘39具有较窄部,但是通过增大提供伸长部的接合焊盘39的尺寸,将更小的应力传递给互连结构40,因此,改善了生成的封装件的可靠性。
明显地,在芯片20的外围或者角部15处,分层问题尤其严重,因为角部15比芯片的其他地方(例如在中心处)经受更大的应力。至少由于这种原因,根据本发明的另一方面,接合焊盘39具有大体上沿着应力方向60定向的接合焊盘的伸长部,该应力方向从芯片20的中心部辐射到芯片的外围或角部15。通过大体上沿着应力方向60定向伸长部,接合焊盘设计24的实施例更好更有效地解决了分层问题,因为伸长部提供了每单位接合焊盘的更大的线性覆盖,同时提高了接合焊盘39的应力分布特征。
如图5所示,具有沿着应力方向60定向的接合焊盘的伸长部的接合焊盘39被配置为阵列,应力方向从芯片20的中心至向外延伸芯片的外围。根据一些实施例,多个接合焊盘39中的一个或多个具有接合焊盘的伸长部,该接合焊盘的伸长部沿着应力方向60定向,将该应力方向相对于芯片20角部为夹角62。根据一些实施例,夹角62相对于芯片20的角部具有基本上45度夹角。根据其他实施例,多个接合焊盘39中的一个或多个具有沿着应力方向60定向的接合焊盘的伸长部,并且相对于芯片20的角部15具有基本上90度夹角,将该90度夹角标示为夹角64。
根据本发明的一个实施例,接合焊盘设计包括:多个接合焊盘,位于半导体芯片上;和多个凸块下金属(UBM)层,被形成在多个接合焊盘的相应接合焊盘上,其中,接合焊盘中的至少一个具有伸长形状,该伸长形状具有伸长部和收缩部,该伸长部大体上沿着从芯片的中心辐射至芯片的外围的应力方向定向。
根据本发明的另一实施例,接合焊盘结构包括:一个或多个接合焊盘,位于半导体器件上方;和一个或多个凸块下金属(UBM)层,被形成在一个或多个接合焊盘的相应接合焊盘的上方,其中,接合焊盘具有伸长的椭圆形,该伸长的椭圆形具有较窄部分和较宽部分,较宽部分大体上与从半导体器件的中心向外辐射的应力方向平行。
根据本发明的又一实施例,接合焊盘设计包括:多个接合焊盘和多个UBM层,分别以接合焊盘具有包括伸长部和收缩部的形状方式被形成在芯片的表面上,并且其中,将接合焊盘配置为阵列,该阵列从芯片中心向外延伸至芯片的外围。
本发明的实施例具有几个优点。接合焊盘的较窄部或收缩部提供了相邻接合焊盘之间的更大间距,从而允许焊盘之间更多的布线。此外,通过沿着应力方向对准接合焊盘的伸长部,低k介电层享有更大保护而防止分层,因为更小的应力传递给互连结构,因此改善了倒装芯片封装件的可靠性。此外,除了需要修改一种掩模以外,不需要额外的光刻步骤。
在以上详细的描述中,已经描述了特定的示例性实施例。然而,显而易见地,在不背离本发明的宽泛主旨和范围的情况下,本领域中的普通技术人员可以做各种更改、结构、工艺和改变。因此,说明书和附图是为了说明而不用于限定的目的。应该理解,本发明的实施例可以使用各种其它组合和环境且可以在本权利要求书的范围内进行改变和更改。
Claims (10)
1.一种接合焊盘设计,包括:
多个接合焊盘,所述多个接合焊盘位于半导体芯片的上方,其中,所述接合焊盘中的至少一个具有伸长形状,该伸长形状具有伸长部和收缩部,所述伸长部大体上沿着从所述芯片的中心向所述芯片的外围辐射的应力方向定向;以及
多个凸块下金属(UBM)层,所述多个凸块下金属层被形成在所述多个接合焊盘的相应接合焊盘的上方。
2.根据权利要求1所述的接合焊盘设计,进一步包括:一条或多条布线,所述一条或多条布线位于任意两个相邻接合焊盘之间的间隙中。
3.根据权利要求1所述的接合焊盘设计,其中,所述多个UBM层中的至少一个的直径大于所述多个接合焊盘中的一个的所述收缩部的长度。
4.根据权利要求1所述的接合焊盘设计,其中,所述多个UBM层中的至少一个的直径小于所述多个接合焊盘中的一个的所述伸长部的长度。
5.根据权利要求1所述的接合焊盘设计,其中,所述多个接合焊盘中的至少一个具有伸长部,以相对于所述芯片的角部呈基本上45度夹角定向,并且至少一个接合焊盘具有伸长部,以相对于所述芯片的边缘呈基本上90度夹角定向。
6.一种接合焊盘结构,包括:
一个或多个接合焊盘,所述一个或多个接合焊盘位于半导体器件的上方,其中,所述接合焊盘具有包括较窄部分和较宽部分的伸长的椭圆形,所述较宽部分大体上与应力方向平行,所述应力方向从所述半导体器件的中心向外辐射;以及
一个或多个凸块下金属(UBM)层,所述一个或多个凸块下金属层形成在所述一个或多个接合焊盘的相应接合焊盘上。
7.根据权利要求6所述的接合焊盘结构,进一步包括:一条或多条布线,所述一条或多条布线位于任意两个相邻接合焊盘之间的间隙中。
8.根据权利要求6所述的接合焊盘结构,其中,所述UBM层之一的直径大于所述接合焊盘之一的所述较窄部分的长度。
9.根据权利要求6所述的接合焊盘结构,其中,所述UBM层之一的直径小于所述接合焊盘之一的所述较宽部分的长度。
10.一种接合焊盘设计,包括:
多个接合焊盘和多个UBM层,所述多个接合焊盘和多个UBM层以所述接合焊盘具有包括伸长部和收缩部的形状的方式分别形成在芯片的表面上,并且其中,所述接合焊盘被配置为从所述芯片的中心向外延伸至所述芯片的外围的阵列;以及
一条或多条布线,所述一条或多条布线位于任意两个相邻接合焊盘之间的间隙中。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106971945A (zh) * | 2016-01-14 | 2017-07-21 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN114400214A (zh) * | 2022-01-07 | 2022-04-26 | 广东气派科技有限公司 | 一种改善Flip chip晶圆电路层裂纹的方法 |
Families Citing this family (2)
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---|---|---|---|---|
KR20170045553A (ko) * | 2015-10-19 | 2017-04-27 | 에스케이하이닉스 주식회사 | 재배선 라인을 구비하는 반도체 장치 |
US9991189B2 (en) | 2016-07-29 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a dual material redistribution line |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040099936A1 (en) * | 1999-11-10 | 2004-05-27 | Caletka David V. | Partially captured oriented interconnections for BGA packages and a method of forming the interconnections |
CN1926674A (zh) * | 2003-07-31 | 2007-03-07 | 飞思卡尔半导体公司 | 具有减小应力的凸起设计的半导体器件 |
US20080185735A1 (en) * | 2007-02-02 | 2008-08-07 | Freescale Semiconductor, Inc. | Dynamic pad size to reduce solder fatigue |
US20110031618A1 (en) * | 2009-08-07 | 2011-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond Pad Design for Reducing the Effect of Package Stress |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5859474A (en) * | 1997-04-23 | 1999-01-12 | Lsi Logic Corporation | Reflow ball grid array assembly |
US6118180A (en) * | 1997-11-03 | 2000-09-12 | Lsi Logic Corporation | Semiconductor die metal layout for flip chip packaging |
JP2001217355A (ja) * | 1999-11-25 | 2001-08-10 | Hitachi Ltd | 半導体装置 |
US6518675B2 (en) * | 2000-12-29 | 2003-02-11 | Samsung Electronics Co., Ltd. | Wafer level package and method for manufacturing the same |
DE102005009358B4 (de) * | 2005-03-01 | 2021-02-04 | Snaptrack, Inc. | Lötfähiger Kontakt und ein Verfahren zur Herstellung |
US7841508B2 (en) * | 2007-03-05 | 2010-11-30 | International Business Machines Corporation | Elliptic C4 with optimal orientation for enhanced reliability in electronic packages |
-
2011
- 2011-06-24 US US13/167,906 patent/US9053943B2/en active Active
- 2011-10-25 CN CN201110332275.1A patent/CN102842547B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040099936A1 (en) * | 1999-11-10 | 2004-05-27 | Caletka David V. | Partially captured oriented interconnections for BGA packages and a method of forming the interconnections |
CN1926674A (zh) * | 2003-07-31 | 2007-03-07 | 飞思卡尔半导体公司 | 具有减小应力的凸起设计的半导体器件 |
US20080185735A1 (en) * | 2007-02-02 | 2008-08-07 | Freescale Semiconductor, Inc. | Dynamic pad size to reduce solder fatigue |
US20110031618A1 (en) * | 2009-08-07 | 2011-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bond Pad Design for Reducing the Effect of Package Stress |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106971945A (zh) * | 2016-01-14 | 2017-07-21 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
CN114400214A (zh) * | 2022-01-07 | 2022-04-26 | 广东气派科技有限公司 | 一种改善Flip chip晶圆电路层裂纹的方法 |
CN114400214B (zh) * | 2022-01-07 | 2023-02-10 | 广东气派科技有限公司 | 一种改善Flip chip晶圆电路层裂纹的方法 |
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