CN102779919B - Semiconductor encapsulation structure - Google Patents
Semiconductor encapsulation structure Download PDFInfo
- Publication number
- CN102779919B CN102779919B CN201110122501.3A CN201110122501A CN102779919B CN 102779919 B CN102779919 B CN 102779919B CN 201110122501 A CN201110122501 A CN 201110122501A CN 102779919 B CN102779919 B CN 102779919B
- Authority
- CN
- China
- Prior art keywords
- electrode
- adhesive layer
- conductive adhesive
- reflector
- semiconductor package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Led Device Packages (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor encapsulation structure, which comprises a base plate, at least one semiconductor crystal particle, one conducting glue layer and a fluorescence layer, wherein the base plate comprises a first electrode, a second electrode and a reflection layer, the reflection layer is arranged on the first electrode and the second electrode, the conducting glue layer is arranged inside the reflecting layer and covers the first electrode and the second electrode, the semiconductor crystal particle is fixedly arranged on the first electrode and the second electrode through the conducting glue layer and forms the electric connection, and the fluorescence layer is arranged on the conducting glue layer and covers the semiconductor crystal particle. The invention provides a manufacture process for manufacturing the semiconductor encapsulation structure.
Description
Technical field
The present invention relates to a kind of semiconductor package, particularly relate to a kind of semiconductor package with better adaptation.
Background technology
The LED industry of semiconductor packages is one of industry attracted most attention in recent years, is developed so far, and LED product has had energy-conservation, power saving, high efficiency, the reaction time is fast, the life cycle time is long and not mercurous, have the advantages such as environmental benefit.But because the semiconductor package of LED is in order to increase luminous efficiency, there is a reflector and arrange.Described reflector mainly around described semiconductor grain (i.e. described LED chip), is reflected with the light sent described semiconductor grain, produces the effect concentrating light to increase luminosity.But; the electrode contact that the position that described reflector is arranged can be electrically connected with described semiconductor grain; described electrode is metal material; and described reflector is plastic material; tack between these two kinds of materials is not good; therefore interface between often has aqueous vapor and infiltrates, thus causes the afunction of described semiconductor grain.So how to avoid aqueous vapor to infiltrate, improving the adaptation of described semiconductor package, is the problem that current semiconductor packaging industry is made great efforts.
Summary of the invention
In view of this, the semiconductor package providing a kind of adaptation good is necessary.
A kind of semiconductor package, comprises a substrate, at least one semiconductor grain, a conductive adhesive layer and a fluorescence coating.Described substrate includes first electrode, second electrode and a reflector, and described reflector is arranged on first and second electrode described.It is inner that described conductive adhesive layer is arranged on described reflector, and cover first and second electrode described.Described semiconductor grain to be fixed on first and second electrode described by described conductive adhesive layer and to form electric connection.Described fluorescence coating to be arranged on described conductive adhesive layer and to cover described semiconductor grain.
A kind of semiconductor package processing procedure, it comprises the following steps,
A substrate is provided, first electrode and second electrode is set on the substrate, and a reflector is set on first and second electrode described;
Form a conductive adhesive layer, inner in described reflector, and cover first and second electrode described;
At least one semiconductor grain is set, on described conductive adhesive layer, and first and second electrode described in two electrode contact correspondences that described semiconductor grain is had;
A hot pressing die is provided, hot pressing is carried out to described semiconductor grain and described conductive adhesive layer, described semiconductor grain and first and second electrode described are electrically connected; And
Form a fluorescence coating, on described conductive adhesive layer, and cover described semiconductor grain.
In above-mentioned semiconductor package and processing procedure, fix because described semiconductor grain is directly pasted with the hot pressing of described conductive adhesive layer and described two electrodes and reach electric connection, the adaptation of described conductive adhesive layer is high, aqueous vapor effectively can be avoided to infiltrate the electrical connection part of described semiconductor grain and described two electrodes, thus effectively improve air-tightness and the water proofing property of described semiconductor package.The electric connection of especially described semiconductor grain and described two electrodes does not need routing, has the effect reducing described semiconductor package height, is conducive to the Miniaturization Design of product.
Accompanying drawing explanation
Fig. 1 is the cutaway view that semiconductor package of the present invention real first executes mode.
Fig. 2 is the cutaway view that semiconductor package of the present invention real second executes mode.
Fig. 3 is the flow chart of steps of semiconductor package processing procedure of the present invention.
Fig. 4 is the cutaway view that corresponding diagram 3 arranges at least one semiconductor grain step.
Fig. 5 is the cutaway view that corresponding diagram 3 provides first of a hot pressing die step to execute mode.
Fig. 6 is the cutaway view that corresponding diagram 3 provides second of a hot pressing die step to execute mode.
Main element symbol description
| Encapsulating structure | 10、20 |
| Substrate | 12、22 |
| First electrode | 122、222 |
| End face | 1222、1242 |
| Second electrode | 124、224 |
| Reflector | 126、226 |
| Semiconductor grain | 14、24 |
| Electrode contact | 142 |
| Conductive adhesive layer | 16、26 |
| Fluorescence coating | 18、28 |
| Resistance hurdle layer | 228 |
| Hot pressing die | 3 |
| Bed die | 32 |
| Internal mold | 34 |
| Die cavity | 342 |
| Depression | 344 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Do one below in conjunction with accompanying drawing to the present invention specifically to introduce.
Refer to Fig. 1, be depicted as the cutaway view of semiconductor package first execution mode of the present invention, described encapsulating structure 10, comprise a substrate 12, at least one semiconductor grain 14, conductive adhesive layer 16 and a fluorescence coating 18.Described substrate 12 comprises first electrode 122, second electrode 124 and a reflector 126.Described first electrode 122 is symmetrical set with described second electrode 124, and has an end face 1222,1242 respectively, and described reflector 126 is arranged on the end face 1222,1242 of first and second electrode 122,124 described.The material in described reflector 126 can be reflecting material or high molecular material, such as, and PPA (Polyphthalamide) plastics or epoxide resin material.Inside, described reflector 126 arranges described conductive adhesive layer 16, and described conductive adhesive layer 16 covers on first and second electrode 1222,1242 described.Described conductive adhesive layer 16 is anisotropic conductive (ACAs, Anisotropic Conductive Adhesives), above can conduct electricity in a direction (Z-direction as vertical), and upper non-conductive in other direction (X, Y-direction as level).Described semiconductor grain 14 is arranged on described conductive adhesive layer 16, described semiconductor grain 14 has two electrode contacts (pad) 142 of opposed polarity, described two electrode contacts 142 are positioned on the conducting direction of described conductive adhesive layer 16, and corresponding first and second electrode 122,124 described of difference, thus make described semiconductor grain 14 fix its position by described conductive adhesive layer 16, and be electrically connected with described first electrode 122 and described second electrode 124 respectively.Owing to including epoxy resin (epoxy) or silicon Li Kang (silicon) composition in the material of described conductive adhesive layer 16, high with first and second electrode 122,124 adaptation described in metal material, thus can prevent aqueous vapor from infiltrating the electrical connection part of described semiconductor grain 14, improve air-tightness and the water proofing property of described encapsulating structure 10, safeguard its good effective utilization.Described semiconductor grain 14 is light-emitting diode (LED, Light Emitting Diode).Described fluorescence coating 18 is arranged on described conductive adhesive layer 16, and covers described semiconductor grain 14.Described fluorescence coating 18 can comprise at least one fluorescent material, and the material of described fluorescence coating 18 is epoxy resin (epoxy) or silicon Li Kang (silicon).
Referring again to Fig. 2, be depicted as the cutaway view of semiconductor package second execution mode of the present invention, described encapsulating structure 20, comprise a substrate 22, at least one semiconductor grain 24, conductive adhesive layer 26 and a fluorescence coating 28.Described substrate 22 comprises first electrode 222, second electrode 224 and a reflector 226.The essential structure of described encapsulating structure 20 is identical with described encapsulating structure 10, therefore repeats no more.Difference is, inside, described reflector 226 arranges described conductive adhesive layer 26, and described conductive adhesive layer 26, at the joining place of described reflector 226 and described first electrode 222 and the second electrode 224, is formed and has at least one resistance hurdle layer 228.Described resistance hurdle layer 228 can hinder the first electrode 222 described in hurdle and the infiltration of aqueous vapor between the second electrode 224 and described reflector 226 really.Described encapsulating structure 20 has the setting of described resistance hurdle layer 228, forms the encapsulating structure that adaptation is high, effectively can extend the useful life of described encapsulating structure 20.
Referring again to Fig. 3, be depicted as the flow chart of steps of semiconductor package processing procedure of the present invention, it comprises the following steps:
S11 provides a substrate, arranges first electrode and second electrode on the substrate, and arrange a reflector on first and second electrode described;
S12 forms a conductive adhesive layer, inner in described reflector, and covers first and second electrode described;
S13 arranges at least one semiconductor grain, on described conductive adhesive layer, and first and second electrode described in two electrode contact correspondences that described semiconductor grain is had;
S14 provides a hot pressing die, carries out hot pressing to described semiconductor grain and described conductive adhesive layer, and described semiconductor grain and first and second electrode described are electrically connected; And
S15 forms a fluorescence coating, on described conductive adhesive layer, and covers described semiconductor grain.
Described step S11 provides a substrate 12, described substrate 12 arranges first electrode 122 and second electrode 124, and a reflector 126 is set on first and second electrode 122,124 described, as shown in Figure 4, described reflector 126 is shaping in mould model (Molding) mode, the material in described reflector 126 can identical with the material that described substrate 12 uses time, make described reflector 126 can be one-body molded with described substrate 12.
Then carry out described step S12 and form a conductive adhesive layer 16, inner in described reflector 126, and cover first and second electrode 122,124 described, described conductive adhesive layer 16 fills up the bottom surface of inside, described reflector 126 with liquid or adhesive tape kenel.Described conductive adhesive layer 16 is anisotropic conductive, has conductivity in the direction on vertically described first electrode 122 and the second electrode 124 surface.
Then carry out described step S13 and at least one semiconductor grain 14 is set, on described conductive adhesive layer 16, and corresponding first and second electrode 122,124 described of two electrode contacts 142 that described semiconductor grain 14 is had, described two electrode contacts 142 have different polarity, respectively the corresponding vertical direction on described first electrode 122 and the second electrode 124 surface.
Carry out described step S14 again and a hot pressing die 3 is provided, hot pressing is carried out to described semiconductor grain 14 and described conductive adhesive layer 16, and described semiconductor grain 14 is electrically connected with first and second electrode 122,124 described, as shown in Figure 5, described hot pressing die 3 comprises a bed die 32 and an internal mold 34, described bed die 32 is arranged at the bottom of described substrate 12, the space of inside, described internal mold 34 corresponding described reflector 126, makes described hot pressing die 3 can carry out hot pressing to described semiconductor grain 14 and described conductive adhesive layer 16.The inner surface of described internal mold 34 has a die cavity 342, the external form of the corresponding described semiconductor grain 14 of described die cavity 342, when described hot pressing die 3 carries out hot pressing, described die cavity 342 orders about described semiconductor grain 14 and fits with first and second electrode 122,124 described.When described semiconductor grain 14 and first and second electrode 122,124 described are fitted, described two electrode contacts 142 respectively with the surface contact of first and second electrode 122,124 described.Hot pressing is carried out in described hot pressing die 3 heating, described conductive adhesive layer 16 will solidify, thus make described semiconductor grain 14 firm with the contact of first and second electrode 122,124 described, described two electrode contacts 142 also because the surface of vertically contact first and second electrode 122,124 described, and reach electric connection.After described hot pressing die 3 hot pressing completes, directly can remove described hot pressing die 3, make described conductive adhesive layer 16 top of inside, described reflector 126 leave accommodation space.
Described step S14 provides a hot pressing die 3, the described internal mold 34 of described hot pressing die 3, in the outer peripheral edges of described internal mold 34, there is a depression 344 further, described depression 344 is when described hot pressing die 3 carries out hot pressing, make described conductive adhesive layer 26 at the joining place of described reflector 226 and described first electrode 222 and the second electrode 224, formed and there is at least one resistance hurdle layer 228 (as shown in Figure 6).
Finally, described step S15 forms a fluorescence coating 18, on described conductive adhesive layer 16,26, and covers described semiconductor grain 14,24.Described fluorescence coating 18 is shaping in ejection formation (Injection Molding) mode.
To sum up, semiconductor package of the present invention, directly electric connection is reached in conjunction with described first electrode and the second electrode by described conductive adhesive layer at described semiconductor grain, not only can effectively prevent aqueous vapor from infiltrating described encapsulating structure, increase the adaptation of described encapsulating structure, the height of described encapsulating structure can be reduced simultaneously, be beneficial to Miniaturization Design.Semiconductor package processing procedure of the present invention, utilizes the hot pressing mode of described hot pressing die to manufacture, and facilitates the large amount of high adaptation encapsulating structure to manufacture.
In addition, those skilled in the art also can do other change in spirit of the present invention, and certainly, these changes done according to the present invention's spirit, all should be included within the present invention's scope required for protection.
Claims (12)
1. a semiconductor package, comprise a substrate, at least one semiconductor grain, a conductive adhesive layer and a fluorescence coating, described substrate includes first electrode, second electrode and a reflector, it is characterized in that: described reflector is arranged at described first, on two electrodes, it is inner that described conductive adhesive layer is arranged on described reflector, and cover described first, two electrodes, described semiconductor grain is fixed on described first by described conductive adhesive layer, two electrodes form electric connection, described fluorescence coating to be arranged on described conductive adhesive layer and to cover described semiconductor grain, wherein, the inner surface in described reflector is inclined plane, one stops layer is arranged on first, inclined plane on second electrode and bottom described reflector and between described conductive adhesive layer.
2. semiconductor package as claimed in claim 1, is characterized in that: described first electrode and described second electrode are symmetrical set, and have an end face respectively, and described end face arranges described reflector.
3. semiconductor package as claimed in claim 1, is characterized in that: the material in described reflector is high molecular material.
4. semiconductor package as claimed in claim 1, is characterized in that: described conductive adhesive layer is anisotropic conductive adhesive layer.
5. semiconductor package as claimed in claim 1, it is characterized in that: described semiconductor grain has two electrode contacts of opposed polarity, described two electrode contacts are positioned on the conducting direction of described conductive adhesive layer, and corresponding first and second electrode described of difference, described semiconductor grain is electrically connected by described conductive adhesive layer and first and second electrode described.
6. semiconductor package as claimed in claim 5, is characterized in that: described semiconductor grain is light-emitting diode.
7. semiconductor package as claimed in claim 1, it is characterized in that: described fluorescence coating comprises at least one fluorescent material, the material of described fluorescence coating is epoxy resin (epoxy) or silicon Li Kang (silicon).
8. a semiconductor package processing procedure, it comprises the following steps:
A substrate is provided, first electrode and second electrode is set on the substrate, and a reflector is set on first and second electrode described;
Form a conductive adhesive layer, inner in described reflector, and cover first and second electrode described;
At least one semiconductor grain is set, on described conductive adhesive layer, and first and second electrode described in two electrode contact correspondences that described semiconductor grain is had;
A hot pressing die is provided, hot pressing is carried out to described semiconductor grain and described conductive adhesive layer, described semiconductor grain and first and second electrode described are electrically connected, described hot pressing die comprises a bed die and an internal mold, described bed die is arranged at the bottom of described substrate, and the space of the corresponding inside, described reflector of described internal mold, the inner surface of described internal mold has a die cavity, the external form of the corresponding described semiconductor grain of described die cavity, the outer peripheral edges of described internal mold have a depression; And
Form a fluorescence coating, on described conductive adhesive layer, and cover described semiconductor grain.
9. semiconductor package processing procedure as claimed in claim 8, is characterized in that: described in provide in a substrate step, described reflector is shaping in mould model mode, or one-body molded with described substrate.
10. semiconductor package processing procedure as claimed in claim 8, it is characterized in that: described formation conductive adhesive layer step, described conductive adhesive layer fills up the bottom surface of inside, described reflector with liquid or adhesive tape kenel, and has conductivity in the direction of vertically described first electrode and the second electrode surface.
11. semiconductor package processing procedures as claimed in claim 8, it is characterized in that: described at least one semiconductor grain step is set, described two electrode contacts have different polarity, respectively the corresponding vertical direction at described first electrode and the second electrode surface.
12. semiconductor package processing procedures as claimed in claim 8, is characterized in that: described formation fluorescence coating step, described fluorescence coating is shaping with injection molding method.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110122501.3A CN102779919B (en) | 2011-05-12 | 2011-05-12 | Semiconductor encapsulation structure |
| TW100124133A TWI425676B (en) | 2011-05-12 | 2011-07-08 | Structure of the semiconductir package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110122501.3A CN102779919B (en) | 2011-05-12 | 2011-05-12 | Semiconductor encapsulation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102779919A CN102779919A (en) | 2012-11-14 |
| CN102779919B true CN102779919B (en) | 2015-07-08 |
Family
ID=47124770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110122501.3A Expired - Fee Related CN102779919B (en) | 2011-05-12 | 2011-05-12 | Semiconductor encapsulation structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102779919B (en) |
| TW (1) | TWI425676B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195757A (en) * | 2017-07-06 | 2017-09-22 | 庞绮琪 | A kind of LED encapsulation structure |
| CN107331751A (en) * | 2017-07-06 | 2017-11-07 | 庞绮琪 | The encapsulating structure of LED service lifes can be extended |
| CN110880544B (en) * | 2018-09-06 | 2021-09-03 | 深圳市斯迈得半导体有限公司 | Chip for glass substrate and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1925176A (en) * | 2005-09-02 | 2007-03-07 | 杨丕福 | Integrated light emitting device and method for making same |
| CN101295754A (en) * | 2007-04-26 | 2008-10-29 | 亿光电子工业股份有限公司 | Flip-chip soldering encapsulation structure and method for light emitting diode |
| CN101533886A (en) * | 2009-04-28 | 2009-09-16 | 友达光电股份有限公司 | A luminous module encapsulation method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW461123B (en) * | 2000-11-10 | 2001-10-21 | Ind Tech Res Inst | Flip-chip packaging method and structure for light emitting device |
| JP3679786B2 (en) * | 2002-06-25 | 2005-08-03 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
| TWI245437B (en) * | 2004-11-16 | 2005-12-11 | Lighthouse Technology Co Ltd | Package structure of a surface mount device light emitting diode |
| KR100601891B1 (en) * | 2005-08-04 | 2006-07-19 | 삼성전자주식회사 | Led package structure and manufacturing method |
| TW200717854A (en) * | 2005-10-27 | 2007-05-01 | Formosa Epitaxy Inc | Surface mount light emitting diode package |
| KR100845856B1 (en) * | 2006-12-21 | 2008-07-14 | 엘지전자 주식회사 | LED package and method of manufacturing the same |
| CN101488544B (en) * | 2008-01-18 | 2011-07-27 | 晶元光电股份有限公司 | Light emitting element and method for manufacturing the same |
-
2011
- 2011-05-12 CN CN201110122501.3A patent/CN102779919B/en not_active Expired - Fee Related
- 2011-07-08 TW TW100124133A patent/TWI425676B/en not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1925176A (en) * | 2005-09-02 | 2007-03-07 | 杨丕福 | Integrated light emitting device and method for making same |
| CN101295754A (en) * | 2007-04-26 | 2008-10-29 | 亿光电子工业股份有限公司 | Flip-chip soldering encapsulation structure and method for light emitting diode |
| CN101533886A (en) * | 2009-04-28 | 2009-09-16 | 友达光电股份有限公司 | A luminous module encapsulation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102779919A (en) | 2012-11-14 |
| TWI425676B (en) | 2014-02-01 |
| TW201246617A (en) | 2012-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100481546C (en) | Power LED with glue-filling formed bottom and manufacturing method thereof | |
| CN107994104B (en) | Semiconductor light emitting structure and semiconductor packaging structure | |
| US8569781B2 (en) | LED package with light-absorbing layer | |
| CN102072422A (en) | Packaging structure of high-power LED (light emitting diode) light source module | |
| CN102760816A (en) | LED (light emitting diode) packaging structure and manufacturing method thereof | |
| WO2008138183A1 (en) | Side emission type led | |
| CN104064662A (en) | Light-emitting-diode packaging structure | |
| CN102779919B (en) | Semiconductor encapsulation structure | |
| CN102769089B (en) | Semiconductor packaging structure | |
| CN206340542U (en) | A kind of QFN surface-adhered types RGB LED encapsulation modules | |
| CN103972372A (en) | LED encapsulation structure | |
| CN105845807A (en) | Flip chip package structure of light-emitting diode | |
| CN202977376U (en) | Sensor packaging module | |
| CN103000794B (en) | LED package structure | |
| CN208157452U (en) | A kind of flip LED luminescent device | |
| CN103295920A (en) | Noninsulated type power module and packaging process thereof | |
| CN206340568U (en) | A kind of QFN surface mounts RGB LED packages | |
| CN105070813A (en) | Large-power LED support and packaging method thereof | |
| CN104124320B (en) | Light emitting diode | |
| CN108735874B (en) | LED (light-emitting diode) integrally packaged by thermosetting packaging bracket and embedded communication IC (integrated circuit) and process thereof | |
| CN202948921U (en) | Non-insulated type power module | |
| TWI440225B (en) | Method for manufacturing light emitting diode | |
| EP3696853A1 (en) | Power semiconductor chip package structure | |
| TW201314976A (en) | Structure of the LED package | |
| CN203883038U (en) | Led packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150708 Termination date: 20160512 |