CN102779919A - Semiconductor encapsulation structure - Google Patents
Semiconductor encapsulation structure Download PDFInfo
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- CN102779919A CN102779919A CN2011101225013A CN201110122501A CN102779919A CN 102779919 A CN102779919 A CN 102779919A CN 2011101225013 A CN2011101225013 A CN 2011101225013A CN 201110122501 A CN201110122501 A CN 201110122501A CN 102779919 A CN102779919 A CN 102779919A
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- electrode
- adhesive layer
- conductive adhesive
- semiconductor
- semiconductor package
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Abstract
The invention provides a semiconductor encapsulation structure, which comprises a base plate, at least one semiconductor crystal particle, one conducting glue layer and a fluorescence layer, wherein the base plate comprises a first electrode, a second electrode and a reflection layer, the reflection layer is arranged on the first electrode and the second electrode, the conducting glue layer is arranged inside the reflecting layer and covers the first electrode and the second electrode, the semiconductor crystal particle is fixedly arranged on the first electrode and the second electrode through the conducting glue layer and forms the electric connection, and the fluorescence layer is arranged on the conducting glue layer and covers the semiconductor crystal particle. The invention provides a manufacture process for manufacturing the semiconductor encapsulation structure.
Description
Technical field
The present invention relates to a kind of semiconductor package, relate in particular to a kind of semiconductor package with preferable adaptation.
Background technology
The LED industry of semiconductor packages is one of industry that attracted most attention in recent years, development so far, that the LED product has had is energy-conservation, power saving, high efficiency, the reaction time is fast, the life cycle time is long and not mercurous, have advantage such as environmental benefit.Yet, the semiconductor package of LED is provided with because, having a reflector in order to increase luminous efficiency.Said reflector mainly around said semiconductor grain (being said led chip), is reflected with the light that said semiconductor grain is sent, and produces the effect of concentrating light to increase luminosity.But; The position that said reflector is provided with can contact with the electrode that said semiconductor grain electrically connects; Said electrode is to be metal material, and said reflector is to be plastic material, and the tack between these two kinds of materials is not good; Therefore the interface regular meeting of between has aqueous vapor to infiltrate, thereby causes the afunction of said semiconductor grain.So how to avoid aqueous vapor to infiltrate, improve the adaptation of said semiconductor package, be the problem that present semiconductor packages industry is made great efforts.
Summary of the invention
In view of this, be necessary the semiconductor package that provides a kind of adaptation good.
A kind of semiconductor package comprises a substrate, at least one semiconductor grain, a conductive adhesive layer and a fluorescence coating.Said substrate includes one first electrode, second electrode and a reflector, and said reflector is arranged on said first and second electrode.It is inner that said conductive adhesive layer is arranged on said reflector, and cover said first and second electrode.Said semiconductor grain is fixed on said first and second electrode and forms through said conductive adhesive layer and electrically connects.Said fluorescence coating is arranged on the said conductive adhesive layer and covers said semiconductor grain.
A kind of semiconductor package processing procedure, it comprises the steps,
A substrate is provided, one first electrode and one second electrode are set on said substrate, and a reflector is set on said first and second electrode;
Form a conductive adhesive layer, inner in said reflector, and cover said first and second electrode;
At least one semiconductor grain is set, on said conductive adhesive layer, and corresponding said first and second electrode of two electrode contacts that said semiconductor grain is had;
A hot pressing die is provided, said semiconductor grain and said conductive adhesive layer are carried out hot pressing, said semiconductor grain and said first and second electrode are electrically connected; And
Form a fluorescence coating, on said conductive adhesive layer, and cover said semiconductor grain.
In the above-mentioned semiconductor package and processing procedure; Because said semiconductor grain is directly pasted with the hot pressing of said conductive adhesive layer and said two electrodes and is fixed and reach electric connection; The adaptation of said conductive adhesive layer is high; Can effectively avoid aqueous vapor to infiltrate electric connection place of said semiconductor grain and said two electrodes, thereby effectively improve the air-tightness and the water proofing property of said semiconductor package.The electric connection of especially said semiconductor grain and said two electrodes does not need routing, has the effect that reduces said semiconductor package height, helps the miniaturization Design of product.
Description of drawings
Fig. 1 is the cutaway view that semiconductor package of the present invention real first is executed mode.
Fig. 2 is the cutaway view that semiconductor package of the present invention real second is executed mode.
Fig. 3 is the flow chart of steps of semiconductor package processing procedure of the present invention.
Fig. 4 is the cutaway view that corresponding diagram 3 is provided with at least one semiconductor grain step.
Fig. 5 is that corresponding diagram 3 provides first of a hot pressing die step to execute the cutaway view of mode.
Fig. 6 is that corresponding diagram 3 provides second of a hot pressing die step to execute the cutaway view of mode.
The main element symbol description
| Encapsulating structure | 10、20 |
| |
12、22 |
| |
122、222 |
| End face | 1222、1242 |
| |
124、224 |
| The |
126、226 |
| |
14、24 |
| Electrode |
142 |
| Conductive |
16、26 |
| Fluorescence coating | 18、28 |
| |
228 |
| Hot pressing die | 3 |
| Bed die | 32 |
| |
34 |
| Die |
342 |
| |
344 |
Following embodiment will combine above-mentioned accompanying drawing to further specify the present invention.
Embodiment
To combine accompanying drawing that the present invention is done one below specifically introduces.
See also Fig. 1, be depicted as the cutaway view of semiconductor package first execution mode of the present invention, said encapsulating structure 10 comprises a substrate 12, at least one semiconductor grain 14, a conductive adhesive layer 16 and a fluorescence coating 18.Said substrate 12 comprises one first electrode 122, second electrode 124 and a reflector 126.Said first electrode 122 is symmetrical set with said second electrode 124, and has an end face 1222,1242 respectively, and said reflector 126 is arranged on the end face 1222,1242 of said first and second electrode 122,124.The material in said reflector 126 can be reflecting material or high molecular material, for example, and PPA (Polyphthalamide) plastics or epoxide resin material.The said conductive adhesive layer 16 of said reflector 126 set inside, said conductive adhesive layer 16 cover on said first and second electrode 1222,1242.Said conductive adhesive layer 16 is anisotropic conductive (ACAs, Anisotropic Conductive Adhesives), is to go up conduction in a direction (like vertical Z direction), and goes up non-conductive in other direction (like X, the Y direction of level).Said semiconductor grain 14 is arranged on the said conductive adhesive layer 16; Said semiconductor grain 14 has two electrode contacts (pad) 142 of opposed polarity; Said two electrode contacts 142 are positioned on the conducting direction of said conductive adhesive layer 16; And respectively corresponding said first and second electrode 122,124, thereby make said semiconductor grain 14 through said conductive adhesive layer 16 fixing its positions, and electrically connect with said first electrode 122 and said second electrode 124 respectively.In the material of said conductive adhesive layer 16 owing to include epoxy resin (epoxy) or silicon Li Kang (silicon) composition; High with said first and second electrode 122,124 adaptations of metal material; Thereby can prevent that aqueous vapor from infiltrating electric connection place of said semiconductor grain 14; Improve the air-tightness and the water proofing property of said encapsulating structure 10, safeguard the effective utilization that it is good.Said semiconductor grain 14 is light-emitting diode (LED, Light Emitting Diode).Said fluorescence coating 18 is arranged on the said conductive adhesive layer 16, and covers said semiconductor grain 14.Said fluorescence coating 18 can comprise at least a fluorescent material, and the material of said fluorescence coating 18 is epoxy resin (epoxy) or silicon Li Kang (silicon).
Please consult Fig. 2 again, be depicted as the cutaway view of semiconductor package second execution mode of the present invention, said encapsulating structure 20 comprises a substrate 22, at least one semiconductor grain 24, a conductive adhesive layer 26 and a fluorescence coating 28.Said substrate 22 comprises one first electrode 222, second electrode 224 and a reflector 226.Said encapsulating structure 20 essential structures are identical with said encapsulating structure 10, therefore repeat no more.Difference is, the said conductive adhesive layer 26 of said reflector 226 set inside, and said conductive adhesive layer 26 is the joining place with said first electrode 222 and second electrode 224 in said reflector 226, forms to have at least one resistance hurdle layer 228.Said resistance hurdle layer 228 can hinder the infiltration of aqueous vapor between said first electrode 222 in hurdle and second electrode 224 and the said reflector 226 really.Said encapsulating structure 20 has the setting of said resistance hurdle layer 228, forms the high encapsulating structure of adaptation, can effectively prolong the useful life of said encapsulating structure 20.
Please consult Fig. 3 again, be depicted as the flow chart of steps of semiconductor package processing procedure of the present invention, it comprises the steps:
S11 provides a substrate, and one first electrode and one second electrode are set on said substrate, and a reflector is set on said first and second electrode;
S12 forms a conductive adhesive layer, and is inner in said reflector, and covers said first and second electrode;
S13 is provided with at least one semiconductor grain, on said conductive adhesive layer, and corresponding said first and second electrode of two electrode contacts that said semiconductor grain is had;
S14 provides a hot pressing die, and said semiconductor grain and said conductive adhesive layer are carried out hot pressing, and said semiconductor grain and said first and second electrode are electrically connected; And
S15 forms a fluorescence coating, on said conductive adhesive layer, and covers said semiconductor grain.
Said step S11 provides a substrate 12; One first electrode 122 and one second electrode 124 are set on said substrate 12; And on said first and second electrode 122,124, a reflector 126 is set, as shown in Figure 4, said reflector 126 is with the moulding of mould model (Molding) mode; When the material in said reflector 126 can be identical with the material that said substrate 12 uses, make the said reflector 126 can be one-body molded with said substrate 12.
Carry out said step S12 then and form a conductive adhesive layer 16, in 126 inside, said reflector, and cover said first and second electrode 122,124, said conductive adhesive layer 16 fills up the bottom surface of 126 inside, said reflector with liquid state or adhesive tape kenel.Said conductive adhesive layer 16 is an anisotropic conductive, and the direction on vertical said first electrode 122 and second electrode, 124 surfaces has conductivity.
Then carry out said step S13 at least one semiconductor grain 14 is set; On said conductive adhesive layer 16; And two electrode contacts, 142 corresponding said first and second electrodes 122,124 that said semiconductor grain 14 is had; Said two electrode contacts 142 have different polarities, the corresponding respectively vertical direction on said first electrode 122 and second electrode, 124 surfaces.
Carry out said step S14 again a hot pressing die 3 is provided; Said semiconductor grain 14 and said conductive adhesive layer 16 are carried out hot pressing; And said semiconductor grain 14 and said first and second electrode 122,124 are electrically connected; As shown in Figure 5, said hot pressing die 3 comprises a bed die 32 and an internal mold 34, and said bed die 32 is arranged at the bottom of said substrate 12; Said internal mold 34 corresponding said reflector 126 volume inside make said hot pressing die 3 carry out hot pressing to said semiconductor grain 14 and said conductive adhesive layer 16.Has a die cavity 342 on the inner surface of said internal mold 34; The external form of said die cavity 342 corresponding said semiconductor grains 14; When said hot pressing die 3 carried out hot pressing, said die cavity 342 ordered about said semiconductor grain 14 and fits with said first and second electrode 122,124.When said semiconductor grain 14 was fitted with said first and second electrode 122,124, said two electrode contacts 142 contacted with the surface of said first and second electrode 122,124 respectively.Hot pressing is carried out in said hot pressing die 3 heating; Said conductive adhesive layer 16 will solidify; Thereby make said semiconductor grain 14 firm with contacting of said first and second electrode 122,124; Said two electrode contacts 142 are also because vertically contact the surface of said first and second electrode 122,124, and reach electric connection.Said hot pressing die 3 hot pressings can directly remove said hot pressing die 3 after accomplishing, and make 126 inner said conductive adhesive layer 16 tops, said reflector leave accommodation space.
Said step S14 provides a hot pressing die 3; The said internal mold 34 of said hot pressing die 3; Further the outer peripheral edges at said internal mold 34 have a depression 344; When said depression 344 carries out hot pressing at said hot pressing die 3, make the joining place of said conductive adhesive layer 26 at said reflector 226 and said first electrode 222 and second electrode 224, formation has at least one resistance hurdle layer 228 (as shown in Figure 6).
At last, said step S15 forms a fluorescence coating 18, on said conductive adhesive layer 16,26, and covers said semiconductor grain 14,24.Said fluorescence coating 18 is with ejection formation (Injection Molding) mode moulding.
To sum up; Semiconductor package of the present invention; Directly combine said first electrode and second electrode and reach electric connection through said conductive adhesive layer at said semiconductor grain, can prevent effectively that not only aqueous vapor from infiltrating said encapsulating structure, increase the adaptation of said encapsulating structure; Can reduce simultaneously the height of said encapsulating structure, be beneficial to miniaturization Design.Semiconductor package processing procedure of the present invention utilizes the hot pressing mode of said hot pressing die to make, and the big amount of convenient high adaptation encapsulating structure is manufactured.
In addition, those skilled in the art also can do other variation in spirit of the present invention, and certainly, these all should be included within the present invention's scope required for protection according to the variation that the present invention's spirit is done.
Claims (16)
1. semiconductor package; Comprise a substrate, at least one semiconductor grain, a conductive adhesive layer and a fluorescence coating; Said substrate includes one first electrode, second electrode and a reflector; It is characterized in that: said reflector is arranged on said first and second electrode, and it is inner that said conductive adhesive layer is arranged on said reflector, and cover said first and second electrode; Said semiconductor grain is fixed on said first and second electrode and forms through said conductive adhesive layer and electrically connects, and said fluorescence coating is arranged on the said conductive adhesive layer and covers said semiconductor grain.
2. semiconductor package as claimed in claim 1 is characterized in that: said first electrode and said second electrode are symmetrical set, and have an end face respectively, and said end face is provided with said reflector.
3. semiconductor package as claimed in claim 1 is characterized in that: the material in said reflector is reflecting material or high molecular material, for example, and PPA (Polyphthalamide) plastics.
4. semiconductor package as claimed in claim 1 is characterized in that: said conductive adhesive layer is an anisotropic conductive adhesive layer.
5. semiconductor package as claimed in claim 1; It is characterized in that: said semiconductor grain has two electrode contacts of opposed polarity; Said two electrode contacts are positioned on the conducting direction of said conductive adhesive layer; And respectively corresponding said first and second electrode, said semiconductor grain electrically connects through said conductive adhesive layer and said first and second electrode.
6. semiconductor package as claimed in claim 5 is characterized in that: said semiconductor grain is a light-emitting diode.
7. semiconductor package as claimed in claim 1 is characterized in that: said conductive adhesive layer is at the joining place of said reflector and said first electrode and second electrode, and formation has at least one resistance hurdle layer.
8. semiconductor package as claimed in claim 1 is characterized in that: said fluorescence coating comprises at least a fluorescent material, and the material of said fluorescence coating is epoxy resin (epoxy) or silicon Li Kang (silicon).
9. semiconductor package processing procedure, it comprises the steps:
A substrate is provided, one first electrode and one second electrode are set on said substrate, and a reflector is set on said first and second electrode;
Form a conductive adhesive layer, inner in said reflector, and cover said first and second electrode;
At least one semiconductor grain is set, on said conductive adhesive layer, and corresponding said first and second electrode of two electrode contacts that said semiconductor grain is had;
A hot pressing die is provided, said semiconductor grain and said conductive adhesive layer are carried out hot pressing, said semiconductor grain and said first and second electrode are electrically connected; And
Form a fluorescence coating, on said conductive adhesive layer, and cover said semiconductor grain.
10. semiconductor package processing procedure as claimed in claim 9 is characterized in that: said providing in the substrate step, said reflector is with the moulding of mould model mode, or one-body molded with said substrate.
11. semiconductor package processing procedure as claimed in claim 9; It is characterized in that: conductive adhesive layer step of said formation; Said conductive adhesive layer fills up inner bottom surface, said reflector with liquid state or adhesive tape kenel, and has conductivity in the direction of vertical said first electrode and second electrode surface.
12. semiconductor package processing procedure as claimed in claim 9; It is characterized in that: said at least one semiconductor die step that is provided with; Said two electrode contacts have different polarities, the corresponding respectively vertical direction at said first electrode and second electrode surface.
13. semiconductor package processing procedure as claimed in claim 9; It is characterized in that: said a hot pressing die step is provided; Said hot pressing die comprises a bed die and an internal mold, and said bed die is arranged at the bottom of said substrate, the corresponding said reflector of said internal mold volume inside.
14. semiconductor package processing procedure as claimed in claim 13 is characterized in that: have a die cavity on the inner surface of said internal mold, the external form of the corresponding said semiconductor grain of said die cavity.
15. semiconductor package processing procedure as claimed in claim 14 is characterized in that: said internal molds edge has a depression.
16. semiconductor package processing procedure as claimed in claim 9 is characterized in that: fluorescence coating step of said formation, said fluorescence coating is with the injection molding method moulding.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110122501.3A CN102779919B (en) | 2011-05-12 | 2011-05-12 | Semiconductor encapsulation structure |
| TW100124133A TWI425676B (en) | 2011-05-12 | 2011-07-08 | Structure of the semiconductir package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110122501.3A CN102779919B (en) | 2011-05-12 | 2011-05-12 | Semiconductor encapsulation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102779919A true CN102779919A (en) | 2012-11-14 |
| CN102779919B CN102779919B (en) | 2015-07-08 |
Family
ID=47124770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110122501.3A Expired - Fee Related CN102779919B (en) | 2011-05-12 | 2011-05-12 | Semiconductor encapsulation structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102779919B (en) |
| TW (1) | TWI425676B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195757A (en) * | 2017-07-06 | 2017-09-22 | 庞绮琪 | A kind of LED encapsulation structure |
| CN107331751A (en) * | 2017-07-06 | 2017-11-07 | 庞绮琪 | The encapsulating structure of LED service lifes can be extended |
| CN110880544A (en) * | 2018-09-06 | 2020-03-13 | 深圳市斯迈得半导体有限公司 | Chip for glass substrate and manufacturing method thereof |
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| US20060102918A1 (en) * | 2004-11-16 | 2006-05-18 | Wen-Lung Su | Package Structure of a Surface Mount Device Light Emitting Diode |
| US20070029570A1 (en) * | 2005-08-04 | 2007-02-08 | Samsung Electronics Co., Ltd. | LED package and method for fabricating the same |
| CN1925176A (en) * | 2005-09-02 | 2007-03-07 | 杨丕福 | Integrated light emitting device and method for making same |
| CN101295754A (en) * | 2007-04-26 | 2008-10-29 | 亿光电子工业股份有限公司 | Flip-chip soldering encapsulation structure and method for light emitting diode |
| CN101488544A (en) * | 2008-01-18 | 2009-07-22 | 晶元光电股份有限公司 | Light emitting element and method for manufacturing the same |
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| TW461123B (en) * | 2000-11-10 | 2001-10-21 | Ind Tech Res Inst | Flip-chip packaging method and structure for light emitting device |
| JP3679786B2 (en) * | 2002-06-25 | 2005-08-03 | 松下電器産業株式会社 | Manufacturing method of semiconductor device |
| TW200717854A (en) * | 2005-10-27 | 2007-05-01 | Formosa Epitaxy Inc | Surface mount light emitting diode package |
| KR100845856B1 (en) * | 2006-12-21 | 2008-07-14 | 엘지전자 주식회사 | LED package and method of manufacturing the same |
-
2011
- 2011-05-12 CN CN201110122501.3A patent/CN102779919B/en not_active Expired - Fee Related
- 2011-07-08 TW TW100124133A patent/TWI425676B/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060102918A1 (en) * | 2004-11-16 | 2006-05-18 | Wen-Lung Su | Package Structure of a Surface Mount Device Light Emitting Diode |
| US20070029570A1 (en) * | 2005-08-04 | 2007-02-08 | Samsung Electronics Co., Ltd. | LED package and method for fabricating the same |
| CN1925176A (en) * | 2005-09-02 | 2007-03-07 | 杨丕福 | Integrated light emitting device and method for making same |
| CN101295754A (en) * | 2007-04-26 | 2008-10-29 | 亿光电子工业股份有限公司 | Flip-chip soldering encapsulation structure and method for light emitting diode |
| CN101488544A (en) * | 2008-01-18 | 2009-07-22 | 晶元光电股份有限公司 | Light emitting element and method for manufacturing the same |
| CN101533886A (en) * | 2009-04-28 | 2009-09-16 | 友达光电股份有限公司 | A luminous module encapsulation method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195757A (en) * | 2017-07-06 | 2017-09-22 | 庞绮琪 | A kind of LED encapsulation structure |
| CN107331751A (en) * | 2017-07-06 | 2017-11-07 | 庞绮琪 | The encapsulating structure of LED service lifes can be extended |
| CN110880544A (en) * | 2018-09-06 | 2020-03-13 | 深圳市斯迈得半导体有限公司 | Chip for glass substrate and manufacturing method thereof |
| CN110880544B (en) * | 2018-09-06 | 2021-09-03 | 深圳市斯迈得半导体有限公司 | Chip for glass substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102779919B (en) | 2015-07-08 |
| TW201246617A (en) | 2012-11-16 |
| TWI425676B (en) | 2014-02-01 |
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