CN102723286B - 芯片正装双面三维线路先封后蚀制造方法及其封装结构 - Google Patents
芯片正装双面三维线路先封后蚀制造方法及其封装结构 Download PDFInfo
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- CN102723286B CN102723286B CN2012101899379A CN201210189937A CN102723286B CN 102723286 B CN102723286 B CN 102723286B CN 2012101899379 A CN2012101899379 A CN 2012101899379A CN 201210189937 A CN201210189937 A CN 201210189937A CN 102723286 B CN102723286 B CN 102723286B
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/078—Adhesive characteristics other than chemical
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- H01—ELECTRIC ELEMENTS
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN2012101899379A CN102723286B (zh) | 2012-06-09 | 2012-06-09 | 芯片正装双面三维线路先封后蚀制造方法及其封装结构 |
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CN2012101899379A CN102723286B (zh) | 2012-06-09 | 2012-06-09 | 芯片正装双面三维线路先封后蚀制造方法及其封装结构 |
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CN102723286A CN102723286A (zh) | 2012-10-10 |
CN102723286B true CN102723286B (zh) | 2013-11-27 |
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CN2012101899379A Active CN102723286B (zh) | 2012-06-09 | 2012-06-09 | 芯片正装双面三维线路先封后蚀制造方法及其封装结构 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1691314A (zh) * | 2004-04-21 | 2005-11-02 | 美龙翔微电子科技(深圳)有限公司 | 倒装球栅阵列封装基板及其制作工艺 |
CN101840901A (zh) * | 2010-04-30 | 2010-09-22 | 江苏长电科技股份有限公司 | 无基岛静电释放圈引线框结构及其生产方法 |
CN102005432A (zh) * | 2010-09-30 | 2011-04-06 | 江苏长电科技股份有限公司 | 四面无引脚封装结构及其封装方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4373122B2 (ja) * | 2003-04-28 | 2009-11-25 | 大日本印刷株式会社 | 樹脂封止型半導体装置とその製造方法 |
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2012
- 2012-06-09 CN CN2012101899379A patent/CN102723286B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1691314A (zh) * | 2004-04-21 | 2005-11-02 | 美龙翔微电子科技(深圳)有限公司 | 倒装球栅阵列封装基板及其制作工艺 |
CN101840901A (zh) * | 2010-04-30 | 2010-09-22 | 江苏长电科技股份有限公司 | 无基岛静电释放圈引线框结构及其生产方法 |
CN102005432A (zh) * | 2010-09-30 | 2011-04-06 | 江苏长电科技股份有限公司 | 四面无引脚封装结构及其封装方法 |
Non-Patent Citations (1)
Title |
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JP特开2004-327903A 2004.11.18 |
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Effective date of registration: 20200604 Address after: 214434, No. 78, mayor road, Chengjiang, Jiangsu, Jiangyin, Wuxi Patentee after: JIANGSU CHANGJIANG ELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 1-1-1802-7, North Zone, financial and Trade Center, No. 6865, Asia Road, Tianjin pilot free trade zone (Dongjiang Free Trade Port) Patentee before: Xin Xin finance leasing (Tianjin) Co.,Ltd. |