CN101840901A - 无基岛静电释放圈引线框结构及其生产方法 - Google Patents
无基岛静电释放圈引线框结构及其生产方法 Download PDFInfo
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- CN101840901A CN101840901A CN201010165884A CN201010165884A CN101840901A CN 101840901 A CN101840901 A CN 101840901A CN 201010165884 A CN201010165884 A CN 201010165884A CN 201010165884 A CN201010165884 A CN 201010165884A CN 101840901 A CN101840901 A CN 101840901A
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 41
- 239000005022 packaging material Substances 0.000 claims description 20
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- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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- 229910000679 solder Inorganic materials 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
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- 230000007812 deficiency Effects 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010101658848A CN101840901B (zh) | 2010-04-30 | 2010-04-30 | 无基岛静电释放圈引线框结构及其生产方法 |
Applications Claiming Priority (1)
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CN2010101658848A CN101840901B (zh) | 2010-04-30 | 2010-04-30 | 无基岛静电释放圈引线框结构及其生产方法 |
Publications (2)
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CN101840901A true CN101840901A (zh) | 2010-09-22 |
CN101840901B CN101840901B (zh) | 2011-10-05 |
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Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102723284A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片正装单面三维线路先蚀后封制造方法及其封装结构 |
CN102723282A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片正装双面三维线路先蚀后封制造方法及其封装结构 |
CN102723289A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片正装单面三维线路先封后蚀制造方法及其封装结构 |
CN102723286A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片正装双面三维线路先封后蚀制造方法及其封装结构 |
CN102723283A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 双面三维线路芯片正装先蚀后封制造方法及其封装结构 |
CN102723290A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 单面三维线路芯片正装先封后蚀制造方法及其封装结构 |
CN102723280A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 单面三维线路芯片倒装先蚀后封制造方法及其封装结构 |
CN102723288A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片倒装单面三维线路先封后蚀制造方法及其封装结构 |
CN102760668A (zh) * | 2012-06-09 | 2012-10-31 | 江苏长电科技股份有限公司 | 单面三维线路芯片倒装先封后蚀制造方法及其封装结构 |
CN102856212A (zh) * | 2012-06-09 | 2013-01-02 | 江苏长电科技股份有限公司 | 双面三维线路芯片倒装先封后蚀制造方法及其封装结构 |
CN102908793A (zh) * | 2012-10-25 | 2013-02-06 | 浙江大学 | 适于粘稠物系连续分离的卧式双轴蒸馏装置 |
WO2013078750A1 (en) * | 2011-11-30 | 2013-06-06 | Jiangsu Changjiang Electronics Technology Co. Ltd | First-plating-then-etching quad flat no-lead (qfn) packaging structures and method for manufacturing the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US20060033184A1 (en) * | 2004-08-11 | 2006-02-16 | Park Hyung J | Process and lead frame for making leadless semiconductor packages |
CN201060865Y (zh) * | 2007-07-15 | 2008-05-14 | 天水华天科技股份有限公司 | 无基岛引线框架 |
CN201417765Y (zh) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | 无基岛半导体芯片封装结构 |
CN201752008U (zh) * | 2010-04-30 | 2011-02-23 | 江苏长电科技股份有限公司 | 无基岛静电释放圈引线框结构 |
-
2010
- 2010-04-30 CN CN2010101658848A patent/CN101840901B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060033184A1 (en) * | 2004-08-11 | 2006-02-16 | Park Hyung J | Process and lead frame for making leadless semiconductor packages |
CN201060865Y (zh) * | 2007-07-15 | 2008-05-14 | 天水华天科技股份有限公司 | 无基岛引线框架 |
CN201417765Y (zh) * | 2009-04-01 | 2010-03-03 | 苏州固锝电子股份有限公司 | 无基岛半导体芯片封装结构 |
CN201752008U (zh) * | 2010-04-30 | 2011-02-23 | 江苏长电科技股份有限公司 | 无基岛静电释放圈引线框结构 |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013078750A1 (en) * | 2011-11-30 | 2013-06-06 | Jiangsu Changjiang Electronics Technology Co. Ltd | First-plating-then-etching quad flat no-lead (qfn) packaging structures and method for manufacturing the same |
CN102723286B (zh) * | 2012-06-09 | 2013-11-27 | 江苏长电科技股份有限公司 | 芯片正装双面三维线路先封后蚀制造方法及其封装结构 |
CN102856212B (zh) * | 2012-06-09 | 2015-02-11 | 江苏长电科技股份有限公司 | 双面三维线路芯片倒装先封后蚀制造方法及其封装结构 |
CN102856212A (zh) * | 2012-06-09 | 2013-01-02 | 江苏长电科技股份有限公司 | 双面三维线路芯片倒装先封后蚀制造方法及其封装结构 |
CN102723283A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 双面三维线路芯片正装先蚀后封制造方法及其封装结构 |
CN102723290A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 单面三维线路芯片正装先封后蚀制造方法及其封装结构 |
CN102723280A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 单面三维线路芯片倒装先蚀后封制造方法及其封装结构 |
CN102723288A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片倒装单面三维线路先封后蚀制造方法及其封装结构 |
CN102760668A (zh) * | 2012-06-09 | 2012-10-31 | 江苏长电科技股份有限公司 | 单面三维线路芯片倒装先封后蚀制造方法及其封装结构 |
CN102723286A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片正装双面三维线路先封后蚀制造方法及其封装结构 |
CN102723289A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片正装单面三维线路先封后蚀制造方法及其封装结构 |
CN102723288B (zh) * | 2012-06-09 | 2013-09-04 | 江苏长电科技股份有限公司 | 芯片倒装单面三维线路先封后蚀制造方法及其封装结构 |
CN102723282A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片正装双面三维线路先蚀后封制造方法及其封装结构 |
CN102723289B (zh) * | 2012-06-09 | 2013-09-04 | 江苏长电科技股份有限公司 | 芯片正装单面三维线路先封后蚀制造方法及其封装结构 |
CN102723283B (zh) * | 2012-06-09 | 2013-10-09 | 江苏长电科技股份有限公司 | 双面三维线路芯片正装先蚀后封制造方法及其封装结构 |
CN102723284A (zh) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | 芯片正装单面三维线路先蚀后封制造方法及其封装结构 |
CN102723290B (zh) * | 2012-06-09 | 2013-11-27 | 江苏长电科技股份有限公司 | 单面三维线路芯片正装先封后蚀制造方法及其封装结构 |
CN102723284B (zh) * | 2012-06-09 | 2014-02-26 | 江苏长电科技股份有限公司 | 芯片正装单面三维线路先蚀后封制造方法及其封装结构 |
CN102723280B (zh) * | 2012-06-09 | 2014-07-09 | 江苏长电科技股份有限公司 | 单面三维线路芯片倒装先蚀后封制造方法 |
CN102908793A (zh) * | 2012-10-25 | 2013-02-06 | 浙江大学 | 适于粘稠物系连续分离的卧式双轴蒸馏装置 |
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