CN102683264B - 半导体结构的制作方法 - Google Patents

半导体结构的制作方法 Download PDF

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CN102683264B
CN102683264B CN201110053783.6A CN201110053783A CN102683264B CN 102683264 B CN102683264 B CN 102683264B CN 201110053783 A CN201110053783 A CN 201110053783A CN 102683264 B CN102683264 B CN 102683264B
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interconnection layer
semiconductor substrate
annular
hole
dielectric layer
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CN102683264A (zh
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奚民伟
朱虹
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Abstract

本发明实施例提供半导体结构的制作方法，所述方法包括：提供键合为一体的半导体衬底和基板，所述半导体衬底和基板之间具有后段互连层，所述后段互连层内形成有焊垫；在所述半导体衬底或所述半导体衬底与所述后段互连层内形成环形通孔，所述环形通孔露出部分焊垫；在所述环形通孔内形成介质层，所述介质层至少填充满所述环形通孔；进行湿法刻蚀工艺，去除所述环形通孔包围的半导体衬底，形成露出所述焊垫的沟槽；在所述沟槽内形成互连层，所述互连层与所述焊垫电连接；在所述互连层上方形成与互连层电连接的导电凸块。本发明减小了对焊垫的损伤，提高了封装的可靠性；同时，简化了的工艺步骤，提高了生产效率，节约了生产成本。

Description

半导体结构的制作方法
技术领域
本发明涉及半导体技术领域，特别涉及一种半导体结构的制作方法。
背景技术
随着半导体芯片的特征尺寸逐渐缩小，为了在有效的芯片面积内增加更多的功能，3D封装应运而生。所述3D封装采用焊球凸点将PCB基板与半导体衬底焊接，从而无需键合引线，使得封装后的芯片的体积更小，可以支持更高的数据传输速率。现有的3D封装技术需要首先提供符合工艺需要的半导体结构，然后将所述半导体结构进行塑料封装或陶瓷封装。
请结合图1～图4所示现有的半导体结构的制作方法的剖面结构示意图。首先，如图1所示，提供半导体衬底10。所述半导体衬底10一侧的表面形成有半导体后段互连层11，所述半导体后段互连层11内形成有焊垫12(PAD)。所述半导体衬底10内还形成有半导体器件，所述半导体器件与所述焊垫12电连接。
然后，继续参考图1，将所述半导体衬底10的半导体后段互连层11与基板13键合，使得所述半导体衬底10和基板13形成一体的初始半导体结构，之后，对所述半导体衬底10的远离所述基板13的一侧进行减薄工艺，使得减薄后的半导体衬底10的厚度满足工艺要求。
然后，请参考图2，从所述半导体衬底10的远离所述基板13的一侧进行等离子体刻蚀工艺，在所述半导体衬底10的远离所述基板13的一侧形成沟槽，所述沟槽露出所述焊垫12。
接着，请参考图3，在所述沟槽的侧壁和半导体衬底10表面形成介质层16，然后在所述沟槽内形成互连层14，所述互连层14将所述沟槽填满，且所述互连层14覆盖所述介质层16的表面。
接着，请参考图4，在所述互连层14上形成金属凸块(bump)15，所述金属凸块15与所述互连层14电连接。
通常，在所述金属凸块15形成后，需要对所述进行封装工艺。根据产品设计，所述封装工艺可以是塑料封装或陶瓷封装。在公开号为CN101404279A的中国专利申请中还可以发现更多关于现有的3D封装的信息。
然而，现有技术形成的半导体结构的可靠性不高，这使得3D封装的可靠性不高。
发明内容
本发明实施例解决的问题是提供了一种半导体结构的制作方法，所述方法制作的互连层的均匀度好，且减小了对焊垫的损伤，提高了形成的半导体结构的可靠性，提高了3D封装的可靠性，同时，简化了的工艺步骤，提高了生产效率，节约了生产成本。
为解决上述问题，本发明实施例提供一种半导体结构的方法，包括：
提供键合为一体的半导体衬底和基板，所述半导体衬底和基板之间形成有后段互连层，所述后段互连层内形成有焊垫；
在所述半导体衬底或所述半导体衬底与所述后段互连层内形成环形通孔，所述环形通孔露出部分焊垫；
在所述环形通孔内形成介质层，所述介质层至少填充满所述环形通孔；
以所述介质层为掩膜，进行湿法刻蚀工艺，去除所述环形通孔包围的半导体衬底，形成露出所述焊垫的沟槽；
在所述沟槽内形成互连层，所述互连层与所述焊垫电连接；
在所述互连层上方形成导电凸块，所述导电凸块与所述互连层电连接。
可选地，所述湿法刻蚀工艺对所述半导体衬底和介质层的刻蚀选择比大于100∶1，所述湿法刻蚀工艺利用酸性刻蚀溶液进行。
可选地，所述酸性刻蚀溶液为含有氢氟酸和硝酸的混合溶液。
可选地，所述介质层的材质为电学绝缘材质，所述电学绝缘材质为氧化硅或掺杂的氧化硅。
可选地，所述介质层的厚度范围为0.5微米～5微米。
可选地，所述环形通孔的宽度范围为0.1～50微米。
可选地，在所述环形通孔形成前，还包括：
对所述半导体衬底远离所述基板的一侧的表面进行减薄的工艺，减薄后的半导体衬底的厚度范围为2～300微米。
可选地，所述焊垫位于所述后段互连层的靠近所述半导体衬底的表面，所述环形通孔为通过对所述半导体衬底进行刻蚀形成。
可选地，所述焊垫位于所述后段互连层的靠近所述基板的表面，所述环形通孔为通过对所述半导体衬底和后段互连层进行刻蚀形成。
可选地，所述介质层还形成在所述半导体衬底的表面，形成所述互连层包括：
对位于所述沟槽一侧的介质层进行刻蚀，在所述介质层内形成互连层开口，所述互连层开口与所述沟槽相连通；
在所述互连层开口和沟槽内填充金属，在所述互连层开口和沟槽内形成互连层，所述互连层与所述位于沟槽另一侧的介质层齐平。
与现有技术相比，本发明具有以下优点：
本发明实施例首先在所述半导体衬底或半导体衬底与所述后段互连层内形成环形通孔，所述环形通孔露出部分焊垫；接着，在所述环形通孔内形成介质层，所述介质层至少填充满所述环形通孔；然后，本发明实施例以所述介质层为掩膜，进行湿法刻蚀工艺，去除所述环形通孔包围的半导体衬底，形成露出所述焊垫的沟槽；相对于现有技术利用等离子体刻蚀工艺刻蚀所述半导体衬底，在所述半导体衬底内形成沟槽，本发明的湿法刻蚀工艺对焊垫的损伤小，并且本发明实施例提高了形成的沟槽的均匀度，改善了工艺的稳定性，本发明实施例形成的互连层的均匀度较好，本发明实施例对焊垫的损伤较小，从而本发明实施例提高了形成的半导体结构的可靠性，提高了3D封装的可靠性，同时，简化了的工艺步骤，提高了生产效率，节约了生产成本。
附图说明
图1～图4是现有技术的半导体结构的制作方法的剖面结构示意图；
图5是本发明实施例的半导体结构制作方法流程示意图；
图6～图13是本发明一个实施例的半导体结构制作方法的剖面结构示意图；
图14是图8的俯视结构示意图；
图15是图10的俯视结构示意图；
图16是图11的俯视结构示意图；
图17是图12的俯视结构示意图；
图18是图13的俯视结构示意图。
具体实施方式
现有的半导体结构的可靠性不高，这影响了封装后的芯片的可靠性。经过发明人研究发现，由于焊垫受到了损伤，这会影响半导体结构的可靠性。
具体地，请结合图2，在刻蚀半导体衬底10形成沟槽时，现有技术利用等离子体刻蚀工艺进行。由于等离子体刻蚀工艺的刻蚀速率不够均匀，同时需要刻蚀形成的沟槽的深度较大，这使得所述等离子体刻蚀工艺的时间也会较长，从而很难控制半导体衬底各区域沟槽的形貌和工艺的均匀度，从而可能导致焊垫12受到损伤，如图2所示；或者部分焊垫上的半导体衬底未被完全去除。并且所述等离子体刻蚀工艺是在高强度的电场的条件下进行，所述高强度的电场会损伤半导体器件。进一步地，发明人发现，通过调整现有的等离子体刻蚀工艺的参数无法有效改善形成的沟槽的形貌和工艺的均匀度。
为了解决上述问题，发明人提出一种半导体结构的制作方法，请结合图5，图5为本发明实施例的本发明的半导体结构的制作方法，所述方法包括：
步骤S1，提供键合为一体的半导体衬底和基板，所述半导体衬底和基板之间形成有后段互连层，所述后段互连层内形成有焊垫；
步骤S2，在所述半导体衬底或所述半导体衬底与所述后段互连层内形成环形通孔，所述环形通孔露出部分焊垫；
步骤S3，在所述环形通孔内形成介质层，所述介质层至少填充满所述环形通孔；
步骤S4，以所述介质层为掩膜，进行湿法刻蚀工艺，去除所述环形通孔包围的半导体衬底，形成露出所述焊垫的沟槽；
步骤S5，在所述沟槽内形成互连层，所述互连层与所述焊垫电连接；
步骤S6，在所述互连层上方形成导电凸块，所述导电凸块与所述互连层电连接。下面结合具体的实施例对本发明的技术方案进行详细的说明。为了更好地说明本发明的技术方案，请结合图6～图13是本发明一个实施例的半导体结构制作方法剖面结构示意图。
首先，请参考图6，提供s键合为一体的半导体衬底100和基板103，所述半导体衬底100和基板103之间形成有后段互连层101，所述后段互连层101内形成有焊垫102。
作为一个实施例，所述焊垫102位于所述后段互连层101的靠近所述半导体衬底100的表面。作为其他的实施例，所述焊垫102还可以形成在所述后段互连层101的靠近所述基板103的表面上。
所述半导体衬底100的材质通常为半导体材质，例如所述半导体衬底100的材质可以为硅、锗硅或绝缘体上硅。
所述半导体衬底100上还形成有器件层(未示出)，所述器件层内形成有半导体器件，所述半导体器件可以为晶体管、二极管或其他半导体器件。
所述后段互连层101形成于所述器件层上方，所述后段互连层101的材质为电学绝缘材质，所述后段互连层101内形成有金属互连线，所述金属互连线将所述器件层内的半导体器件与焊垫102电连接。所述后段互连层101通过键合或临时键合工艺与所述基板103键合，使得所述半导体衬底100、后段互连层101和基板103形成一体的结构。本实施例中，所述焊垫102的宽度范围为20～100微米。
作为一个实施例，所述基板103的材质为玻璃基板。作为本发明的其他实施，所述基板103的材质还可以为半导体材质。
接着，请参考图7，对所述半导体衬底100远离所述基板103的一侧表面进行减薄，使得减薄后的半导体衬底100的厚度符合工艺要求。本实施例中，减薄后的半导体衬底100的厚度范围为2～300微米。所述减薄的方法与现有技术相同，作为本领域技术人员的公知技术，在此不做详细的说明。
然后，请参考图8，沿所述半导体衬底100的厚度方向对所述半导体衬底100远离所述基板103一侧的表面进行刻蚀工艺，在所述半导体衬底100内形成环形通孔，所述环形通孔露出所述焊垫102，所述环形通孔包围部分半导体衬底100。所述刻蚀工艺可以为等离子体刻蚀工艺或湿法刻蚀工艺。
请结合图8，所述环形通孔具有外环和内环。其中，所述环形通孔的外环宽度W1的尺寸与所述焊垫102的宽度相同，并且所述环形通孔的外环的两端与所述焊垫102的两端对应，所述环形通孔的内环宽度W2的尺寸比所述外环宽度W1略小，使得所述环形通孔位于所述焊垫102的外围。
所述环形通孔内将在后续的工艺步骤中填充介质层，所述介质层一方面可以用于将后续填充的金属层与半导体衬底100电学绝缘，另一方面所述介质层还可以用于后续刻蚀所述环形通孔包围的半导体衬底时保护下方的焊垫102和环形通孔两侧的半导体衬底，使得所述焊垫102和环形通孔两侧的半导体衬底避免受到刻蚀工艺的损伤。
由于所述环形通孔下方的部分焊垫102将由于覆盖了介质层而无法作为焊垫使用，会减小所述焊垫的实际使用面积。为了避免所述焊垫102的损伤过大，所述环形通孔的宽度不应过大。本发明所述的实施例所述的环形通孔的宽度具体是指，环形通孔的外环宽度W1与内环宽度W2的宽度之差的1/2。作为可选的实施例，以所述焊垫102宽度范围为20～150微米为例，所述环形通孔的宽度范围为0.1～50微米。
请结合图14所示的图8的俯视结构示意图。所述环形通孔包围部分半导体衬底100，所述环形通孔露出部分焊垫102。
本实施例中，所述环形通孔暴露出所述焊垫102的外围。所述环形通孔的形状为圆形，在其他的实施例中，所述环形通孔的性质还可以为椭圆、四边形等形状，在此不应限制本发明的保护范围。
需要说明的是，若所述焊垫102位于所述后段互连层101的靠近所述基板103的表面上，则所述环形通孔需要形成在所述半导体衬底100与后段互连层101内，对应地，所述刻蚀工艺需要对所述半导体衬底100与所述后段互连层101进行，以保证形成的环形通孔将所述焊垫102露出。
然后，请参考图9，在所述环形通孔内形成介质层104，本实施例中，所述介质层104还覆盖所述半导体衬底100表面，位于所述环形通孔内的所述介质层104包围部分半导体衬底100。
作为一个实施例，所述介质层104的厚度范围为0.5微米～5微米。
位于所述环形通孔内的介质层104包围的部分半导体衬底100将通过刻蚀工艺去除，位于环形通孔内的所述介质层104作为刻蚀工艺的保护层，保护不需要进行刻蚀工艺的半导体衬底。所述介质层104的材质应选择与所述半导体衬底100和焊垫102具有刻蚀选择比的材质。本实施例中，所述介质层104的材质为电学绝缘材质。所述电学绝缘材质可以为氧化硅、氮化硅、碳化硅或氮氧化硅。作为可选的实施例，所述电学绝缘材质为氧化硅，所述氧化硅可以为纯净的氧化硅或掺杂的氧化硅。所述掺杂的氧化硅可以为含磷氧化硅、含硼氧化硅或含硼磷氧化硅。
然后，请参考图10，去除所述环形通孔包围的半导体衬底100表面覆盖的介质层104，以便于将所述环形通孔包围的部分半导体衬底暴露。可以利用湿法刻蚀或干法刻蚀将所述介质层104去除。
请结合图15，图15为图10的半导体结构的俯视结构示意图。所述环形通孔包围半导体衬底100。
具体地，在去除所述环形通孔包围的半导体衬底100表面的覆盖的介质层104时，需要在所述半导体衬底100表面形成掩膜层，所述掩膜层将所述环形通孔包围的半导体衬底100表面覆盖的介质层104暴露，然后以所述掩膜层为掩膜，进行干法刻蚀工艺或湿法刻蚀工艺，从而将所述掩膜层暴露的区域去除，形成如图15和图10所示的结构，将所述环形通孔包围的半导体衬底100表面覆盖的介质层104去除。最后，还需要将所述掩膜层去除。所述掩膜层可以为光刻胶层或硬掩膜层。
接着，请参考图11，进行湿法刻蚀工艺，去除所述环形通孔包围的部分所述半导体衬底100，形成露出所述焊垫102的沟槽。所述湿法刻蚀工艺对所述半导体衬底100和介质层104的刻蚀选择比大于100∶1，所述湿法刻蚀工艺利用酸性刻蚀溶液进行。所述酸性刻蚀溶液为含有氢氟酸和硝酸的混合溶液。
由于利用湿法刻蚀工艺制作所述沟槽，与现有技术利用等离子体刻蚀工艺相比，所述湿法刻蚀工艺的均匀度好，并且由于所述湿法刻蚀工艺对所述半导体衬底100和介质层104的刻蚀选择比大于100∶1，从而所述湿法刻蚀工艺对可以将位于环形通孔内的半导体衬底和氧化物去除而不会损伤焊垫102和所述介质层104。
在进行所述湿法刻蚀工艺前，需要在所述半导体衬底100表面形成掩膜层，所述掩膜层覆盖在介质层104表面，从而将环形通孔包围的半导体衬底暴露。在所述湿法刻蚀工艺结束后，还需要将所述掩膜层去除。本发明实施例所述的掩膜层可以为光刻胶或硬掩膜层。
作为本发明的一个实施例，还在所述沟槽一侧的介质层104进行刻蚀工艺，在所述介质层104内形成互连层开口108，所述互连层开口108与所述沟槽相连通。
请结合图16，图16为图11的半导体结构的俯视结构示意图。互连层开口108与所述沟槽相连通，所述互连层开口108和沟槽内在后续的工艺步骤中将填充金属，形成互连层。
形成所述互连层开口108的刻蚀工艺可以为湿法刻蚀工艺或干法刻蚀工艺。本实施例中，形成所述互连层开口108的刻蚀工艺为湿法刻蚀工艺。作为一个实施例，形成所述互连层开口108的刻蚀工艺为湿法刻蚀工艺，形成所述互连层开口108的湿法刻蚀工艺与形成所述沟槽的刻蚀工艺利用同一湿法刻蚀工艺进行，以节约工艺步骤。当然，所述互连层开口108也可以采用单独的湿法刻蚀工艺或干法刻蚀工艺制作。本实施例中，所述互连层开口108的深度范围为刻蚀前的介质层的厚度的1/5～3/4。
接着，请继续参考图12，在所述沟槽和所述互连层开口107内填充金属，形成互连层107。所述金属可以为金、银、钛、铜、钨、铝等。作为一个实施例，所述互连层107的材质为铜。所述互连层107可以利用电镀工艺制作。
在所述互连层107制作后，需要进行平坦化工艺，使得所述互连层107与所述沟槽另一侧的介质层104齐平。所述平坦化工艺可以为化学机械研磨工艺。
请参考图17，图17为图12的半导体结构的俯视结构示意图。所述互连层107填充满所述沟槽和互连层开口108。
需要说明的是，所述互连层107也可以形成在所述沟槽内和介质层的表面，对应地，在进行湿法刻蚀工艺形成所述沟槽时，无需在所述沟槽一侧的介质层内形成互连层开口。
然后，请参考图13，在所述互连层107上方形成导电凸块109。所述导电凸块109的制作方法与现有技术相同，作为本领域技术人员的公知技术，在此不做详细的说明。
结合图18，图18为图13所示的半导体结构的俯视结构示意图。导电凸块109形成在互连层107上。
通常，在导电凸块109形成后，需要进行塑料封装工艺。所述封装工艺可以为公知的塑料封装或陶瓷封装，作为本领域技术人员的公知技术，在此不做详细的说明。
经过上述步骤，形成的半导体结构如图13所示，包括：
键合为一体的半导体衬底100、基板103，所述半导体衬底100和基板103之间具有后段互连层101，所述后段互连层101内具有焊垫102，所述半导体衬底100上具有器件层，所述器件层内形成有半导体器件，所述后段互连层101位于所述器件层上方，本实施例中，所述后段互连层101内形成有金属互连线，所述金属互连线将所述器件层内的半导体器件与焊垫102电连接；
沟槽，位于所述半导体衬底100内，所述沟槽与所述半导体衬底100齐平；
介质层104，位于所述沟槽的侧壁和半导体衬底100的表面；本实施例中，位于所述沟槽两侧的介质层104的厚度不同，位于所述沟槽一侧的介质层104内形成有互连层开口，所述互连层开口与所述沟槽相连通；
互连层107，位于所述沟槽和互连层开口内，所述互连层107与所述焊垫102电连接；
导电凸块108，位于所述互连层107上方，所述导电凸块108与所述互连层107电连接。
其中，所述环形通孔的位置与所述焊垫102的位置有关，在其他的实施例中，若所述焊垫102位于所述后段互连层101的靠近所述基板103的一侧，则所述环形通孔将位于所述半导体衬底100和后段互连层101内。
在本发明的其他实施例中，位于所述沟槽两侧的介质层104的厚度可以相同，所述沟槽一侧的介质层104内可以没有互连层开口，所述互连层107可以形成于所述沟槽内和介质层104表面。
综上，本发明实施例首先在所述半导体衬底或半导体衬底与所述后段互连层内形成环形通孔，所述环形通孔露出部分焊垫；接着，在所述环形通孔内形成介质层，所述介质层至少填充满所述环形通孔；然后，本发明实施例以所述介质层为掩膜，进行湿法刻蚀工艺，去除所述环形通孔包围的半导体衬底，形成露出所述焊垫的沟槽；相对于现有技术利用等离子体刻蚀工艺刻蚀所述半导体衬底，在所述半导体衬底内形成沟槽，本发明的湿法刻蚀工艺对焊垫的损伤小，并且本发明实施例提高了形成的沟槽的均匀度，改善了工艺的稳定性，本发明实施例形成的互连层的均匀度较好，本发明实施例对焊垫的损伤较小，从而本发明实施例提高了形成的半导体结构的可靠性，提高了3D封装的可靠性，同时，简化了的工艺步骤，提高了生产效率，节约了生产成本。
以上所述，仅是本发明的较佳实施例而已，并非对本发明作任何形式上的限制。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (9)

1.一种半导体结构的制作方法，其特征在于，包括：
提供键合为一体的半导体衬底和基板，所述半导体衬底和基板之间形成有后段互连层，所述后段互连层内形成有焊垫；
在所述半导体衬底或所述半导体衬底与所述后段互连层内形成环形通孔，所述环形通孔露出部分焊垫；
在所述环形通孔内形成介质层，所述介质层至少填充满所述环形通孔；
以所述介质层为掩膜，进行湿法刻蚀工艺，去除所述环形通孔包围的半导体衬底，形成露出所述焊垫的沟槽；
在所述沟槽内形成互连层，所述互连层与所述焊垫电连接；
在所述互连层上方形成导电凸块，所述导电凸块与所述互连层电连接。
2.如权利要求1所述的半导体结构的制作方法，其特征在于，所述湿法刻蚀工艺对所述半导体衬底和介质层的刻蚀选择比大于100:1，所述湿法刻蚀工艺利用酸性刻蚀溶液进行。
3.如权利要求2所述的半导体结构的制作方法，其特征在于，所述酸性刻蚀溶液为含有氢氟酸和硝酸的混合溶液。
4.如权利要求1所述的半导体结构的制作方法，其特征在于，所述介质层的材质为电学绝缘材质，所述电学绝缘材质为氧化硅或掺杂的氧化硅。
5.如权利要求1所述的半导体结构的制作方法，其特征在于，所述环形通孔的宽度范围为0.1～50微米，所述的环形通孔的宽度是环形通孔的外环宽度与内环宽度的宽度之差的1/2。
6.如权利要求1所述的半导体结构的制作方法，其特征在于，在所述环形通孔形成前，还包括：
对所述半导体衬底远离所述基板的一侧的表面进行减薄的工艺，减薄后的半导体衬底的厚度范围为2～300微米。
7.如权利要求1所述的半导体结构的制作方法，其特征在于，所述焊垫位于所述后段互连层的靠近所述半导体衬底的表面，所述环形通孔为通过对所述半导体衬底进行刻蚀形成。
8.如权利要求1所述的半导体结构的制作方法，其特征在于，所述焊垫位于所述后段互连层的靠近所述基板的表面，所述环形通孔为通过对所述半导体衬底和后段互连层进行刻蚀形成。
9.如权利要求1所述的半导体结构的制作方法，其特征在于，所述介质层还形成在所述半导体衬底的表面，形成所述互连层包括：
对位于所述沟槽一侧的介质层进行刻蚀，在所述介质层内形成互连层开口，所述互连层开口与所述沟槽相连通；
在所述互连层开口和沟槽内填充金属，在所述互连层开口和沟槽内形成互连层，所述互连层与位于所述沟槽另一侧的介质层齐平。
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