CN101404279A - 一种多芯片3d堆叠封装结构 - Google Patents

一种多芯片3d堆叠封装结构 Download PDF

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CN101404279A
CN101404279A CNA2008102025135A CN200810202513A CN101404279A CN 101404279 A CN101404279 A CN 101404279A CN A2008102025135 A CNA2008102025135 A CN A2008102025135A CN 200810202513 A CN200810202513 A CN 200810202513A CN 101404279 A CN101404279 A CN 101404279A
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stacking
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李云芳
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Huaya Microelectronics Shanghai Inc
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Abstract

本发明涉及一种多芯片3D堆叠封装结构，包括一个主芯片和至少一个辅助芯片，所述主芯片和辅助芯片分别具有各自的电路面和与该电路面相对的背面；所述辅助芯片堆叠在所述主芯片上；在所述主芯片的电路面上设有主焊垫，所述辅助芯片的电路面上设有辅助焊垫，所述辅助焊垫通过金属线与所述主焊垫相连。采用上述多芯片3D堆叠封装结构，将视频处理主芯片进行设计，使之可以在一个封装体内将多个辅助芯片全部通过内部导线连接，在双列直插式封装内完成三颗芯片的功能整合，芯片的高成度为客户缩小了线路板面积，缩减了生产厂商的生产成本，同时减少了信号的传输延迟，提高了系统的性能，同时系统板以及模块封装尺寸小，具有质量轻的优势。

Description

一种多芯片3D堆叠封装结构
技术领域
本发明涉及一种集成电路封装结构，特别涉及一种双列直插式封装的多芯片3D堆叠集成电路封装结构，可以用来封装多个半导体芯片。
背景技术
以往系统中的视频处理芯片和组成系统必须的flash和DRAM芯片都是单独封装成独立IC，封装完成后由生产厂商上板组成系统。这种系统结构在线路板设计上浪费空间，并在信号传输中存在信号延迟等问题，成本上也比较高。而采用Flash和DRAM多芯片堆叠封装的一般为高端的BGA或者QFP，这两种封装在线路板设计时必须使用双面板，整机系统成本较高。
发明内容
本发明所要解决的技术问题是提供一种多芯片3D堆叠封装结构，以解决目前多芯片封装结构空间较大、信号传输性能不佳以及封装制造成本高昂的技术问题。
为了实现上述目的，本发明的技术方案如下：
一种多芯片3D堆叠封装结构，包括一个主芯片和至少一个辅助芯片，所述主芯片和辅助芯片分别具有各自的电路面和与该电路面相对的背面；所述辅助芯片堆叠在所述主芯片上；在所述主芯片的电路面上设有主焊垫，所述辅助芯片的电路面上设有辅助焊垫，所述辅助焊垫通过金属线与所述主焊垫相连。
所述辅助芯片为两个以上，包括Flash芯片和DRAM芯片。所述Flash芯片为两个以上，依次堆叠后再堆叠在主芯片上。所述DRAM芯片为两个以上，依次堆叠后再堆叠在主芯片上。
所述金属线优选金线、银线或者铜线。
所述主芯片采用RDL技术对主焊垫进行重新排布。所述辅助芯片采用RDL技术对辅助焊垫进行重新排布。
需要相互连接的主芯片上的主焊垫和辅助芯片上的辅助焊垫之间依次排布，即主芯片与辅助芯片焊垫之间的金属连线不存在交叉现象。
所述芯片之间的堆叠是通过绝缘胶将一芯片的背面固定到另一芯片的电路面上。
另一种多芯片3D堆叠封装结构，包括一个主芯片、一个DRAM辅助芯片和一个Flash辅助芯片，所述主芯片、DRAM辅助芯片和Flash辅助芯片分别具有各自的电路面和与该电路面相对的背面；所述DRAM辅助芯片的背面通过绝缘胶固定在所述主芯片的电路面上；所述Flash辅助芯片的背面通过绝缘胶固定在所述主芯片的电路面上；在所述主芯片的电路面上设有主焊垫，所述DRAM辅助芯片、Flash辅助芯片的电路面上设有辅助焊垫，所述辅助焊垫通过金属线与所述主焊垫按照就近原则相连。
采用上述多芯片3D堆叠封装结构，将视频处理主芯片进行设计，使之可以在一个封装体内将FLASH和DRAM芯片全部通过内部导线连接，在双列直插式封装内完成三颗芯片的功能整合，芯片的高成度为客户缩小了线路板面积，缩减了生产厂商的生产成本，同时减少了信号的传输延迟，提高了系统的性能，同时系统板以及模块封装尺寸小，具有质量轻的优势。由于双列直插式封装的采用可以使线路板设计时采用单面板，大幅减低成本，从根本上解决双面板产品维修困难的问题，从而增强产品的竞争力。
附图说明
图1为本发明的三芯片3D堆叠封装结构的俯视示意图。
图2为本发明的三芯片3D堆叠封装剖面示意图。
图3为本发明的两芯片3D堆叠封装结构的俯视示意图。
图4为本发明的两芯片3D堆叠封装剖面示意图。
图5为本发明的四芯片3D堆叠封装结构的俯视示意图。
图6为本发明的四芯片3D堆叠封装剖面示意图。
具体实施方式
下面根据图1至图6，给出本发明的较佳实施例，并予以详细描述，使能更好地理解本发明的功能、特点。
图1显示的是本发明的三芯片3D堆叠封装结构的俯视示意图，主芯片200的电路面上的外围形成一圈焊垫201，焊垫201既可以是如图1所示的单排分布，也可以采用双排分布(图未示出)。辅助芯片300的上、下两侧分别设有一排焊垫301。辅助芯片400的外围设有多个焊垫401。主芯片200的焊垫201的排布与辅助芯片300的焊垫301以及辅助芯片400的焊垫401的排布是相互匹配的，以保证主芯片200与辅助芯片300、400之间的金属线500连接。在用于连接的焊垫的选择上，采用就近原则，以进一步节省所需金属线的量。在辅助芯片的排布上，也采用有利于就近原则的方式。如本实施例中的辅助芯片400就排布在主芯片200的右上角，辅助芯片400上的四个焊垫401则分别与相离最近的主芯片200的焊垫201连接。
主芯片200在布图设计时需考虑金属线500的排布问题，须将彼此需要连线的焊垫201、301、401按顺序依次排布，即主芯片与辅助芯片焊垫之间的金属连线不存在交叉现象。对于已经存在的芯片，如果不可以直接连接也可以通过RDL技术将已经存在的焊垫重新排布，以保证需相互连接的两者之间可以直接用金属线连接。将辅助芯片200、400的背面通过绝缘胶和主芯片200的正面固定。主芯片200和辅助芯片300，400的连接通过金属线500连接，实现信号联通。金属线最好采用金、银或铜等金属。
图2显示本发明的三芯片3D堆叠封装的剖面示意图。如图2所示，本发明的三芯片3D堆叠封装结构是构建于一个普通的框架100上，用以封装的三个半导体芯片200、300、400，包括直接放置于框架100的中央焊片座101上的主芯片200，以及放置于主芯片200上的辅助的DRAM芯片300，辅助FLASH芯片400。每一个芯片的正面为芯片的电路面，即芯片上形成半导体电路结构以及焊线接触的焊垫的所在面。芯片之间通过金属线实现信号联通，然后主芯片200将信号通过框架100的引脚102与外部互联。
图3显示的是两芯片3D堆叠封装结构的俯视示意图，主芯片200的电路面上的外围形成一圈焊垫201，其中焊垫201既可以是单排分布也可以是双排分布。主芯片200的焊垫201的排布需要配合辅助芯片300的焊垫301的排布，以保证主芯片200和辅助芯片300之间的金属线500连接。主芯片在版图设计时需考虑焊线排布问题，须将彼此需要连线的焊垫按顺序依次排布，对于已经存在的芯片如果不可以直接连接亦可以通过RDL技术将已经存在的焊垫重新排布，以保证两者之间可以直接用金属线连接。辅助芯片的背面通过绝缘胶和主芯片的正面固定。主芯片200和辅助芯片300的连接通过金线500连接，实现信号联通。
图4显示本发明的两芯片3D堆叠封装的剖面示意图。如图所示，本发明的两芯片3D堆叠封装结构是构建于一个普通的框架100上，包括直接放置于框架100的中央焊片座101上的主芯片200，以及放置于主芯片上的辅助的DRAM芯片300。每一个芯片的正面为芯片的电路面，即芯片上形成半导体电路结构以及焊线接触的焊片垫的所在面。芯片之间通过金线实现信号联通，然后主芯片200将信号通过框架100的引脚102与外部互联。
图5显示的是四芯片3D堆叠封装结构的俯视示意图，主芯片200的电路面上的外围形成一圈焊垫201，其中焊垫201既可以是单排分布也可以是双排分布。主芯片的焊垫排布需要配合辅助芯片300，400以及900焊垫的排布，以保证主芯片200和辅助芯片之间的金属线500连接。主芯片在版图设计时需考虑主芯片和所有辅助芯片的焊线排布问题，须将彼此需要连线的焊垫按顺序依次排布，对于已经存在的芯片如果不可以直接连接亦可以通过RDL技术将已经存在的焊垫重新排布，RDL技术可以应用于主芯片，亦可以应该用于辅助芯片，以保证两者之间可以直接用金属线连接。芯片之间的连接通过绝缘胶固定。主芯片200和辅助芯片300，400，900的连接通过金属线500，最好是金线连接，实现信号联通。主芯片和辅助芯片之间的连接是按照就近原则来设计的。当堆叠的辅助芯片增多的时候可以将主芯片的焊垫进行里外两列交错摆放放置在下层的辅助芯片和里面的焊垫相连，放置在上层的辅助芯片和外圈的焊垫相连，保证连线就近原则同时联系之间不交叉。
图6显示本发明的四芯片3D堆叠封装的剖面示意图。如图6所示，本发明的四芯片3D堆叠封装结构是构建于一个普通的框架100上，用以封装的四个半导体芯片，包括直接放置于框架100的中央焊片座101上的主芯片200，以及放置于主芯片上的辅助的DRAM芯片300，辅助FLASH芯片400，以及放置于辅助芯片300之上的芯片900。每一个芯片的正面为芯片的电路面，即芯片上形成半导体电路结构以及焊线接触的焊片垫的所在面。芯片之间通过金线实现信号联通，然后主芯片200将信号通过框架100的引脚102与外部互联。对于本实施例，在保证主芯片与辅助芯片的直接相连的的情况下，芯片900亦可以比芯片300面积大。此时只需要在芯片900和芯片300之间增加一个支撑用的隔离芯片即可。
图中的结构仅为示意图，亦可以根据芯片的焊垫排布改变芯片间的相对位置。对于已经存在的芯片，亦可以采用RDL的技术，将已经存在的焊垫按照需求进行重新排布。在新的位置，重新生成焊垫，以利于封装的生产。可以根据实际情况，对于已经存在的主芯片可以采用RDL技术进行焊垫的重新排布，也可以对Flash或者Dram芯片根据需要采用RDL技术进行焊垫的重新排布。
对于芯片的堆叠数量，亦可以根据实际的需要，增加或者减少叠层芯片的数量。例如可以根据实际应用情况不堆叠Flash芯片，只实现DRAM芯片和视频主芯片的连接。或者按照需要，增加需要堆叠的芯片的数量或者层数，以确保芯片的集成效果。
下面以三芯片3D堆叠封装为例，介绍主要的加工工艺。首先芯片按实际需要进行切割，其次切割后的芯片逐次进行Die Attach，由于有三颗芯片需要进行此工艺，故首先需要进行主芯片200的上片，将主芯片200和框架100用导电胶700(亦可绝缘胶600)连接，完成后进行烘烤进行第二颗辅助芯片300的上片，此时用绝缘胶600将第二颗辅助芯片300粘贴在第一颗主芯片200的上表面，完成后仍需要进行烘烤，烘烤结束后再进行第三颗辅助芯片400的上片，第三颗芯片仍用绝缘胶600粘贴在第一颗主芯片200的上表面，粘结完成后进行烘烤。芯片Die Attach结束后进行金线键合，用金线将主芯片200与辅助芯片300和400实现信号联通，同时将主芯片200的焊垫和框架的引脚102之间用金线实现信号联通。由于精度要求很高，需要采用高精度的金线键合设备进行金线键合，这一步将完成芯片内部全部的电性性能的连接。金线键合结束后进行塑封，用黑胶将已经键合好的主芯片200，辅助芯片300和400以及金线框架包起来以形成封装塑封体800，用以保护芯片以及相关的金线。塑封完成后进行切筋打弯，将每一颗系统高度集成的完整的芯片从框架上独立出来。此即完成了本发明的多芯片3D堆叠结构。
综上所述，本发明提供了一种实用的多芯片3D堆叠封装结构，由于芯片之间的连接采用金线直接的连接，因此可以减少信号的传输延迟，提高系统的性能。由于封装形式采用双列直插式封装结构，故制造成本低廉，返修方便，因此可以提升芯片的操作性以及降低生产成本。因此本发明有很强的实用性。
以上所述的，仅为本发明的较佳实施例，并非用以限定本发明的范围，本发明的上述实施例还可以做出各种变化。例如，两类不同的辅助芯片其实也是可以相互堆叠的。即凡是依据本发明申请的权利要求书及说明书内容所作的简单、等效变化与修饰，皆落入本发明专利的权利要求保护范围。

Claims (10)

1、一种多芯片3D堆叠封装结构，包括一个主芯片和至少一个辅助芯片，所述主芯片和辅助芯片分别具有各自的电路面和与该电路面相对的背面；其特征在于，所述辅助芯片堆叠在所述主芯片上；在所述主芯片的电路面上设有主焊垫，所述辅助芯片的电路面上设有辅助焊垫，所述辅助焊垫通过金属线与所述主焊垫相连。
2、如权利要求1所述的多芯片3D堆叠封装结构，其特征在于，所述辅助芯片为两个以上，包括Flash芯片和DRAM芯片。
3、如权利要求2所述的多芯片3D堆叠封装结构，其特征在于，所述Flash芯片为两个以上，依次堆叠后再堆叠在主芯片上。
4、如权利要求2所述的多芯片3D堆叠封装结构，其特征在于，所述DRAM芯片为两个以上，依次堆叠后再堆叠在主芯片上。
5、如权利要求1所述的多芯片3D堆叠封装结构，其特征在于，所述金属线为金线、银线或者铜线。
6、如权利要求1所述的多芯片3D堆叠封装结构，其特征在于，所述主芯片采用RDL技术对主焊垫进行重新排布。
7、如权利要求1所述的多芯片3D堆叠封装结构，其特征在于，所述辅助芯片采用RDL技术对辅助焊垫进行重新排布。
8、如权利要求1所述的多芯片3D堆叠封装结构，其特征在于，需要相互连接的主芯片上的主焊垫和辅助芯片上的辅助焊垫之间依次排布。
9、如权利要求1至4中任一权利要求所述的多芯片3D堆叠封装结构，其特征在于，所述芯片之间的堆叠是通过绝缘胶将一芯片的背面固定到另一芯片的电路面上。
10、一种多芯片3D堆叠封装结构，包括一个主芯片、一个DRAM辅助芯片和一个Flash辅助芯片，所述主芯片、DRAM辅助芯片和Flash辅助芯片分别具有各自的电路面和与该电路面相对的背面；其特征在于，所述DRAM辅助芯片的背面通过绝缘胶固定在所述主芯片的电路面上；所述Flash辅助芯片的背面通过绝缘胶固定在所述主芯片的电路面上；在所述主芯片的电路面上设有主焊垫，所述DRAM辅助芯片、Flash辅助芯片的电路面上设有辅助焊垫，所述辅助焊垫通过金属线与所述主焊垫按照就近原则相连。
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CN102832189A (zh) * 2012-09-11 2012-12-19 矽力杰半导体技术(杭州)有限公司 一种多芯片封装结构及其封装方法
US8389404B2 (en) 2011-03-07 2013-03-05 Semiconductor Manufacturing International Corp. Semiconductor device and method for manufacturing the same
CN103117263A (zh) * 2013-01-31 2013-05-22 建荣集成电路科技(珠海)有限公司 一种集成电路封装
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US8389404B2 (en) 2011-03-07 2013-03-05 Semiconductor Manufacturing International Corp. Semiconductor device and method for manufacturing the same
CN104769709A (zh) * 2012-07-23 2015-07-08 马维尔国际贸易有限公司 涉及包括多存储器裸片的半导体封装体的方法和布置
CN102832189A (zh) * 2012-09-11 2012-12-19 矽力杰半导体技术(杭州)有限公司 一种多芯片封装结构及其封装方法
CN102832189B (zh) * 2012-09-11 2014-07-16 矽力杰半导体技术(杭州)有限公司 一种多芯片封装结构及其封装方法
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CN103117263A (zh) * 2013-01-31 2013-05-22 建荣集成电路科技(珠海)有限公司 一种集成电路封装
CN106098672A (zh) * 2016-06-20 2016-11-09 东莞市联洲知识产权运营管理有限公司 一种改进的集成电路封装
CN110518003A (zh) * 2019-08-30 2019-11-29 甬矽电子(宁波)股份有限公司 芯片封装结构和芯片封装方法

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