CN102668071B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN102668071B
CN102668071B CN201080050383.3A CN201080050383A CN102668071B CN 102668071 B CN102668071 B CN 102668071B CN 201080050383 A CN201080050383 A CN 201080050383A CN 102668071 B CN102668071 B CN 102668071B
Authority
CN
China
Prior art keywords
power supply
pattern
gnd
terminal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201080050383.3A
Other languages
English (en)
Chinese (zh)
Other versions
CN102668071A (zh
Inventor
星聪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Publication of CN102668071A publication Critical patent/CN102668071A/zh
Application granted granted Critical
Publication of CN102668071B publication Critical patent/CN102668071B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/658—Shapes or dispositions of interconnections for devices provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
CN201080050383.3A 2009-11-11 2010-11-02 半导体装置 Expired - Fee Related CN102668071B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2009258195 2009-11-11
JP2009-258195 2009-11-11
JP2010240054A JP2011124549A (ja) 2009-11-11 2010-10-26 半導体装置
JP2010-240054 2010-10-26
PCT/JP2010/006472 WO2011058718A1 (en) 2009-11-11 2010-11-02 Semiconductor apparatus

Publications (2)

Publication Number Publication Date
CN102668071A CN102668071A (zh) 2012-09-12
CN102668071B true CN102668071B (zh) 2016-08-17

Family

ID=43797617

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080050383.3A Expired - Fee Related CN102668071B (zh) 2009-11-11 2010-11-02 半导体装置

Country Status (4)

Country Link
US (1) US9252098B2 (enExample)
JP (1) JP2011124549A (enExample)
CN (1) CN102668071B (enExample)
WO (1) WO2011058718A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI554174B (zh) * 2014-11-04 2016-10-11 上海兆芯集成電路有限公司 線路基板和半導體封裝結構
JP2016134543A (ja) * 2015-01-21 2016-07-25 セイコーエプソン株式会社 半導体モジュール、半導体装置、及び電気光学装置
US10707159B2 (en) 2015-08-31 2020-07-07 Aisin Aw Co., Ltd. Semiconductor device, chip module, and semiconductor module
CN106211556B (zh) * 2016-07-28 2019-03-19 Oppo广东移动通信有限公司 印刷电路板及具有其的电子装置
JP6799430B2 (ja) * 2016-10-04 2020-12-16 株式会社Ｊｏｌｅｄ 半導体装置及び表示装置
TWI615927B (zh) * 2017-07-14 2018-02-21 矽品精密工業股份有限公司 電子封裝件暨基板結構及其製法
JP6817906B2 (ja) * 2017-07-27 2021-01-20 京セラ株式会社 配線基板
JP7120309B2 (ja) * 2018-07-10 2022-08-17 株式会社アイシン 回路モジュール及び電源チップモジュール

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479758B1 (en) * 2000-01-21 2002-11-12 Kabushiki Kaisha Toshiba Wiring board, semiconductor package and semiconductor device
US20030051910A1 (en) * 2001-09-20 2003-03-20 Dyke Peter D. Van Electrical and physical design integration method and apparatus for providing interconnections on first level ceramic chip carrier packages
US7075185B2 (en) * 2004-09-14 2006-07-11 Hewlett-Packard Development Company, L.P. Routing vias in a substrate from bypass capacitor pads

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5904499A (en) * 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
JP4365166B2 (ja) 2003-08-26 2009-11-18 新光電気工業株式会社 キャパシタ、多層配線基板及び半導体装置
JP4674850B2 (ja) * 2005-02-25 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置
US8786072B2 (en) * 2007-02-27 2014-07-22 International Rectifier Corporation Semiconductor package
JP5049717B2 (ja) * 2007-09-21 2012-10-17 新光電気工業株式会社 多層配線基板
JP2009258195A (ja) 2008-04-14 2009-11-05 Hitachi High-Technologies Corp プロキシミティ露光装置、プロキシミティ露光装置の基板移動方法、及び表示用パネル基板の製造方法
JP5534699B2 (ja) 2009-04-02 2014-07-02 株式会社東芝 Ｘ線診断装置及び画像処理装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6479758B1 (en) * 2000-01-21 2002-11-12 Kabushiki Kaisha Toshiba Wiring board, semiconductor package and semiconductor device
US20030051910A1 (en) * 2001-09-20 2003-03-20 Dyke Peter D. Van Electrical and physical design integration method and apparatus for providing interconnections on first level ceramic chip carrier packages
US7075185B2 (en) * 2004-09-14 2006-07-11 Hewlett-Packard Development Company, L.P. Routing vias in a substrate from bypass capacitor pads

Also Published As

Publication number Publication date
JP2011124549A (ja) 2011-06-23
WO2011058718A1 (en) 2011-05-19
US9252098B2 (en) 2016-02-02
CN102668071A (zh) 2012-09-12
US20120211897A1 (en) 2012-08-23

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C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160817

Termination date: 20191102