CN102629587A - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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CN102629587A
CN102629587A CN2011103794663A CN201110379466A CN102629587A CN 102629587 A CN102629587 A CN 102629587A CN 2011103794663 A CN2011103794663 A CN 2011103794663A CN 201110379466 A CN201110379466 A CN 201110379466A CN 102629587 A CN102629587 A CN 102629587A
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pixel electrode
electrode
substrate
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array base
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李润复
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to US13/806,182 priority patent/US9147697B2/en
Priority to PCT/CN2012/084404 priority patent/WO2013075591A1/zh
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    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps

Abstract

本发明涉及液晶显示器技术领域，具体公开了一种阵列基板及其制作方法、显示装置。该阵列基板的制作方法包括：步骤S1、在基板上形成栅电极、栅线和公共电极；步骤S2、在完成步骤S1的基板上依次形成栅绝缘层和有源层；步骤S3、在完成步骤S2的基板上形成源漏电极层；步骤S4、在完成步骤S3的基板上形成钝化层，并在所述钝化层上形成过孔；步骤S5、在完成步骤S4的基板上形成像素电极，其通过过孔与源漏电极层中的漏电极连接；其中，所述形成像素电极的过程包括：初次刻蚀工艺、灰化工艺和二次刻蚀工艺。本发明通过形成具有微小图案的像素电极，提高了液晶面板的透过率和亮度，改善了斑和波纹等不良，提高了液晶面板的显示品质。

Description

阵列基板及其制作方法、显示装置
技术领域
本发明涉及液晶显示器技术领域，特别涉及一种阵列基板及其制作方法、显示装置。
背景技术
薄膜晶体管液晶显示(Thin Film Transistor Liquid CrystalDisplay，TFT-LCD)技术在近些年来发展迅速，液晶显示器在正面观看画面显示效果很好，而从侧面观看就会出现变色。广视角(WideViewing Angle)技术由于降低了侧面看屏幕产生的变色程度，而成为新的发展趋势。ADSDS(Advanced Super Dimension Switch)，简称ADS，即高级超维场转换技术是液晶界为解决大尺寸、高清晰度桌面显示器和液晶电视应用而开发的广视角技术。其通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而提高了液晶工作效率并增大了透光效率。高级超维场开关技术可以提高TFT-LCD产品的画面品质，具有高分辨率、高透过率、低功耗、宽视角、高开口率、低色差、无挤压水波纹(push Mura)等优点。
如图1所示，ADS模式的液晶面板包括彩膜基板12和阵列基板，阵列基板包括位于下部的形成于基板1上的透明氧化铟锡(ITO)公共电极(Vcom，可视为板状电极)3，和位于上部的钝化层(Passivation)7上的像素(Pixel，可视为狭缝状电极)电极8’。其中像素电极8’通过曝光、显影、刻蚀和剥离形成图案(Pattern)。彩膜基板12和阵列基板之间发生多维电场后在大部分领域上使光透过，从而可以实现高亮度的广视角。ADS模式液晶面板的透过率与像素电极8’的间距(Pitch)a相关。
目前的液晶面板其像素电极的间距a一般是8～10um，像素电极的间距a等于像素电极的宽度(CD)b与像素电极之间的间隙(Spacer)c之和。当像素电极的间距a为10um时，像素电极的宽度b为4um，像素电极之间的间隙c为6um；当间距为8um，像素电极的宽度b为2.6um，像素电极之间的间隙c为5.4um时，液晶面板的亮度特性较好。当像素电极的间距a为6um，像素电极的宽度b为2um，间隙c为4um时，液晶面板的亮度特性非常好，但由于现有的曝光机能够曝光的宽度在3.0-5.0um之间，因此工艺上要实现像素电极的宽度b小于3um较难，随着像素电极宽度的变化液晶面板容易产生斑或波纹(Mura)等不良，降低液晶面板的显示品质。
如图2所示，示出了液晶面板的透过率与像素电极的宽度b之间的关系，随着间距a＝b+c逐渐变小，液晶面板的亮度(即透过率)会增加；虽然亮度在增加，但维持亮度均一性的工艺范围在逐渐减小。
再如图3所示，示出了透过率的变化随像素电极宽度b的变化仿真数据。图中两条曲线分别代表像素电极的间距a为8um和像素电极的间距a为10um时的情形。从图中可以看出，当宽度b的增加百分比相同的情况下，像素电极的间距a为8um与像素电极的间距a为10um的液晶面板相比，透过率随间距变化量的变化较大，容易产生斑或波纹(Mura)等现象。
结合图2和图3中两个曲线图可知，像素电极的间距a越小，液晶面板的亮度越好；在同样的像素电极的间距a的情况下，像素电极的宽度b越小，液晶面板的亮度越好。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是如何形成尺寸更小的像素电极，以提高显示装置的透过率，改善斑或波纹现象。
(二)技术方案
为了解决上述技术问题，本发明实施例首先提供了一阵列基板的制作方法，包括：
步骤S1、在基板上形成栅电极、栅线和公共电极；
步骤S2、在完成步骤S1的基板上依次形成栅绝缘层和有源层；
步骤S3、在完成步骤S2的基板上形成源漏电极层；
步骤S4、在完成步骤S3的基板上形成钝化层，并在所述钝化层上形成过孔；
步骤S5、在完成步骤S4的基板上形成像素电极，所述像素电极通过过孔与源漏电极层中的漏电极连接；其中，所述形成像素电极的过程包括：初次刻蚀工艺、灰化工艺和二次刻蚀工艺。
在进一步的技术方案中，所述步骤S5具体包括：
步骤S51、在所述钝化层上依次沉积透明导电膜和光刻胶；
步骤S52、对所述光刻胶进行曝光和显影；
步骤S53、对步骤S52之后的透明导电膜进行第一次刻蚀；
步骤S54、对步骤S53之后的光刻胶进行灰化处理；
步骤S55、对步骤S54之后的透明导电膜进行第二次刻蚀；
步骤S56、对步骤S55之后的光刻胶进行剥离处理，所述透明导电膜形成像素电极。
在进一步的技术方案中，所述步骤S5中形成的像素电极的间距为4.5-6um，形成的像素电极的宽度为1.5-2um。
在进一步的技术方案中，所述步骤S5中形成的像素电极的间距为4.5um，形成的像素电极的宽度为1.5um。
为了解决上述技术问题，本发明实施例还提供了一种阵列基板，包括：基板，形成于所述基板上的栅电极、栅线和公共电极，形成于所述基板上并覆盖所述栅电极、栅线和公共电极的栅绝缘层，依次形成在所述栅绝缘层上并位于栅电极之上的有源层和源漏电极层，形成在所述基板上的钝化层，所述钝化层上形成有过孔，形成在所述钝化层上并通过过孔与源漏电极层中的漏电极连接的像素电极。
在进一步的技术方案中，所述像素电极的间距为4.5-6um，所述像素电极的宽度为1.5-2um。
在进一步的技术方案中，所述像素电极的间距为4.5um，所述像素电极的宽度为1.5um。
为了解决上述技术问题，本发明实施例还提供了一种显示装置，包括上述阵列基板。
(三)有益效果
上述技术方案具有如下有益效果：在形成像素电极时，通过在初次刻蚀工艺之后追加灰化工艺和二次刻蚀工艺，使得像素电极的图案更微小，从而提高了显示装置的亮度和透过率，改善了斑和波纹等不良，提高了液晶面板的显示品质。
附图说明
图1是现有技术中ADS模式的液晶面板的结构示意图；
图2是现有技术中透过率随像素电极的宽度变化的曲线图；
图3是现有技术中透过率的变化随像素电极宽度的变化量变化的曲线图；
图4是本发明实施例的阵列基板的制作方法流程图；
图5是图4中步骤S5的流程图；
图6a-图6f是步骤S5的各个步骤对应的结构图；
图7是本发明实施例的阵列基板的结构示意图；
其中，1：基板；2：栅电极；31：透明电极；32：公共电极线；4：栅绝缘层；5：有源层；6：源漏电极层；7：钝化层；8，8’：像素电极；9：ITO导电膜；10：光刻胶；11：掩模板；12：彩膜基板。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
实施例一
如图4所示，为本发明实施例的阵列基板的制作方法流程图，并结合图7所示，本方法包括以下步骤：
步骤S1、在基板1上形成透明电极31，并沉积金属薄膜，通过构图工艺形成栅电极2、栅线(未示出)和公共电极线32；其中透明电极31和公共电极线32构成ITO公共电极；
本步骤中的金属薄膜可以采用Mo，Cu，Al或铝镍合金及其组合物组成；基板1可以为玻璃基板、树脂基板等等；
步骤S2、在完成步骤1的基板上连续沉积栅绝缘层4和非晶硅薄膜，通过构图工艺在栅绝缘层4上形成有源层5；
本步骤中栅绝缘层4的材料一般选用氮化硅或氧化硅等，用于形成有源层5的非晶硅薄膜包括a-Si非晶硅薄膜和n+a-Si非晶硅薄膜；
步骤S3、在完成步骤S2的基板上沉积金属薄膜，通过构图工艺形成源漏电极层6，同时将n+a-Si非晶硅薄膜的暴露部分完全刻蚀掉，将a-Si非晶硅薄膜的暴露部分刻蚀掉一部分，从而形成TFT沟道；
步骤S4、在完成步骤S3的基板上沉积钝化层7，并在钝化层7上形成过孔(未标示)；
步骤S5、在完成步骤S4的基板上形成像素电极8，像素电极8通过过孔与源漏电极层6中的漏电极连接；其中，所述形成像素电极8的过程至少包括：初次刻蚀工艺、灰化工艺和二次刻蚀工艺。
上述步骤中所涉及的构图工艺至少包括：涂覆、掩模曝光、显影、刻蚀、剥离等一系列过程。
如图5所示，该步骤S5具体包括：
步骤S51、在钝化层7上依次沉积透明导电膜和光刻胶(Photoresist，PR)10；如图6a所示；其中透明导电膜可以是氧化铟锡(ITO)导电膜或铟锌氧化物(IZO)导电膜等，本实施例以ITO导电膜9为例进行说明。
步骤S52、采用掩模板11对光刻胶10进行曝光和显影；如图6b所示；
步骤S53、对步骤S52之后的ITO导电膜9进行第一次刻蚀；如图6c所示；
步骤S54、对步骤S53之后的光刻胶10进行灰化处理；如图6d所示；
步骤S55、对步骤S54之后的ITO导电膜9进行第二次刻蚀；如图6e所示；
步骤S56、对步骤S55之后的光刻胶10进行剥离处理，得到ITO导电膜9制作的具有微小图案的像素电极8，如图6f所示。
在第一次刻蚀工艺之后追加灰化工艺和二次刻蚀工艺，最后形成的像素电极8的间距能够达到4.5-6um，优选地，为4.5um；像素电极8的宽度能够达到1.5-2um，优选地，为1.5um；像素电极8之间的间隙能够达到3-4um，优选地，为3um；经试验证明，与现有技术相比，液晶面板的亮度特性能够改善20％-30％，并且提高了透过率，改善了斑或波纹等现象。
实施例二
如图7所示，本发明还提供了一种阵列基板，包括基板1，形成于基板1上的栅电极2、栅线和公共电极，形成在基板1上的栅绝缘层4，栅绝缘层4覆盖在栅电极2、栅线和公共电极上；依次形成在栅绝缘层4上并位于栅电极2之上的有源层5和源漏电极层6，形成在基板1上的钝化层7，钝化层7上形成有过孔，形成在钝化层7上并通过过孔与源漏电极层6中的漏电极连接的像素电极8。其中公共电极包括透明电极31和公共电极线32；
其中，像素电极8的间距为4.5-6um，优选地，为4.5um；像素电极8的宽度为1.5-2um，优选地，为1.5um；像素电极8之间的间隙为3-4um，优选地，为3um。
实施例三
本发明实施例还提供了一种显示装置，包括液晶显示装置以及其他类型的显示装置。其中，液晶显示装置可以是液晶面板、液晶电视、手机、液晶显示器等，其包括彩膜基板、以及上述实施例中的阵列基板。上述其他类型显示装置，比如电子纸，其不包括彩膜基板，但是包括上述实施例中的阵列基板。
本发明的各个实施例均适用于ADS型液晶显示装置以及平面转换(In-Plane Switching，IPS)型液晶显示装置。
由以上实施例可以看出，本发明实施例在形成像素电极时，通过在初次刻蚀工艺之后追加灰化工艺和二次刻蚀工艺，使得像素电极的图案更微小，从而提高了显示装置的亮度和透过率，改善了斑和波纹等不良，提高了液晶面板的显示品质。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和变型，这些改进和变型也应视为本发明的保护范围。

Claims (8)

1.阵列基板的制作方法，其特征在于，包括：
步骤S1、在基板上形成栅电极、栅线和公共电极；
步骤S2、在完成步骤S1的基板上依次形成栅绝缘层和有源层；
步骤S3、在完成步骤S2的基板上形成源漏电极层；
步骤S4、在完成步骤S3的基板上形成钝化层，并在所述钝化层上形成过孔；
步骤S5、在完成步骤S4的基板上形成像素电极，所述像素电极通过过孔与源漏电极层中的漏电极连接；其中，所述形成像素电极的过程包括：初次刻蚀工艺、灰化工艺和二次刻蚀工艺。
2.如权利要求1所述的阵列基板的制作方法，其特征在于，所述步骤S5具体包括：
步骤S51、在所述钝化层上依次沉积透明导电膜和光刻胶；
步骤S52、对所述光刻胶进行曝光和显影；
步骤S53、对步骤S52之后的透明导电膜进行第一次刻蚀；
步骤S54、对步骤S53之后的光刻胶进行灰化处理；
步骤S55、对步骤S54之后的透明导电膜进行第二次刻蚀；
步骤S56、对步骤S55之后的光刻胶进行剥离处理，所述透明导电膜形成像素电极。
3.如权利要求1或2所述的阵列基板的制作方法，其特征在于，所述步骤S5中形成的像素电极的间距为4.5-6um，形成的像素电极的宽度为1.5-2um。
4.如权利要求3所述的阵列基板的制作方法，其特征在于，所述步骤S5中形成的像素电极的间距为4.5um，形成的像素电极的宽度为1.5um。
5.如权利要求1-4任一项所述的方法制作的阵列基板，其特征在于，包括：基板，形成于所述基板上的栅电极、栅线和公共电极，形成于所述基板上并覆盖所述栅电极、栅线和公共电极的栅绝缘层，依次形成在所述栅绝缘层上并位于栅电极之上的有源层和源漏电极层，形成在所述基板上的钝化层，所述钝化层上形成有过孔，形成在所述钝化层上并通过过孔与源漏电极层中的漏电极连接的像素电极。
6.如权利要求5所述的阵列基板，其特征在于，所述像素电极的间距为4.5-6um，所述像素电极的宽度为1.5-2um。
7.如权利要求6所述的阵列基板，其特征在于，所述像素电极的间距为4.5um，所述像素电极的宽度为1.5um。
8.显示装置，其特征在于，包括权利要求5-7任一项所述的阵列基板。
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