CN102576698A - 具有增强的接地接合可靠性的引线框封装 - Google Patents

具有增强的接地接合可靠性的引线框封装 Download PDF

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Publication number
CN102576698A
CN102576698A CN2010800427454A CN201080042745A CN102576698A CN 102576698 A CN102576698 A CN 102576698A CN 2010800427454 A CN2010800427454 A CN 2010800427454A CN 201080042745 A CN201080042745 A CN 201080042745A CN 102576698 A CN102576698 A CN 102576698A
Authority
CN
China
Prior art keywords
pad
die attach
attach pad
encapsulation
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010800427454A
Other languages
English (en)
Chinese (zh)
Inventor
邵卫·李
埃因新·吴
赤锡·刘
义金·李
李汉明@尤金·李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of CN102576698A publication Critical patent/CN102576698A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07511—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07531—Techniques
    • H10W72/07532—Compression bonding, e.g. thermocompression bonding
    • H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
CN2010800427454A 2009-10-19 2010-10-08 具有增强的接地接合可靠性的引线框封装 Pending CN102576698A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/581,609 US8093707B2 (en) 2009-10-19 2009-10-19 Leadframe packages having enhanced ground-bond reliability
US12/581,609 2009-10-19
PCT/US2010/052061 WO2011049764A2 (en) 2009-10-19 2010-10-08 Leadframe packages having enhanced ground-bond reliability

Publications (1)

Publication Number Publication Date
CN102576698A true CN102576698A (zh) 2012-07-11

Family

ID=43878665

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010800427454A Pending CN102576698A (zh) 2009-10-19 2010-10-08 具有增强的接地接合可靠性的引线框封装

Country Status (5)

Country Link
US (1) US8093707B2 (https=)
JP (1) JP2013508974A (https=)
CN (1) CN102576698A (https=)
TW (1) TWI515855B (https=)
WO (1) WO2011049764A2 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110115063A1 (en) * 2009-11-18 2011-05-19 Entropic Communications, Inc. Integrated Circuit Packaging with Split Paddle
US20110140253A1 (en) * 2009-12-14 2011-06-16 National Semiconductor Corporation Dap ground bond enhancement
US9337240B1 (en) * 2010-06-18 2016-05-10 Altera Corporation Integrated circuit package with a universal lead frame
TWI489607B (zh) * 2010-11-23 2015-06-21 登豐微電子股份有限公司 封裝結構
CN102800765A (zh) * 2012-03-21 2012-11-28 深圳雷曼光电科技股份有限公司 Led封装结构及其封装工艺
US9147656B1 (en) * 2014-07-11 2015-09-29 Freescale Semicondutor, Inc. Semiconductor device with improved shielding
US9922904B2 (en) 2015-05-26 2018-03-20 Infineon Technologies Ag Semiconductor device including lead frames with downset
US10249556B1 (en) * 2018-03-06 2019-04-02 Nxp B.V. Lead frame with partially-etched connecting bar
US20190287918A1 (en) * 2018-03-13 2019-09-19 Texas Instruments Incorporated Integrated circuit (ic) packages with shields and methods of producing the same
CN109192715B (zh) * 2018-09-20 2024-03-22 江苏长电科技股份有限公司 引线框结构、封装结构及其制造方法
US20240162121A1 (en) * 2022-11-16 2024-05-16 Texas Instruments Incorporated Integrated circuit package with wire bond
JPWO2024166846A1 (https=) * 2023-02-08 2024-08-15
US20250105196A1 (en) * 2023-09-27 2025-03-27 Wolfspeed, Inc. Semiconductor Die Bonding

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297918A (ja) * 1998-04-10 1999-10-29 Nec Corp リードフレーム及び半導体装置及び半導体装置の製造方法
US20020024122A1 (en) * 2000-08-25 2002-02-28 Samsung Electronics Co., Ltd. Lead frame having a side ring pad and semiconductor chip package including the same
US20030205790A1 (en) * 1996-10-25 2003-11-06 Hinkle S. Derek Multi-part lead frame with dissimilar materials
CN2831428Y (zh) * 2005-01-06 2006-10-25 威盛电子股份有限公司 引脚架封装体
US7205180B1 (en) * 2003-07-19 2007-04-17 Ns Electronics Bangkok (1993) Ltd. Process of fabricating semiconductor packages using leadframes roughened with chemical etchant

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US5328079A (en) * 1993-03-19 1994-07-12 National Semiconductor Corporation Method of and arrangement for bond wire connecting together certain integrated circuit components
JP3074264B2 (ja) * 1997-11-17 2000-08-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
US6398556B1 (en) * 1998-07-06 2002-06-04 Chi Fai Ho Inexpensive computer-aided learning methods and apparatus for learners
JP3062691B1 (ja) * 1999-02-26 2000-07-12 株式会社三井ハイテック 半導体装置
WO2001009953A1 (en) * 1999-07-30 2001-02-08 Amkor Technology, Inc. Lead frame with downset die pad
US6424024B1 (en) * 2001-01-23 2002-07-23 Siliconware Precision Industries Co., Ltd. Leadframe of quad flat non-leaded package
US20020096766A1 (en) * 2001-01-24 2002-07-25 Chen Wen Chuan Package structure of integrated circuits and method for packaging the same
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
TW552689B (en) * 2001-12-21 2003-09-11 Siliconware Precision Industries Co Ltd High electrical characteristic and high heat dissipating BGA package and its process
WO2003079407A2 (en) * 2002-03-12 2003-09-25 Fairchild Semiconductor Corporation Wafer-level coated copper stud bumps
US7229906B2 (en) * 2002-09-19 2007-06-12 Kulicke And Soffa Industries, Inc. Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine
WO2004053973A1 (en) * 2002-12-10 2004-06-24 Infineon Technolgies Ag Method of packaging integrated circuits, and integrated circuit packages produced by the method
TWI250632B (en) * 2003-05-28 2006-03-01 Siliconware Precision Industries Co Ltd Ground-enhancing semiconductor package and lead frame
KR100536898B1 (ko) * 2003-09-04 2005-12-16 삼성전자주식회사 반도체 소자의 와이어 본딩 방법
US7214606B2 (en) * 2004-03-11 2007-05-08 Asm Technology Singapore Pte Ltd. Method of fabricating a wire bond with multiple stitch bonds
JP4252563B2 (ja) * 2005-07-05 2009-04-08 株式会社ルネサステクノロジ 半導体装置
US8937393B2 (en) * 2007-05-03 2015-01-20 Stats Chippac Ltd. Integrated circuit package system with device cavity

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030205790A1 (en) * 1996-10-25 2003-11-06 Hinkle S. Derek Multi-part lead frame with dissimilar materials
JPH11297918A (ja) * 1998-04-10 1999-10-29 Nec Corp リードフレーム及び半導体装置及び半導体装置の製造方法
US20020024122A1 (en) * 2000-08-25 2002-02-28 Samsung Electronics Co., Ltd. Lead frame having a side ring pad and semiconductor chip package including the same
US7205180B1 (en) * 2003-07-19 2007-04-17 Ns Electronics Bangkok (1993) Ltd. Process of fabricating semiconductor packages using leadframes roughened with chemical etchant
CN2831428Y (zh) * 2005-01-06 2006-10-25 威盛电子股份有限公司 引脚架封装体

Also Published As

Publication number Publication date
JP2013508974A (ja) 2013-03-07
TWI515855B (zh) 2016-01-01
US20110089556A1 (en) 2011-04-21
TW201125092A (en) 2011-07-16
WO2011049764A3 (en) 2011-11-17
WO2011049764A2 (en) 2011-04-28
US8093707B2 (en) 2012-01-10

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Application publication date: 20120711