CN2831428Y - 引脚架封装体 - Google Patents
引脚架封装体 Download PDFInfo
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- CN2831428Y CN2831428Y CNU2005200160596U CN200520016059U CN2831428Y CN 2831428 Y CN2831428 Y CN 2831428Y CN U2005200160596 U CNU2005200160596 U CN U2005200160596U CN 200520016059 U CN200520016059 U CN 200520016059U CN 2831428 Y CN2831428 Y CN 2831428Y
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Abstract
本实用新型是有关于一种引脚架封装体,其包括有:一晶片、一引脚架、复数个焊线、及一绝缘材料。其中引脚架包括有一晶片载垫、复数个引脚、复数个信号接垫及复数个非信号接垫。信号接垫及非信号接垫分别位于信号引脚及非信号引脚的下方。而非信号接垫具有其各别孔洞连接至电路板的非信号平面。信号接垫具有一向其相邻的非信号接垫延伸结构。藉由增加信号接垫的尺寸,信号接垫与电路板中非信号平面之间的电容效应因而增加。此增加的电容效应可补偿焊线所产生的电感效应,在射频应用上可改善信号传递路径的响应行为。
Description
技术领域
本实用新型是关于焊线接合式引脚架封装体(wire-bonding type-leadframe package)。特别是关于一种可改善焊线接合式引脚架封装体电气特性的引脚接垫接合结构。
背景技术
现代电子产品基本上都含有一半导体晶片(chip)以及一作为电性连接至该晶片的载板(carrier)。在目前将晶片与载板电性连接的技术中,主要是利用以下三种技术:焊线接合制程(wire-bonding process)、覆晶制程(flip chip process)及胶带自动接合制程(tape-automated-bonding,TAB)。在基板为引脚架(lead-frame)的应用中,焊线接合技术是最被广泛采用的技术。然而,此封装体的焊线(bonding wire)会引起一寄生电感,对于射频(radio frequency)产品需应用在数GHz的操作频率下,此寄生电感的影响变得越显著。寄生电感对电路电气特性会有不利的影响,因此有必要发展出一种可以降低寄生电感及改善在高频率之下的频率响应的解决方式。
图1A说明在射频电路应用上的一传统平面型无引脚接脚封装体(quadflat non-lead package,QFN package)的剖面示意图。图1B与图1C分别为图1A中一单一信号源的接合结构的立体图与俯视图。如图1A、图1B及图1C所示,该晶片封装体100包含有:一晶片110、一引脚架(lead-frame)120、复数个焊线(bonding wire)130、以及一绝缘材料(insulation material)140。引脚架120具有一晶片载垫(diepad)121、复数个接地引脚(ground lead)122及复数信号引脚(signal lead)123。接地引脚122及信号引脚123平均分布在晶片载垫121的周围。晶片110由一粘胶(adhesive glue)固定在晶片载垫121上。焊线130在一焊线接合制程中将晶片110分别电性连接至引脚122及123。晶片载垫121与接地引脚122经由一接地接垫(ground pad)181、一晶片载垫承载平台(die padlanding)及一接地孔(ground via)160电性连接至接地平面170。绝缘材料140包覆晶片110、引脚架120及焊线130。晶片载垫121、封装体100上的接地引脚122及信号引脚123以焊接方式固定在电路板190上。
图1D说明在图1A所示封装体之中一单一信号源(single ended mode)的接合结构的俯视图。在传统接垫设计中,信号接垫(signal pad)182位于信号引脚123的下方,且信号引脚的形状对应于信号接垫182。类似地,接地接垫181位于接地引脚122的下方,且接地引脚的形状对应于接地接垫181。接地引脚181电性连接至一位于晶片载垫121下方的承载平台,再经由接地孔160电性连接至接地平面170。
图2A是在封装体中一差动信号源(differential mode)的接合结构的立体示意图。图2B是在封装体中一差动信号源的接合结构的俯视图。一差动信号源包含有一传输正信号的传输线231及一传输负信号的传输线231。此传输信号具有相同的振幅但相反的相位。此二差动信号源传输线231的端点阻抗相差约有100欧姆(Ohms)。在一具有差动信号源的封装体中,此二信号引脚223彼此相邻。对于一信号引脚223而言,其一侧为另一信号引脚223,而其相对侧为一相邻的接地引脚222。在信号引脚223的下方有一信号接垫282;类似地,在接地引脚222的下方有一接地接垫281。接地接垫281与信号接垫282的大小及形状分别对应于接地引脚222与信号引脚223。接地接垫281电性连接至一位于晶片载垫221的下方的承载平台,再经由接地孔160电性连接至接地平面170。
发明内容
有鉴于此,本实用新型提出一接垫接合结构,可提高焊线接合式封装体的电气特性。
依据本实用新型的目的,本实用新型揭露一较佳实施例,一种引脚架封装体,其至少包括:一晶片载垫;一晶片,承载于该晶片载垫上;复数个信号引脚及复数个非信号引脚;复数个焊线,分别连接该晶片至该复数个引脚;一基板,具有复数个接垫配置于该基板的一上表面,其中该接垫包括有:复数个信号接垫,分别位于该信号引脚的下方;及复数个非信号接垫,分别位于该非信号引脚的下方;其中至少一个信号接垫具有一结构向至少一相邻的非信号接垫延伸,且该结构重叠于部分该相邻的非信号引脚但不接触该相邻的非信号接垫与非信号引脚;而该相邻的非信号接垫经由一孔洞连接至该基板上的一非信号平面;以及一绝缘材料,包覆该引脚、该晶片、以及该焊线。
以上的概述及随后的实施例说明,为使本实用新型的特征及目的更能清楚揭示,而非如申请专利范围般将本实用新型限制于其所揭露的范围。可以理解的是以上的概述及随后的实施例说明是提供申请专利范围更具体的解释与了解。
附图说明
经由以下各图示相互对照比较,可以进一步明了本实用新型的优点与特征。图式中所揭露的具体实施例以及在实施方式中所对应的说明,可以明了本实用新型的精神与范围。
图1A说明在射频电路应用上的一传统平面型无引脚接脚封装体(quadflat non-lead package,QFN package)的剖面示意图。
图1B说明在图1A中一共平面的单一信号源的焊线接合结构的立体图。
图1C说明在图1A中一共平面的单一信号源的焊线接合结构的俯视图。
图1D说明在图1A中一单一信号源的引脚接垫接合结构的俯视图。
图2A说明在一封装体中一差动信号源的接合结构的立体示意图。
图2B说明在一封装体中一差动信号源的接合结构的俯视图。
图3A说明依据本实用新型的第一具体实施例的俯视图,具有一延伸T型接垫。
图3B说明依据本实用新型的第一具体实施例的立体图,具有一延伸T型接垫。
图4A说明第一具体实施例与先前技术的基频(S11)频率响应。
图4B说明第一具体实施例与先前技术在史密斯图上的频率响应。
图5A说明依据本实用新型的第二具体实施例的立体图,具有一延伸L型接垫。
图5B说明依据本实用新型的第二具体实施例的俯视图,具有一延伸L型接垫。
图6A说明依据本实用新型的第三具体实施例的立体图,具有一延伸L型接垫及数层阶梯状传输线。
图6B说明依据本实用新型的第三具体实施例的俯视图,具有一延伸L型接垫及数层阶梯状传输线。
图7A说明第二具体实施例、第三具体实施例与先前技术的基频(S11)频率响应。
图7B说明第二具体实施例、第三具体实施例与先前技术在史密斯图上的频率响应。
100:封装体
110:晶片
120:引脚架(lead-frame)
121:晶片载垫(die pad)
122:信号引脚(signal lead)
123:接地引脚(ground lead)
130:焊线(bonding wire)
140:绝缘材料(insulation material)
160:接地孔(ground via)
170:接地平面(ground plane)
181:接地接垫(ground pad)
182:信号接垫(signal pad)
190:电路板
210:晶片
221:晶片载垫(die pad)
222:接地引脚(ground lead)
223:信号引脚(signal lead)
230:焊线
231:一组差动传输线(a pair of differential transmission line)
281:接地接垫(ground pad)
282:信号接垫(signal pad)
322:接地引脚
323:信号引脚
360:接地孔
370:接地平面
381:接地接垫
382:信号接垫
401:习知的单一信号源封装结构的频率响应
402:依据本实用新型的第一实施例的频率响应
403:习知的单一信号源封装结构在史密斯图的特征响应
404:依据本实用新型的第一实施例在史密斯图的特征响应
522:非信号引脚
523:信号引脚
531:一组差动信号传输线
560:接地孔
570:接地平面
581:非信号接垫
582:信号接垫
622:非信号引脚
623:信号引脚
631:一组差动信号传输线
632:多阶阻抗传输线
670:接地平面
681:非信号接垫
682:信号接垫
701:习知的差动信号源封装结构的频率响应
702:依据本实用新型的第二实施例的频率响应
703:依据本实用新型的第三实施例的频率响应
704:习知的差动信号源封装结构在史密斯图的特征响应
705:依据本实用新型的第二实施例在史密斯图的特征响应
706:依据本实用新型的第三实施例在史密斯图的特征响应
具体实施方式
在依据本实用新型的各具体实施例及其对照的图示中,各主要元件均有标号协助说明。在尽可能清楚辨别下,各图示及说明当中若使用相同的标号代表该元件为相同或其均等物品。
请参阅图3A和图3B所示,图3A是依据本实用新型的第一具体实施例的俯视图,具有一延伸T型接垫。图3B是依据本实用新型的第一具体实施例的立体图。先前技术利用一接地接垫181连接至一位于晶片载垫121下方的承载平台,再以接地孔160电性连接至接地平面170。请参阅图3A与图3B所示,为取代此先前的接地连接线路,本实用新型的第一实施例将此接地接垫381经由各自的接地孔360电性连接至接地平面370。接地接垫381向与晶片110位置相反方向延伸,再各自以接地孔360接地。藉由此创新的接地接垫381设计,会产生多余空间供信号接垫382向其相邻的接地接垫381延伸。信号接垫382延伸至相邻的接地接垫381且重叠在部分相邻的接地引脚322的下方,但不会接触相邻的接地接垫381及接地引脚322。此外,信号接垫382可能只重叠在部分相邻的接地引脚322的下方或是延伸超过此接地引脚322。在本实施例中,一信号引脚323两侧分别相邻的接地引脚322,一信号接垫382分别向两相邻接地引脚322方向延伸,形成一突出的T型信号引脚382。相较于先前技术,此突出的T型信号引脚382具有较大的尺寸,因此增加信号引脚382与接地平面370之间的电容效应。增加的电容效应可以用来补偿焊线130所产生的电感效应,改善线路间的阻抗匹配及提升封装体在高频下的电气特性。本实用新型的另一优点是信号接垫382的尺寸可以弹性调整,藉以达到最佳电气特性。
图4A说明本实用新型第一实施例与如图1D所示的先前技术的电气特性比较。图4A显示上述的单一信号源封装结构的频率响应(S11),其中曲线401代表习知的单一信号源封装结构的频率响应,而曲线402代表依据本实用新型的第一实施例的频率响应。从图中所显示的响应在操作频率范围1~6GHz内,可清楚发现依据本实用新型的第一实施例的响应优于习知的结构,特别是在操作频率较低时。
图4B以史密斯图来说明上述两个结构的特征响应。曲线403代表习知的单一信号源封装结构在史密斯图的响应,而曲线404代表依据本实用新型的第一实施例在史密斯图的特征响应。特征响应位于史密斯图的上半部代表一电感性响应而响应位于史密斯图的下半部代表一电容性响应,因此当其特征响应位于史密斯图的中心点(如图中的1,00所示)代表此时为其特征阻抗匹配最佳的条件。在图4B中,曲线404较曲线403接近史密斯图的中心点,这也代表习知结构的电感性响应被本实用新型所揭示的T型信号接垫所补偿。这也同时说明依据本实用新型的第一实施例可得到较佳的特征阻抗匹配。
图5A说明依据本实用新型的第二实施例的立体图,其具有L型信号接垫。图5B则为依据本实用新型的第二实施例的俯视图。此L型信号接垫可以应用在差动信号源的封装结构上。请参阅图5A及图5B所示,接地接垫581经由各自孔洞560电性连接至接地平面570。二个信号引脚523是位于一焊线接合封装体中相互临近的差动信号源,其各自接触于信号接垫582,而信号接垫582连接至一100Ohm差动信号传输线531,藉以传递信号。在二相邻的信号引脚523的外侧为一相邻的接地引脚522。信号引脚523之下具有信号接垫582。类似地,接地引脚522之下具有接地接垫581。与习知的接垫设计(如图2A与图2B所示)不同的是,此信号接垫582向其相邻的接地接垫581方向延伸且重叠于部分的接地引脚522。然而,需特别注意到此信号接垫582并不接触到接地接垫581或接地引脚522。在此差动信号源线路中产生两个延长的L型信号接垫582。如同在上述说明中所揭露,当信号接垫582尺寸增大时,信号接垫582与接地平面570之间的电容效应会因而增加。此增加的电容效应可补偿焊线130所产生的电感效应。因此,此焊线接合封装体在高频下的电气特性可藉由增大信号接垫582的尺寸获得显著地提升。此外,经由改变信号接垫582的尺寸,可以得到此焊线接合封装体的最佳电气特性。
为了进一步改善此焊线接合封装体的频率响应,一多阶阻抗传输线632可代替一习知的传输线连接至信号接垫682,如图6A与图6B所示的第三实施例。此多阶阻抗传输线632可提供一电感效应,藉以补偿因大尺寸延长L型信号接垫682所产生的过度电容。为了了解此多阶阻抗传输线632对此封装体响应的影响,可参照图7A及图7B。图7A说明不同信号接垫及传输线下的差动信号源封装体的频率响应,包含三个曲线701、702、及703。曲线701表示如图2A与图2B所示的习知的差动信号源结构的响应。曲线702为如图5A与图5B所示的第二实施例的响应。曲线703为如图6A与图6B所示的第三实施例的响应。从图中可以发现,曲线702的响应优于曲线701所代表的习知的差动信号源接合结构的响应。然而,当频率增加后,其改善越不明显。藉由此多阶阻抗传输线可进一步改善其响应。曲线703显示其具有良好响应不会因操作频率不同而有显著改变。其中,最佳响应特性发生在操作频率为5.5GHz时。针对各种所需的操作频率下,可变化L型信号接垫的尺寸及多阶阻抗传输线的尺寸达成其最佳匹配条件。
图7B显示上述三个差动信号源结构在史密斯图上的特征响应。特征响应位于史密斯图的上半部代表一电感性响应而响应位于史密斯图的下半部代表一电容性响应,因此当其特征响应位于史密斯图的中心点(如图中的1,00所示)代表此时为其特征阻抗匹配最佳的条件。曲线705较曲线704接近于史密斯图中心点,因为具有延长的L型信号接垫设计可补偿焊线的寄生电感。再配合多阶阻抗传输线设计,使得曲线706几乎仅位于史密斯图的中心附近,这也代表此第三实施例具有极优异的响应。
本实用新型具有的良好响应对于射频应用是极完美的,特别是在高频下的响应特性。本实用新型仅利用增加信号接垫面积,不但容易实施,更不需要额外的制造成本。
以上的说明及实施例中藉由接地接垫、接地引脚及接地平面为实例使本实用新型的特征及目的能清楚揭示,然而电源接垫、电源引脚及电源平面亦可取代接地接垫、接地引脚及接地平面而达到相同的效果。有鉴于此,以一词“非信号”代表其为一电源或一接地点,是可以为熟悉此技艺者所明了与接受的。
综合以上所述,在一焊线接合封装体中,其接地接垫各自经由其接地孔电性连接至线路板中的接地平面。因此,可节省一部分空间作为相邻的信号接垫向此空间延伸,藉以提供较多的电容效应补偿焊线所产生的寄生电感。在操作频率1~6GHz范围内,其特征阻抗匹配及频率响应可获得明显的改善。此外,藉以在信号接垫及一100Ohm传输线之间加入一多阶阻抗传输线,可进一步改善其特征阻抗的匹配状况。总之,本实用新型所提出的接垫设计使一焊线接合封装体具有良好的响应特性,可适用在射频应用产品中。
尽管本实用新型已以数个实施例揭露如上,然其并非用以限定本实用新型,任何熟习此技艺者,在不脱离本实用新型的精神及范围内,当可作各种的变化与润饰,因此本实用新型的保护范围当视后附的申请专利范围为依据。
Claims (7)
1、一种引脚架封装体,其特征在于其至少包括:
一晶片载垫;
一晶片,承载于该晶片载垫上;
复数个信号引脚及复数个非信号引脚;
复数个焊线,分别连接该晶片至该复数个引脚;
一基板,具有复数个接垫配置于该基板的一上表面,其中该接垫包括有:
复数个信号接垫,分别位于该信号引脚的下方;及复数个非信号接垫,分别位于该非信号引脚的下方;其中至少一个信号接垫具有一结构向至少一相邻的非信号接垫延伸,且该结构重叠于部分该相邻的非信号引脚但不接触该相邻的非信号接垫与非信号引脚;而该相邻的非信号接垫经由一孔洞连接至该基板上的一非信号平面;以及
一绝缘材料,包覆该引脚、该晶片、以及该焊线。
2、根据权利要求1所述的引脚架封装体,其特征在于其中对于一单一信号源的焊线接合式封装体而言,该信号接垫是一T型结构。
3、根据权利要求1所述的引脚架封装体,其特征在于其中对于一差动信号源的焊线接合式封装体而言,该信号接垫是一L型结构。
4、根据权利要求1所述的引脚架封装体,其特征在于其中所述的信号接垫延伸并越过该相邻非信号接垫。
5、根据权利要求1所述的引脚架封装体,其特征在于其中所述的非信号接垫是一接地接垫或一电源接垫,且该非信号引脚是一接地引脚或一电源引脚。
6、根据权利要求1所述的引脚架封装体,其特征在于其中所述的非信号平面是一接地平面或一电源平面。
7、根据权利要求1所述的引脚架封装体,其特征在于其中信号传递是经由一多阶阻抗传输线电性连接至该信号接垫。
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US11/031,659 | 2005-01-06 | ||
US11/031,659 US7247937B2 (en) | 2005-01-06 | 2005-01-06 | Mounting pad structure for wire-bonding type lead frame packages |
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CN102576698A (zh) * | 2009-10-19 | 2012-07-11 | 国家半导体公司 | 具有增强的接地接合可靠性的引线框封装 |
CN104332463A (zh) * | 2013-07-12 | 2015-02-04 | 英飞凌科技奥地利有限公司 | 多芯片器件 |
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WO2020220465A1 (zh) * | 2019-04-29 | 2020-11-05 | 深圳市华星光电技术有限公司 | 印刷电路板及显示装置 |
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US20080182120A1 (en) * | 2007-01-28 | 2008-07-31 | Lan Chu Tan | Bond pad for semiconductor device |
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JP5953703B2 (ja) * | 2011-10-31 | 2016-07-20 | ソニー株式会社 | リードフレームおよび半導体装置 |
JP6128756B2 (ja) * | 2012-05-30 | 2017-05-17 | キヤノン株式会社 | 半導体パッケージ、積層型半導体パッケージ及びプリント回路板 |
US8643168B1 (en) | 2012-10-16 | 2014-02-04 | Lattice Semiconductor Corporation | Integrated circuit package with input capacitance compensation |
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JP3764587B2 (ja) * | 1998-06-30 | 2006-04-12 | 富士通株式会社 | 半導体装置の製造方法 |
JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
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JP2004071670A (ja) * | 2002-08-02 | 2004-03-04 | Fuji Photo Film Co Ltd | Icパッケージ、接続構造、および電子機器 |
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- 2005-04-11 TW TW094111295A patent/TWI278091B/zh active
- 2005-04-15 CN CNU2005200160596U patent/CN2831428Y/zh not_active Expired - Lifetime
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US11310906B2 (en) * | 2019-04-29 | 2022-04-19 | TCL China Star Ovtoelectronics Technology Co., Ltd. | Printed circuit board and display device |
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TWI278091B (en) | 2007-04-01 |
TW200625585A (en) | 2006-07-16 |
US20060145341A1 (en) | 2006-07-06 |
US7247937B2 (en) | 2007-07-24 |
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