CN2570979Y - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

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CN2570979Y
CN2570979Y CN02254294U CN02254294U CN2570979Y CN 2570979 Y CN2570979 Y CN 2570979Y CN 02254294 U CN02254294 U CN 02254294U CN 02254294 U CN02254294 U CN 02254294U CN 2570979 Y CN2570979 Y CN 2570979Y
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徐鑫洲
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Via Technologies Inc
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Abstract

本实用新型涉及一种具有保护电路设计的芯片封装结构,此芯片封装结构是将两成对的接地导线分别配设于一用来传输高频信号的信号导线的两侧,使得高频信号于导线之内传输时不易受到外界的干扰,并可提供多点接地处及较短的电流回流回路,同时将高频信号于信号导线之内传输时所产生的电磁场限制在两成对的接地导线之间,故可缩小电磁场的影响面积,并降低高频信号的插入损耗及返回损耗,有助于提升芯片于封装后的电气效能。

Description

芯片封装结构
技术领域
本实用新型涉及一种芯片封装结构,且特别涉及一种具有保护电路设计的芯片封装结构。
背景技术
随着电子科技产业的突飞猛进,各种具有不同功能的电子产品均逐渐深入到我们的日常生活当中。一般而言,电子产品的内部都配设有集成电路(Integrated Circuit,IC),为了使结构脆弱的集成电路裸芯片(die)能受到有效的保护,并同时使集成电路裸芯片能与外界相互传递信号,常见技术是利用“封装(package)”来达成上述的目的。目前已经研发出的芯片封装技术众多,以芯片接合技术来说,常见的芯片接合技术为打线(Wire Bonding,W/B)、倒装片(Flip Chip,F/C)及卷带式自动接合(Tape Automatic Bonding,TAB)等,其中又以打线(W/B)型态的芯片接合技术最早发展也最为成熟。
就射频电路(RF circuit)及高速电路(high speed circuit)而言,在工作频率及电气效能的考量下,射频电路芯片(die)及高速电路芯片所采用的芯片封装结构,其必须能够提供较大的接地(ground)面积。因此,目前应用于射频电路芯片及高速电路芯片的芯片封装结构包括四方扁平无接脚(Quad Flat No-lead,QFN)及凸块芯片承载器(Bump Chip Carrier,BCC)等型态,其中这两种型态的芯片封装结构均会应用到打线(W/B)型态的芯片接合技术。
请参考图1,其为常见的四方扁平无接脚(QFN)型态的芯片封装结构其剖面示意图。芯片封装结构100主要包括承载器110、芯片120、导线130及封胶(molding compound)140等。首先,承载器110包括一芯片座(die pad)112及多个电极凸块114,而这些电极凸块114环绕于芯片座112的周围。此外,芯片120具有一工作表面(active surface)122及对应的一背面123,而芯片120以其背面123贴附于芯片座112上,其中工作表面122泛指芯片120的具有工作组件(active device)的一面,且芯片120还具有多个焊垫124,其均配置于芯片120的工作表面122。另外,部分导线130的两端分别连接焊垫124及电极凸块114的顶面的接点118,而部分导线130的两端则分别连接焊垫124及芯片座112的顶面的接点116。最后,封胶140包覆芯片120及导线130,并同时暴露出芯片座112的底面及电极凸块114的底面,使得芯片120可经由芯片座112及电极凸块114而与外界作电性连接。值得注意的是,承载器110的芯片座112除了可承载芯片120之外,还可提供较大的接地面积及散热面积。
当射频电路芯片或高速电路芯片采用四方扁平无接脚(QFN)型态的芯片封装结构时,为了保护高频信号于导线之内传递时不会受到外界信号的干扰,同时缩小高频信号于导线之内传递时所产生电磁场的影响面积,故可将成对的接地导线分别配设在高频信号导线的两侧,且分别略平行于高频信号导线,用以作为高频信号导线的保护电路,如图2A--2D所示,其中图2A--2D依序为常见的四种保护电路设计的结构示意图。然而,常见的四种保护电路设计并未能够提供最佳的防护效果至高频信号导线,原因为何将于本实用新型的较佳实施例作详细说明。
发明内容
本实用新型的目的在于提供一种具有保护电路设计的芯片封装结构,可使得高频信号于导线之内传输时较不易受到外界的干扰,并可提供多点接地处及较短的电流回流回路,也可有效缩小高频信号于导线之内传输时所产生电磁场的影响面积,且可有效降低高频信号的插入损耗(insertion loss),使得高频信号能较完整地传输出去,也可有效降低高频信号的返回损耗(returnloss),使得高频信号于导线之内传输时,将有效降低因阻抗不匹配(impedance mismatch)所造成的反射。
基于上述目的,本实用新型提出一种芯片封装结构,此芯片封装结构至少具有一承载器、一芯片、一信号导线、一对第一非信号导线及一对第二非信号导线。首先,承载器具有一信号接点、一对第一非信号接点及一对第二非信号接点,而信号接点、该对第一非信号接点及该对第二非信号接点均配置于承载器的表面,且该对第二非信号接点彼此电性连接。此外,芯片具有一工作表面及对应该工作表面的一背面,而芯片以其背面配置于承载器的表面,且该芯片还具有一信号焊垫、一对第一非信号焊垫及一对第二非信号焊垫,而信号焊垫、该对第一非信号焊垫及该对第二非信号焊垫均配置于芯片的工作表面。另外,信号导线的两端分别连接该信号焊垫及该信号接点。并且,该对第一非信号导线的两端分别连接该对第一非信号焊垫之一及该对第一非信号接点之一,且该对第一非信号导线分别位于信号导线的两侧。而且,该对第二非信号导线的两端分别连接该对第二非信号焊垫之一及该对第二非信号接点之一,且该对第二非信号导线分别位于信号导线及该对第一非信号导线的两侧。
为让本实用新型的上述目的、特征和优点能明显易懂,下文特举一较佳实施例,并配合附图作详细说明如下。
附图说明
图1为常见的四方扁平无接脚(QFN)型态的芯片封装结构其剖面示意图;
图2A--2D为常见的四种保护电路设计的结构示意图;
图3A--3D分别为对应图2A--2D的四种保护电路设计的电磁场分布示意图;
图4为本实用新型的保护电路设计的结构示意图;
图5为图4的保护电路设计的电磁场分布示意图;
图6为常见的四种保护电路设计与本实用新型的保护电路设计的插入损耗的比较图;
图7为常见的四种保护电路设计与本实用新型的保护电路设计的插入损耗的比较表;
图8为常见的四种保护电路设计与本实用新型的保护电路设计的返回损耗的比较图;
图9为常见的四种保护电路设计与本实用新型的保护电路设计的返回损耗的比较表;
图10为另一种可应用本实用新型的保护电路设计的芯片封装结构其剖面示意图;
图11为又一种可应用本实用新型的保护电路设计的芯片封装结构其剖面示意图。标号说明
100:芯片封装结构    110:承载器
112:芯片座          114:电极凸块
116:接点            118:接点
120:芯片            122:作表面
123:背面            124:焊垫
130:导线            140:封胶
212:芯片座          214:电极凸块
216:接点            218:接点
220:芯片            222:工作表面
224:焊垫            230:导线
412:芯片座          414:电极凸块
416:接点            418:接点
420:芯片            422:工作表面
424:焊垫            430:导线
601a--601d:(常见的)插入损耗曲线
602:(本实用新型的)插入损耗曲线
701a--701d:(常见的)返回损耗曲线
702:(本实用新型的)返回损耗曲线
800:芯片封装结构    810:承载器
812:芯片承载结构    814:盆状导电结构
816:接点            818:接点
820:芯片            822:工作表面
823:背面            824:焊垫
830:导线            840:封胶
900:芯片封装结构    910:承载器
916:接地环          918:接点
920:片              922:工作表面
923:背面            924:焊垫
930:导线            940:封胶
具体实施方式
本实用新型的较佳实施例将公开一种保护电路设计,并将的应用于图1所示的四方扁平无接脚(QFN)型态的芯片封装结构之中。值得注意的是,由于上文已针对四方扁平无接脚(QFN)型态的芯片封装结构作详述,故可参考图1及其相关说明,本实用新型的较佳实施例于下文不再重复赘述的。
请同时参考图1、图4,其中图4为本实用新型的保护电路设计的结构示意图。芯片420(即图1的芯片120)贴附于芯片座41 2(即图1的芯片座112)上,并利用打线制作过程(W/B)来形成导线430,并将导线430(即图1的导线130)的两端分别连接芯片420的工作表面422上的焊垫424(即图1的焊垫124)及电极凸块414(即图1的电极凸块114)的顶面所构成的接点418(即图1的接点118),其中信号导线430a的两端分别连接信号焊垫424a及信号接点418a。
请同样参考图4,本实用新型的较佳实施例的保护电路设计是将一成对的接地导线430b分别配设于信号导线430a的两侧,并将另一成对的接地导线430c分别配设于信号导线430a及上述成对的接地导线430b的两侧。值得注意的是,成对的接地导线430b的两端分别连接成对的接地焊垫424b之一及成对的接地接点418b之一,而成对的接地导线430c的两端则分别连接成对的接地焊垫424c之一及成对的接地接点416之一,其中成对的接地接点416均由芯片座412的顶面所构成。
请再参考图4,本实用新型的较佳实施例的保护电路设计乃是将一成对的接地导线430b配设于信号导线430a的两侧,并将另一成对的接地导线430c分别配设于信号导线430a及上述成对的接地导线430b的两侧,且利用此一成对的接地导线430c来连接芯片420的接地焊垫424c及芯片座412的顶面所构成的接地接点416。如此一来,高频信号于信号导线430a之内传输时,其较不易受到外界的干扰,并且信号导线430a将可就近以高弧的接地导线430b作为良好的参考,同时利用两成对的接地导线430b及接地导线430c来提供多点接地处,并利用成对的接地导线430c来提供较短的电流回流回路。此外,高频信号于信号导线430a之内传输时所产生的电磁场将有效限制在两成对的接地导线430b及接地导线430c之间,故可有效缩小电磁场的影响面积,同时降低高频信号的插入损耗及返回损耗,而有助于提升芯片420于封装后的电气效能。
为了比较出常见的四种保护电路设计与本实用新型的保护电路设计之间于结构及功效上的明显差异,下文将配合相关附图来依序简述常见的四种保护电路设计,并将其个别与本实用新型的保护电路设计作比较。
请参考图2A,其为常见的第一种保护电路设计的结构示意图。常见的第一种保护电路设计乃是将一成对的接地导线230b配设于信号导线230a的两侧,并将另一成对的接地导线230c配设于信号导线230a及成对的接地导线230b的两侧。值得注意的是,由于常见的第一种保护电路设计并未提供成对的接地导线(如图4的成对的接地导线430c)来连接芯片220的接地用的焊垫224及芯片座212,因而无法提供较短的电流回流回路,如此将造成较大的插入损耗及返回损耗,使得高频信号在穿越信号导线230a时有较为显著的失真情形。
请参考图2B,其为常见的第二种保护电路设计的结构示意图。常见的第二种保护电路设计乃是将一成对的接地导线230b配设于信号导线230a的两侧,并将另一成对的接地导线230c配设于信号导线230a及成对的接地导线230b的两侧。值得注意的是,常见的第二种保护电路设计虽可提供成对的接地导线230b来连接芯片220的接地用的焊垫224及芯片座212,但也使得成对的接地导线230c均相对远离信号导线230a,如此将无法有效缩小高频信号于信号导线230a之内传输时所产生电磁场的影响面积,反而增加电磁场的影响面积,如第3B图所示。
请参考图2C,其为常见的第三种保护电路设计的结构示意图。常见的第三种保护电路设计乃是将一成对的接地导线230b配设于信号导线230a的两侧,并将一成对的接地导线230c配设于信号导线230a及成对的非信号导线230b的两侧,且将一成对的接地导线230d配设于上述多条导线的两侧。值得注意的是,由于电流经由两成对的接地导线230b及接地导线230c而顺流至外界,接着再经由芯片座212及成对的接地导线230d而逆流回芯片220,然由于两成对的接地导线230b及接地导线230c的截面积大于成对的接地导线230d的截面积,所以部分电流仍将经由接地导线230b或接地导线230c而逆流回芯片220,如此将相对降低两成对的接地导线230b对于信号导线230a的防护效果。
请参考图2D,其为常见的第四种保护电路设计的结构示意图。常见的第四种保护电路设计乃是将一成对的接地导线230b配设于信号导线230a的两侧,并将另一成对的接地导线230c配设于信号导线230a及成对的接地导线230b的两侧。值得注意的是,由于常见的第四种保护电路设计并未提供成对的接地导线(如图4的成对的接地导线430b),并将其配设于信号导线230a的两侧,如此将无法有效缩小高频信号于信号导线230a之内传输时所产生电磁场的影响面积,反而增加电磁场的影响面积,如第3D图所示。
为了比较常见的四种保护电路设计与本实用新型的保护电路设计于不同工作频率时其插入损耗及返回损耗的明显差异,下文将配合相关附图作详细说明。
首先,请同时参考图6及图7,其中图6为常见的四种保护电路设计与本实用新型的保护电路设计的插入损耗的比较图,而图7为常见的四种保护电路设计与本实用新型的保护电路设计的插入损耗的比较表。如图6所示,其中纵坐标是代表插入损耗的强度(magnitude),而横坐标则是代表芯片的工作频率(frequency),且常见的四种保护电路设计的插入损耗曲线依序为曲线601a、曲线601b、曲线601c及曲线601d,而本实用新型的保护电路设计的插入损耗曲线则为曲线602。值得注意的是,当高频信号的插入损耗越小时,那么高频信号的能量损失也将相对较小,如此将可使高频信号能够较为完整地传输出去。
如图6及图7所示,当芯片的工作频率为2.4GHz(十亿赫兹)时,常见的曲线601a、曲线601b、曲线601c及曲线601d所分别对应到的插入损耗的强度依序为-0.128dB(分贝)、-0.117dB、-0.117dB、-0.143dB,而本实用新型的曲线602所对应到的插入损耗的强度仅为-0.114dB,其小于常见的曲线601a、曲线601b、曲线601c及曲线601d所分别对应到的插入损耗的强度。同样如图6及图7所示,当芯片的工作频率提升为5GHz时,常见的曲线601a、曲线601b、曲线601c及曲线601d所对应分别到的插入损耗的强度依序为-0.371dB、-0.333dB、-0.332dB、-0.432dB,而本实用新型的曲线602所对应到的插入损耗的强度仅为-0.315dB,其小于常见的曲线601a、曲线601b、曲线601c及曲线601d所分别对应到的插入损耗的强度。
基于上述在相同的工作频率下,由于本实用新型的保护电路设计所产生插入损耗的强度均小于常见的四种保护电路设计所分别产生插入损耗的强度,故本实用新型的保护电路设计与常见的四种保护电路设计相比之下,本实用新型的保护电路设计将可有效降低高频信号的能量损失,使得高频信号能够较为完整地传输出去。
其次,请同时参考图8及图9,其中图8为常见的四利保护电路设计与本实用新型的保护电路设计的返回损耗的比较图,而图9为常见的四种保护电路设计与本实用新型的保护电路设计的返回损耗的比较表。如图8所示,其中纵坐标是代表返回损耗的强度,而横坐标则是代表芯片的工作频率,且常见的四种保护电路设计的返回损耗曲线依序为曲线701a、曲线701b、曲线701c及曲线701d,而本实用新型的保护电路设计的插入损耗曲线则为曲线702。值得注意的是,当高频信号的返回损耗越小时,将有效降低因阻抗不匹配所造成的反射。
如图8及图9所示,当芯片的工作频率为2.4GHz时,常见的曲线701a、曲线701b、曲线701c及曲线701d所分别对应到的返回损耗的强度依序为-18.26dB、-18.71dB、-18.71dB、-17.17dB,而本实用新型的曲线602所对应到的返回损耗的强度仅为-19.04 dB,其小于常见的曲线701a、曲线701b、曲线701c及曲线701d所分别对应到的返回损耗的强度。同样如图8及图9所示,当芯片的工作频率提升为5GHz时,常见的曲线701a、曲线701b、曲线701c及曲线701d所对应分别到的返回损耗的强度依序为-12.22dB、-12.73dB、-12.73dB、-11.28dB,而本实用新型的曲线602所对应到的返回损耗的强度仅为-13.79dB,其小于常见的曲线701a、曲线701b、曲线701c及曲线701d所分别对应到的返回损耗的强度。
基于上述在相同的工作频率下,由于本实用新型的保护电路设计所产生返回损耗的强度均小于常见的四种保护电路设计所分别产生返回损耗的强度,故本实用新型的保护电路设计与常见的四种保护电路设计相比之下,本实用新型的保护电路设计将可有效减少高频信号的返回损耗,进而有效降低因阻抗不匹配所造成的反射。
然而,本实用新型的较佳实施例的保护线路设计除了可应用在四方扁平无接脚(QFN)型态的芯片封装结构以外,也可应用在凸块芯片承载器(BCC)型态的芯片封装结构(如图10所示),以及采用打线(W/B)制作过程的基板(substrate)型态的芯片封装结构(如图11所示),或是其它采用打线(W/B)制作过程的承载器的芯片封装结构。接下来,下文将配合相关附图来简述本实用新型的保护电路设计可应用的凸块芯片承载器(BCC)型态的芯片封装结构及采用打线(W/B)制作过程的基板型态的芯片封装结构。
首先,请参考同时参考图1、图8,图10为另一种可应用本实用新型的保护电路设计的芯片封装结构其剖面示意图。芯片封装结构800为凸块芯片承载器(BCC)型态的芯片封装结构,由于芯片封装结构800与芯片封装结构100之间最显著的差异在于承载器810与承载器110的结构不同,故以下仅就芯片封装结构800的承载器810来作详细说明。首先,芯片封装结构800的承载器810主要包括一芯片承载结构812及多个盆状导电结构814,而这些盆状导电结构814环绕于芯片承载结构812的周围。此外,芯片承载结构812用以让芯片820的背面823贴附其上,并提供较大的接地面积及散热面积,且芯片承载结构812的顶面构成接点816,其作用与图1的接点116相同,用以连接导线830的一端。另外,盆状导电结构814的内面则构成接点818,其作用与图1的接点118相同,用以连接导线830的一端。并且封胶840包覆芯片820及导线830,且部分封胶840填充于盆状导电结构814的内面所围成的空间,而芯片承载结构212的底面及盆状导电结构214的底面还裸露于封胶840之外。
其次,请参考图11,其为又一种可应用本实用新型的保护电路设计的芯片封装结构其剖面示意图。芯片封装结构900主要包括基板910、芯片920、导线930及封胶940等。
基板910的顶面具有一接地环(或电源环)916,其环绕于芯片920的外围,且接地环(或电源环)916用以构成作为接地用(或电源用)的多个接点,其与图1的芯片座112所构成的接点116具有共同接地(或共同电源)的功能。此外,基板910的顶面还具有多个接点918,其配置于基板910的顶面,且这些接点918环绕于芯片920的外围,并较接地环(或电源环)916相对远离芯片920,而这些接点918的作用与图1的接点118相同。另外,芯片920以其背面923贴附于基板910的顶面,故基板910即是作为芯片920的承载器,且芯片920的工作表面922还配置有多个焊垫924,而部分导线930的两端分别连接焊垫924之一及接地环(或电源环)916之一,且部分导线930的两端则分别连接焊垫924之一及接点918之一,而封胶940则包覆芯片920及导线930。
值得注意的是,本实用新型的较佳实施例除了利用成对的接地导线来缩小高频信号于传输时所产生的电磁场影响之外,也可利用成对的电源导线来取代上述成对的接地导线,因而达到相同的功效,此时须对应改变接地焊垫为电源焊垫,且对应改变接地接点为电源接点。因此,本实用新型的保护电路设计乃是将两成对的「非信号」导线(即成对的接地导线或成对的电源导线)分别配设于信号导线的两侧。此外,本实用新型的较佳实施例所提到的高频信号大致上是指工作频率超过500MHz(百万赫兹)以上的信号,且本实用新型的较佳实施例所提到的高频信号的种类例如为时钟信号、参考信号或其它具有不同功能的信号。
综上所述,本实用新型的保护电路设计主要应用于一采用打线制作过程的承载器型态的芯片封装结构,其是将第一成对的接地导线配设于信号导线的两侧,并同时将第二成对的接地导线配设于信号导线及第一成对的接地导线的两侧,故可利用此二成对的接地导线来防止外界的信号干扰到高频信号的传输,并且信号导线还可就近以邻近且高弧的接地导线来作为良好的参考。此外,由于第二成对的接地导线的两端分别连接芯片的接地用的焊垫及承载器的顶面所构成的接地用的接点,故可提供多点接地处及较短的电流回流回路。另外,本实用新型的保护电路设计还可将高频信号于导线之内传输时所产生的电磁场限制于两成对的接地导线之间,故可缩小电磁场的影响面积,同时降低高频信号的插入损耗及返回损耗,因而有助于提升芯片于封装后的电气效能,使得高频信号在穿越一具有此保护电路设计的芯片封装结构时,将可有效避免其穿越一具有传统保护电路设计的芯片封装结构所可能会发生的失真情形。
虽然本实用新型已以较佳实施例公开如上,然其并非用于限定本实用新型,任何本领域的普通技术人员,在不脱离本实用新型的精神和范围内,可作一些等效变化和变动,因此本实用新型的保护范围以权利要求为准。

Claims (10)

1、一种芯片封装结构,其特征在于,至少包括:
一承载器,具有数个第一接点及数个第二接点,其中这些第一接点及这些第二接点均配置于该承载器的表面,且这些第二接点彼此电性连接,并且这些第二接点较这些第一接点还接近该芯片;
一芯片,具有一工作表面及相对于该工作表面的一背面,其中该芯片以该背面配置于该承载器的表面,而该芯片还具有数个焊垫,且这些焊垫均配置于该芯片的该工作表面;
一信号导线,该信号导线的两端分别连接这些焊垫之一及这些第一接点之一;
一对第一非信号导线,每一该对第一非信号导线的两端分别连接这些焊垫之一及这些第一接点之一,且该对第一非信号导线分别位于该信号导线的两侧;以及
一对第二非信号导线,每一该对第二非信号导线的两端分别连接这些焊垫之一及这些第二接点之一,且该对第二非信号导线分别位于该信号导线及该对第一非信号导线的两侧。
2、如权利要求1所述的芯片封装结构,其特征在于,还包括一封胶,其包覆该芯片、该信号导线、该对第一非信号导线及该对第二非信号导线。
3、如权利要求1所述的芯片封装结构,其特征在于,该对第一非信号导线为接地导线。
4、如权利要求1所述的芯片封装结构,其特征在于,该对第一非信号导线为电源导线。
5、如权利要求1所述的芯片封装结构,其特征在于,该对第二非信号导线为接地导线。
6、如权利要求5所述的芯片封装结构,其特征在于,该承载器还具有一接地环,其配置于该承载器的表面,而该接地环的部分构成这些第二接点。
7、如权利要求1所述的芯片封装结构,其特征在于,该对第二非信号导线为电源导线。
8、如权利要求7所述的芯片封装结构,其特征在于,该承载器还具有一电源环,其配置于该承载器的表面,而该电源环的部分构成这些第二接点。
9、如权利要求1所述的芯片封装结构,其特征在于,该承载器包括一芯片座及数个电极凸块,且这些电极凸块环绕于该芯片座的周围,而该芯片配置于该芯片座的顶面,且该芯片座的顶面构成这些第二接点,而部分这些电极凸块的顶面分别构成这些第一接点。
10、如权利要求1所述的芯片封装结构,其特征在于,该承载器包括一芯片承载结构及数个盆状导电结构,且这些盆状导电结构环绕于该芯片承载结构的周围,而该芯片配置于该芯片承载结构的顶面,且该芯片承载结构的顶面构成这些第二接点,而部分这些盆状导电结构的内面分别构成这些第一接点。
CN02254294U 2002-09-19 2002-09-19 芯片封装结构 Expired - Lifetime CN2570979Y (zh)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100375095C (zh) * 2005-03-24 2008-03-12 威盛电子股份有限公司 中央处理器与北桥芯片共构模块
CN1770971B (zh) * 2004-10-04 2011-06-29 三星电子株式会社 减少电磁干扰的方法及使用该方法的电路连接装置
CN103503133A (zh) * 2011-03-03 2014-01-08 天工方案公司 与线焊盘有关且降低高rf损耗镀覆影响的设备和方法
CN105916290A (zh) * 2016-06-28 2016-08-31 广东欧珀移动通信有限公司 电子产品
CN106802455A (zh) * 2017-03-31 2017-06-06 青岛海信宽带多媒体技术有限公司 一种光模块

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1770971B (zh) * 2004-10-04 2011-06-29 三星电子株式会社 减少电磁干扰的方法及使用该方法的电路连接装置
CN100375095C (zh) * 2005-03-24 2008-03-12 威盛电子股份有限公司 中央处理器与北桥芯片共构模块
CN103503133A (zh) * 2011-03-03 2014-01-08 天工方案公司 与线焊盘有关且降低高rf损耗镀覆影响的设备和方法
CN103503133B (zh) * 2011-03-03 2016-09-28 天工方案公司 与线焊盘有关且降低高rf损耗镀覆影响的设备和方法
CN105916290A (zh) * 2016-06-28 2016-08-31 广东欧珀移动通信有限公司 电子产品
CN106802455A (zh) * 2017-03-31 2017-06-06 青岛海信宽带多媒体技术有限公司 一种光模块

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