CN102543971B - 芯片封装体及其形成方法 - Google Patents

芯片封装体及其形成方法 Download PDF

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CN102543971B
CN102543971B CN201110461727.6A CN201110461727A CN102543971B CN 102543971 B CN102543971 B CN 102543971B CN 201110461727 A CN201110461727 A CN 201110461727A CN 102543971 B CN102543971 B CN 102543971B
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chip
substrate
packing
hole
support blocks
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CN102543971A (zh
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张恕铭
刘沧宇
何彦仕
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种芯片封装体及其形成方法，该芯片封装体包括：一第一芯片；一第二芯片，设置于该第一芯片之上；一孔洞，自该第一芯片的一表面朝向该第二芯片延伸；一导电层，设置于该第一芯片的该表面上，且延伸进入该孔洞而与该第一芯片中的一导电区或掺杂区电性连接；以及一支撑块体，设置于该第一芯片与该第二芯片之间，且该支撑块体完全覆盖该孔洞的一底部。本发明可提升芯片封装体的可靠度。

Description

芯片封装体及其形成方法
技术领域
本发明有关于芯片封装体，且特别是有关于堆叠有至少两芯片的芯片封装体。
背景技术
芯片封装制程是形成电子产品过程中的一重要步骤。芯片封装体除了将芯片保护于其中，使免受外界环境污染外，还提供芯片内部电子元件与外界的电性连接通路。
提高芯片封装体的可靠度与结构稳定性已成为重要课题。
发明内容
本发明一实施例提供一种芯片封装体，包括：一第一芯片；一第二芯片，设置于该第一芯片之上；一孔洞，自该第一芯片的一表面朝向该第二芯片延伸；一导电层，设置于该第一芯片的该表面上，且延伸进入该孔洞而与该第一芯片中的一导电区或掺杂区电性连接；以及一支撑块体，设置于该第一芯片与该第二芯片之间，且该支撑块体完全覆盖该孔洞的一底部。
本发明所述的芯片封装体，还包括：一保护层，设置于该第一芯片的该表面上；以及一导电凸块，设置于该第一芯片的该表面上，且电性连接该导电层。
本发明所述的芯片封装体，还包括一连接块体，设置于该第二芯片与该第一芯片之间，该连接块体连接该第二芯片与该支撑块体。
本发明所述的芯片封装体，其中，该第一芯片包括一控制芯片，而该第二芯片包括一MEMS芯片。
本发明所述的芯片封装体，还包括一绝缘层，位于该导电层与该第一芯片之间。
本发明所述的芯片封装体，该第一芯片包括一MEMS芯片，而该第二芯片包括一控制芯片。
本发明所述的芯片封装体，其中，该第一芯片包括一承载基底及一半导体层，其中该孔洞自该承载基底朝该半导体层延伸，且露出该半导体层中的一掺杂区。
本发明所述的芯片封装体，其中，该支撑块体与该孔洞的一底部隔有一间距而不直接接触该孔洞的该底部。
本发明所述的芯片封装体，还包括一密封环结构，设置于该第一芯片与该第二芯片之间，且该密封环结构设置于该第一芯片及/或该第二芯片的外围之上，而包围该第一芯片及/或该第二芯片上的一元件区。
本发明所述的芯片封装体，其中，该密封环结构包括形成于该第一芯片的该表面上的一第一连接层及形成于该第二芯片上的一第二连接层。
本发明所述的芯片封装体，其中，该第一连接层的材质与该支撑块体的材质相同。
本发明所述的芯片封装体，还包括至少一辅助支撑结构，设置于该第一芯片与该第二芯片之间。
本发明一实施例提供一种芯片封装体的形成方法，包括：提供一第一基底；于该第一基底的一表面上形成一支撑块体；提供一第二基底；将该第二基底接合于该第一基底的该表面上；自该第一基底的一第二表面移除部分的该第一基底以形成朝该第一基底上的该支撑块体延伸的一孔洞，其中该支撑块体完全覆盖该孔洞的一底部；以及于该第一基底的该第二表面上形成一导电层，其中该导电层延伸进入该孔洞，且电性连接该第一基底中的一导电区或掺杂区。
本发明所述的芯片封装体的形成方法，还包括：于该第一基底的该第二表面上形成一保护层，其中该保护层具有一开口，露出部分的该导电层；以及于露出的该导电层之上形成一导电凸块。
本发明所述的芯片封装体的形成方法，还包括切割该第一基底及该第二基底以形成至少一芯片封装体。
本发明所述的芯片封装体的形成方法，还包括：于该第二基底的一表面上形成一连接块体；以及以该连接块体连接该第一基底及该第二基底。
本发明所述的芯片封装体的形成方法，其中，该连接块体直接接合该支撑块体。
本发明所述的芯片封装体的形成方法，还包括于该第一基底与该第二基底之间设置至少一密封环结构，其中该密封环结构包围该第一基底及/或该第二基底上的一元件区。
本发明所述的芯片封装体的形成方法，其中，该密封环结构于将该连接块体直接接合该支撑块体的步骤时形成。
本发明所述的芯片封装体的形成方法，其中，在形成该孔洞之前，还包括薄化该第一基底。
本发明所述的芯片封装体的形成方法，还包括于该第一基底与该第二基底之间设置至少一辅助支撑结构。
本发明所述的芯片封装体的形成方法，其中，该第一基底及该第二基底为两半导体晶片。
本发明所述的芯片封装体的形成方法，还包括于该第一基底与该第二基底之间设置一晶片边缘密封环，该晶片边缘密封环、该第一基底及该第二基底共同形成一空腔。
本发明可提升芯片封装体的可靠度。
附图说明
图1A-1I显示根据本发明一实施例的芯片封装体的制程剖面图。
图2显示根据本发明一实施例的芯片封装体的剖面图。
图3A-3B分别显示根据本发明实施例的芯片封装体的剖面图。
图4A-4E分别显示根据本发明实施例的芯片封装体于切割制程前的俯视示意图。
图5显示根据本发明一实施例的芯片封装体的剖面图。
附图中符号的简单说明如下：
10、20、100：基底；100a、100b：表面；102：连接层；104：绝缘层；106：导电区；108：孔洞；110：绝缘层；112：导电层；114：保护层；116：导电凸块；200：半导体层；200a、200b：表面；202：连接层；204：接合层；206：承载基底；208：孔洞；210：绝缘层；212：导电层；214：保护层；216：导电凸块；300：芯片；300a、300b：表面；302：连接层；306：导电区或掺杂区；400：芯片；400a、400b：表面；402：连接层；410：密封环结构；412：支撑结构；502：空腔；SC：切割道。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的芯片封装体可用以封装各种堆叠芯片。例如，在本发明的芯片封装体的实施例中，其可应用于下述芯片的堆叠封装结构，例如包括各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital oranalog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro Mechanical System；MEMS)、微流体系统(microfluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶片级封装(wafer scale package；WSP)制程对影像感测元件、发光二极管(light-emitting diodes；LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件(surface acoustic wavedevices)、压力感测器(process sensors)喷墨头(ink printer heads)、或功率芯片模组(power IC module)等半导体芯片进行封装。
其中，上述晶片级封装制程主要指在晶片阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体芯片重新分布在一承载晶片上，再进行封装制程，亦可称之为晶片级封装制程。另外，上述晶片级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶片，以形成多层集成电路(multi-layer integrated circuit devices)的芯片封装体。
图1A-1I显示根据本发明一实施例的芯片封装体的制程剖面图。如图1A所示，提供基底10及基底20。基底10及基底20可为两半导体晶片。例如，基底10可为(但不限于)一包含有多个控制集成电路(control IC)的晶片，其上定义有多个预定切割道而将基底10划分成多个区域。这些区域中可分别形成有控制集成电路，其可包含CMOS元件。基底20可为(但不限于)一包含有多个MEMS元件的晶片，其上定义有多个预定切割道而将基底20划分成多个区域。这些区域中可分别形成有MEMS元件。在基底20中，形成有多个MEMS元件运作所需的孔洞或凹槽。
如图1A所示，基底10可包括半导体基底100，其中可形成有至少一导电区106。导电区106例如是一导电垫，其可电性连接半导体基底100中的元件区。例如，导电区106可电性连接半导体基底中的CMOS元件。或者，在另一实施例中，导电区106实质上为一掺杂区。
基底20可包括半导体层200及承载基底206。半导体层200的表面200a与承载基底206之间可形成有一接合层204。例如，在一实施例中，基底20可包括绝缘层上覆半导体基底(SOIsubstrate)。在此情形下，接合层204例如为氧化硅层。
如图1A所示，可于基底100的表面100a上形成连接层102，并可选择性形成绝缘层104于基底100的表面100a。绝缘层104具有露出连接层102的开口。连接层102可用以使基底10与基底20彼此接合。在一实施例中，连接层102的材质可为金属材料，例如金、铜、铝、或其相似物。或者，连接层102的材质可为半导体材料，例如硅、锗、或其相似物。相似地，可于半导体层200的表面200b上形成连接层202。在一实施例中，基底20与基底10可通过彼此间的连接层102及202的互相接合而连接。
如图1B所示，可使基底20与基底10上的连接层彼此对齐接合而连接两基底。连接层102与连接层202之间的接合可为(但不限于)金属与半导体的接合(metal to semiconductor bonding)、金属与金属的接合(metal to metal bonding)、或半导体与半导体的接合(semiconductor to semiconductor bonding)。连接层202可视为连接块体，用以接合基底10与基底20。
在接合基底10与基底20之后，可选择性薄化基底100以利后续制程进行。例如，可以承载基底206为支撑，自基底100的表面100b研磨基底100而将基底100薄化至适合厚度。适合的薄化制程例如是机械研磨或化学机械研磨。
接着，如图1C所示，可例如以微影及蚀刻制程自基底100的表面100b移除部分的基底100以形成朝导电区106及其中一连接层102延伸的孔洞108。在此情形下，连接层102除了用以接合基底20之外，还可用作孔洞108底部下的支撑块体。在一实施例中，支撑块体(连接层102)大抵完全覆盖孔洞108的底部。在一实施例中，支撑块体(连接层102)与孔洞108的底部隔有一间距而不直接接触孔洞108的底部。基底100一般需经薄化，且在基底100中形成孔洞108之后，造成基底100的结构强度下降，使得导电区106容易破裂。由于在本发明实施例中，于孔洞108的底部上覆盖了支撑块体(连接层102)，将有助于增加孔洞108底部的结构强度，可提升芯片封装体的可靠度。因此，在基底10与基底20的接合过程中，孔洞108底部的结构及导电区106将不易断裂。在后续芯片封装体完成之后，支撑块体(连接层102)可继续加强芯片封装体的结构强度，可确保芯片封装体于使用中的运作。
接着，如图1D所示，可选择性于基底100的表面100b上形成绝缘层110。绝缘层110可延伸进入孔洞108之中。绝缘层110例如为环氧树脂、防焊材料、或其他适合的绝缘物质，例如无机材料的氧化硅层、氮化硅层、氮氧化硅层、金属氧化物、或前述的组合；或亦可为有机高分子材料的聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene,BCB,道氏化学公司)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates)等。绝缘层110的形成方式可包含涂布方式，例如旋转涂布(spin coating)、喷涂(spraycoating)、或淋幕涂布(curtain coating)，或其他适合的沉积方式，例如，液相沉积、物理气相沉积、化学气相沉积、低压化学气相沉积、等离子增强式化学气相沉积、快速热化学气相沉积、或常压化学气相沉积等制程。然应注意的是，在一实施例中，绝缘层110的形成并非必须，在后续形成的导电层与基底间无短路疑虑的情形下，可不需形成绝缘层110。
接着，如图1E所示，移除绝缘层110位于孔洞108底部上的部分以使部分的导电区106露出。
如图1F所示，于基底100的表面100b上形成导电层112。导电层112可延伸进入孔洞108之中而与导电区106电性连接。导电层112的材质可包括铜、铝、金、铂、或其相似物。导电层112的形成方式可为物理气相沉积、溅镀、化学气相沉积、电镀、或无电镀等。可通过微影及蚀刻制程将导电层112图案化。
接着，如图1 G所示，可于基底100的表面100b上形成保护层114。保护层114具有露出导电层112的开口。接着，如图1H所示，于露出的导电层112上形成导电凸块116。
如图1I所示，可接着沿着预定切割道SC切割基底10与20以形成至少一芯片封装体。如图1I所示，在一实施例中，芯片封装体包括下芯片(切割后的部分的基底10)；设置于下芯片上的上芯片(切割后的部分的基底20)；自下芯片的表面100b朝向上芯片延伸的孔洞108；设置于下芯片的表面100b上，且延伸进入孔洞108而与下芯片中的导电区106或掺杂区电性连接的导电层110；以及设置于下芯片与上芯片之间的支撑块体(102)，且支撑块体(102)大抵完全覆盖孔洞108的底部。在一实施例中，连接层102为具导电性的材质(如，金属材料)，而导电区106通过基底100中的导电线路而与连接层102电性连接。连接层202亦可具有导电性的材质(如，半导体材料)。因此，下芯片的导电区106可通过支撑块体而与上芯片的半导体层200中的一掺杂区电性连接。
本发明实施例可有许多变化。例如，孔洞108不限于形成在基底10之中。图2显示根据本发明一实施例的芯片封装体的剖面图，其中相同或相似的标号用以标示相同或相似的元件。在图2的实施例中，孔洞208自上芯片的承载基底206的表面朝下芯片延伸。导电层212形成于孔洞208的侧壁上的绝缘层210之上而与半导体层200电性接触。在一实施例中，半导体层200可包括掺杂区，且此掺杂区可与导电层212电性接触。在图2的实施例中，孔洞208下方的连接层202可用作支撑块体，可于与下芯片的连接层102接合的制程过程中，保护孔洞208底部上的结构免于破裂。相似地，在一实施例中，下芯片的导电区106可电性连接导电层212。相似地，上芯片上亦可设置有保护层214及与导电层212电性连接的导电凸块216。
图3A-3B分别显示根据本发明实施例的芯片封装体的剖面图。在图3A的实施例中，芯片300与芯片400分别通过其上的连接层302及402而彼此接合。孔洞308自芯片300的表面300a朝表面300b延伸而露出导电区或掺杂区306。连接层302及402可共同形成连接块体，用以接合芯片300与芯片400。孔洞308的底部下方的连接层302及402还可用作支撑块体，用以强化孔洞308底部下方的结构。
应注意的是，孔洞308的底部下方的支撑块体不限于同时用作连接块体。例如，在图3B的实施例中，孔洞308的底部下方的支撑块体仅包括连接层302。在此情形下，连接层302仅用作支撑块体而非用作连接芯片300与芯片400的连接块体。
图4A-4E分别显示根据本发明实施例的芯片封装体于切割制程前的俯视示意图，其用以显示连接层102的位置。图4A的实施例类似于图1A-1I的实施例。在此实施例中，连接层102覆盖于导电区106之上。请同时参照图1I，在导电区106上的连接层102除了连结上下两芯片之外，还可用作孔洞下方的支撑块体，可确保芯片封装体于制作过程及使用期间，免于受到外力而破裂。此外，在形成支撑块体时，还可同时形成出部分的密封环结构410。在一实施例中，连接层102可覆盖于预定切割道SC之上而围绕待切割的芯片。在上下芯片接合之后，部分的连接层102及202可共同形成密封环结构。密封环结构可设置于下芯片及/或上的外围之上，而包围下芯片及/或上芯片上的元件区，可保护元件区免受外界环境的影响。例如，密封环结构有助于阻挡水气进入芯片封装体之中。
在图4B实施例中，密封环结构410可不及于预定切割道SC，可有利于切割制程的进行。
在图4C实施例中，密封环结构410向内延伸而覆盖导电区106。因此，在此实施例中，密封环结构可同时用作接合块体与孔洞下的支撑块体。应注意的是，在此实施例中，为避免发生短路，可不移除导电区106上方的绝缘层。即，使连接层102不电性接触导电区106。在此情形下，导电区106可通过其他线路而与上芯片电性连接。
在图4D及图4E的实施例中，可于该上芯片与下芯片之间形成辅助支撑结构412，其可用以辅助上芯片与下芯片的接合与加强对上芯片的支撑。辅助支撑结构412可由部分的连接层102及202所构成。辅助支撑结构412可为环形结构(如图4D)或柱状结构(如图4E)。
图5显示根据本发明一实施例的芯片封装体的剖面图，其中相同或相似的标号用以标示相同或相似的元件。在此实施例中，可于基底10与基底20之间设置晶片边缘密封环，其可设置于两基底的外围上。晶片边缘密封环、基底20、及基底10共同形成一空腔502。晶片边缘密封环亦可由部分的连接层102及202所构成。
在本发明实施例中，通过支撑块体、连接块体、及或密封环结构的设置，可提高芯片封装体的可靠度与结构稳定性。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (23)

1.一种芯片封装体，其特征在于，包括：
一第一芯片；
一第二芯片，设置于该第一芯片之上；
一孔洞，自该第一芯片的一下表面朝向该第二芯片延伸；
一导电层，设置于该第一芯片的该下表面上，且延伸进入该孔洞而与该第一芯片中的一导电区或掺杂区电性连接；以及
一支撑块体，设置于该第一芯片与该第二芯片之间，该支撑块体露出该第一芯片的一上表面，且该支撑块体完全覆盖该孔洞的一底部。
2.根据权利要求1所述的芯片封装体，其特征在于，还包括：
一保护层，设置于该第一芯片的该下表面上；以及
一导电凸块，设置于该第一芯片的该下表面上，且电性连接该导电层。
3.根据权利要求1所述的芯片封装体，其特征在于，还包括一连接块体，设置于该第二芯片与该第一芯片之间，该连接块体连接该第二芯片与该支撑块体。
4.根据权利要求1所述的芯片封装体，其特征在于，该第一芯片包括一控制芯片，而该第二芯片包括一MEMS芯片。
5.根据权利要求1所述的芯片封装体，其特征在于，还包括一绝缘层，位于该导电层与该第一芯片之间。
6.根据权利要求1所述的芯片封装体，其特征在于，该第一芯片包括一MEMS芯片，而该第二芯片包括一控制芯片。
7.根据权利要求6所述的芯片封装体，其特征在于，该第一芯片包括一承载基底及一半导体层，其中该孔洞自该承载基底朝该半导体层延伸，且露出该半导体层中的一掺杂区。
8.根据权利要求1所述的芯片封装体，其特征在于，该支撑块体与该孔洞的一底部隔有一间距而不直接接触该孔洞的该底部。
9.根据权利要求1所述的芯片封装体，其特征在于，还包括一密封环结构，设置于该第一芯片与该第二芯片之间，且该密封环结构设置于该第一芯片及/或该第二芯片的外围之上，而包围该第一芯片及/或该第二芯片上的一元件区。
10.根据权利要求9所述的芯片封装体，其特征在于，该密封环结构包括形成于该第一芯片的该下表面上的一第一连接层及形成于该第二芯片上的一第二连接层。
11.根据权利要求10所述的芯片封装体，其特征在于，该第一连接层的材质与该支撑块体的材质相同。
12.根据权利要求1所述的芯片封装体，其特征在于，还包括至少一辅助支撑结构，设置于该第一芯片与该第二芯片之间。
13.一种芯片封装体的形成方法，其特征在于，包括：
提供一第一基底；
于该第一基底的一第一表面上形成一支撑块体，该支撑块体露出该第一表面；
提供一第二基底；
将该第二基底接合于该第一基底的该第一表面上；
自该第一基底的一第二表面移除部分的该第一基底以形成朝该第一基底上的该支撑块体延伸的一孔洞，其中该支撑块体完全覆盖该孔洞的一底部；以及
于该第一基底的该第二表面上形成一导电层，其中该导电层延伸进入该孔洞，且电性连接该第一基底中的一导电区或掺杂区。
14.根据权利要求13所述的芯片封装体的形成方法，其特征在于，还包括：
于该第一基底的该第二表面上形成一保护层，其中该保护层具有一开口，露出部分的该导电层；以及
于露出的该导电层之上形成一导电凸块。
15.根据权利要求13所述的芯片封装体的形成方法，其特征在于，还包括切割该第一基底及该第二基底以形成至少一芯片封装体。
16.根据权利要求13所述的芯片封装体的形成方法，其特征在于，还包括：
于该第二基底的一表面上形成一连接块体；以及
以该连接块体连接该第一基底及该第二基底。
17.根据权利要求16所述的芯片封装体的形成方法，其特征在于，该连接块体直接接合该支撑块体。
18.根据权利要求16所述的芯片封装体的形成方法，其特征在于，还包括于该第一基底与该第二基底之间设置至少一密封环结构，其中该密封环结构包围该第一基底及/或该第二基底上的一元件区。
19.根据权利要求18所述的芯片封装体的形成方法，其特征在于，该密封环结构于将该连接块体直接接合该支撑块体的步骤时形成。
20.根据权利要求13所述的芯片封装体的形成方法，其特征在于，在形成该孔洞之前，还包括薄化该第一基底。
21.根据权利要求13所述的芯片封装体的形成方法，其特征在于，还包括于该第一基底与该第二基底之间设置至少一辅助支撑结构。
22.根据权利要求13所述的芯片封装体的形成方法，其特征在于，该第一基底及该第二基底为两半导体晶片。
23.根据权利要求22所述的芯片封装体的形成方法，其特征在于，还包括于该第一基底与该第二基底之间设置一晶片边缘密封环，该晶片边缘密封环、该第一基底及该第二基底共同形成一空腔。
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