CN102456404A - NVM (nonvolatile memory) storage device, memory controller and data storage method - Google Patents
NVM (nonvolatile memory) storage device, memory controller and data storage method Download PDFInfo
- Publication number
- CN102456404A CN102456404A CN2010105279215A CN201010527921A CN102456404A CN 102456404 A CN102456404 A CN 102456404A CN 2010105279215 A CN2010105279215 A CN 2010105279215A CN 201010527921 A CN201010527921 A CN 201010527921A CN 102456404 A CN102456404 A CN 102456404A
- Authority
- CN
- China
- Prior art keywords
- memory
- data
- order
- physical blocks
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses an NVM (nonvolatile memory) storage device, a memory controller and a data storage method. The NVM storage device comprises a connector, an energy storage circuit, a power supply converting and supply circuit, an NVM module, a memory controller and a buffer memory, wherein the power supply converting and supply circuit is used for converting an output voltage from the energy storage circuit into a first voltage applied to the NVM module and a second voltage applied to the memory controller and the buffer memory; the memory controller is used for writing data temporarily stored in the buffer memory into the NVM module in a special writing mode when receiving a detection signal (for indicating that an input voltage is persistently less than a preset voltage during a preset time period), or a detection signal (for indicating the inactivated state of the connector), or a suspend-mode signal, a warm reset signal or a hot reset signal received from a host system.
Description
Technical field
The present invention relates to a kind of nonvolatile memory stores device, Memory Controller and date storage method, and be particularly related to a kind of nonvolatile memory stores device, Memory Controller and date storage method that can be when the nonvolatile memory stores device cuts off the power supply the data in the memory buffer be write to non-volatile memory module.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, make the consumer also increase rapidly the demand of storage medium.Because nonvolatile memory has that data are non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., suitable portable use, the most suitable being used on the portable battery-powered product of this type.Dish is exactly a kind of with the memory storage of NAND flash memory (Flash Memory) as storage medium with oneself.For example, (Universal Serial Bus, USB), the user plugs carry-on dish in main frame easily, to carry out the transmission of numerical data through USB.
Owing to write the transmission speed of the speed of data to flash memory far below the USB that is connected with main frame, therefore, in general, memory buffer can be configured in the nonvolatile memory stores device, with the temporary data that come from main frame.Particularly; Assign when main frame and to write instruction with the data desiring to write during to the nonvolatile memory stores device; Memorizer control circuit (also being called Memory Controller) meeting indication soon after data are temporary in memory buffer has been accomplished the message that writes instruction and has been replied to main frame; So that main frame can continue to carry out next running, promote operational paradigm thus.
Yet because dish is to operate in the power supply that main frame provides through USB with oneself, therefore, if in memory buffer, still have when the user pulls out carry-on dish under the data conditions from main frame, the data that are temporary in the memory buffer will be lost.The base this, the data that how when the nonvolatile memory stores device cuts off the power supply, will be temporary in the memory buffer write in the flash memory, are the problems that these those skilled in the art endeavour.
Summary of the invention
The present invention provides a kind of storage system, Memory Controller and date storage method, and its data that can when outage, will be temporary in the memory buffer write in the non-volatile memory module.
Exemplary embodiment of the present invention proposes a kind of nonvolatile memory stores device, and it comprises connector, tank circuit, power source conversion and supply circuit, non-volatile memory module, Memory Controller and memory buffer.Connector is in order to be electrically connected to host computer system.Tank circuit is in order to receive input voltage and output voltage is provided.Power source conversion and supply circuit electrically connect tank circuit and in order to output voltage is converted to first voltage and second voltage.Non-volatile memory module electrically connects power source conversion and supply circuit and operates in first voltage.Memory Controller electrically connects connector, tank circuit and power source conversion and supply circuit and operates in second voltage.Memory buffer is in order to temporal data.Memory Controller writes to non-volatile memory module in order to the data that when receiving signal, will be temporarily stored in the memory buffer, and wherein this signal is in order to indicate above-mentioned input voltage in one section Preset Time, to continue less than the detection signal of predeterminated voltage or in order to non-activation (inactive) the status detection signal of indication connector or be the park mode signal that from host computer system, is received, warm reset signal or warm reset signal.
Exemplary embodiment of the present invention proposes a kind of Memory Controller, and it comprises HPI, memory interface, memory management circuitry and memory buffer.HPI is in order to be electrically connected to host computer system.Memory interface is in order to be electrically connected to non-volatile memory module.Memory management circuitry electrically connects HPI and memory interface.Memory buffer electrically connects memory management circuitry and in order to the temporary data that come from host computer system.Memory management circuitry writes to non-volatile memory module in order to the data that when receiving signal, will be temporarily stored in the memory buffer.In addition, wherein memory management circuitry also is included in the switch in the tank circuit in order to unlatching.
Exemplary embodiment of the present invention proposes a kind of date storage method, is used for a non-volatile memory module.This date storage method comprises judges whether the input voltage that comes from host computer system continues less than predeterminated voltage in Preset Time; And when the input voltage that comes from host computer system continues less than predeterminated voltage, the data that are temporarily stored in the memory buffer are write to non-volatile memory module in Preset Time.
Exemplary embodiment of the present invention proposes a kind of date storage method, is used for a non-volatile memory module.This date storage method comprises: the unactivated state that judges whether to detect connector; And when detecting the unactivated state of connector, the data that are temporarily stored in the memory buffer are write to non-volatile memory module.
Exemplary embodiment of the present invention proposes a kind of date storage method, is used for a non-volatile memory module.This date storage method comprises: judge whether from host computer system, to receive park mode signal, warm reset signal or warm reset signal; And when from host computer system, receiving park mode signal, warm reset signal or warm reset signal, the data that are temporarily stored in the memory buffer are write to non-volatile memory module.
Based on above-mentioned, the data that the storage system of exemplary embodiment of the present invention, Memory Controller and date storage method can will be temporary in the memory buffer when the nonvolatile memory stores device cuts off the power supply write in the flash memory.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and conjunction with figs. elaborates as follows.
Description of drawings
Figure 1A is host computer system and the nonvolatile memory stores device that exemplary embodiment illustrates according to the present invention.
Figure 1B is computing machine, input/output device and the nonvolatile memory stores schematic representation of apparatus that exemplary embodiment illustrated according to the present invention.
Fig. 1 C is host computer system and the nonvolatile memory stores schematic representation of apparatus that another exemplary embodiment illustrated according to the present invention.
Fig. 2 is the summary calcspar that illustrates the nonvolatile memory stores device shown in Figure 1A.
Fig. 3 is the summary calcspar of the Memory Controller that exemplary embodiment illustrated according to the present invention.
Fig. 4 and Fig. 5 are the example schematic of the diode-capacitor storage module that exemplary embodiment illustrated according to the present invention.
Fig. 6～Fig. 8 is the example that writes data to non-volatile memory module that exemplary embodiment illustrated according to the present invention.
Fig. 9 is the synoptic diagram of the tank circuit that exemplary embodiment illustrated according to the present invention.
Figure 10 is the process flow diagram of the date storage method that exemplary embodiment illustrated according to the present invention.
Figure 11 is the process flow diagram of the date storage method that another exemplary embodiment illustrated according to the present invention.
Figure 12 is the process flow diagram of the date storage method that another exemplary embodiment illustrated according to the present invention.
[main element symbol description]
1000: host computer system
1100: computing machine
1102: microprocessor
1104: RAS
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: carry-on dish
1214: storage card
1216: solid state hard disc
1310: digital camera
The 1312:SD card
The 1314:MMC card
1316: memory stick
The 1318:CF card
1320: embedded memory storage
100: the nonvolatile memory stores device
102: connector
104: Memory Controller
106: non-volatile memory module
108: tank circuit
110: power source conversion and supply circuit
202: memory management circuitry
204: HPI
206: memory interface
208: memory buffer
210: bug check and correcting circuit
304 (0)～304 (R): physical blocks
402: the data field
404: the spare area
406: system region
408: replace the district
510 (0)～510 (H): blocks
Vin: input voltage
Vout: output voltage
D: diode
R1: first resistance
R2: second resistance
S: switch
C: capacitance group
GND: earth terminal
Embodiment
Generally speaking, nonvolatile memory stores device (also claiming the nonvolatile memory stores system) comprises non-volatile memory module and Memory Controller (also claiming memorizer control circuit).Usually the nonvolatile memory stores device is to use with host computer system, so that host computer system can write to the nonvolatile memory stores device or reading of data from the nonvolatile memory stores device with data.
Figure 1A is host computer system and the nonvolatile memory stores device that exemplary embodiment illustrated according to the present invention.
Please with reference to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprise microprocessor 1102, RAS (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 like Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, nonvolatile memory stores device 100 is to electrically connect through data transmission interface 1110 other elements with host computer system 1000.Can data be write to nonvolatile memory stores device 100 or reading of data from nonvolatile memory stores device 100 through microprocessor 1102, RAS 1104 with the running of input/output device 1106.For example, nonvolatile memory stores device 100 can be carry-on dish 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) the nonvolatile memory stores device of 1216 grades shown in Figure 1B.
Generally speaking, host computer system 1000 can be substantially for storing any system of data.Though in this exemplary embodiment; Host computer system 1000 is to explain with computer system; Yet host computer system 1000 can be systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example; In host computer system is digital camera (video camera) 1310 o'clock, and 100 in nonvolatile memory stores device is its employed SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (shown in Fig. 1 C).Embedded memory storage 1320 comprise the built-in multimedia card (Embedded MMC, eMMC).What deserves to be mentioned is that the built-in multimedia card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 is the summary calcspar that illustrates the nonvolatile memory stores device shown in Figure 1A.
Please with reference to Fig. 2, nonvolatile memory stores device 100 comprises connector 102, Memory Controller 104, non-volatile memory module 106, tank circuit 108 and power source conversion and supply circuit 110.
In this exemplary embodiment, connector 102 is USB (Universal Serial Bus, a USB) connector.Yet; It must be appreciated; The invention is not restricted to this, in another exemplary embodiment of the present invention, connector 102 also can be Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers; IEEE) 1394 connectors, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express; PCI Express) connector, serial advanced annex (Serial Advanced Technology Attachment, SATA) connector, secure digital (Secure Digital, SD) interface connector, memory stick (Memory Stick; MS) interface connector, multimedia storage card (Multi Media Card; MMC) interface connector, compact flash (Compact Flash, CF) interface connector, integrated driving electrical interface (Integrated Device Electronics, IDE) connector or other connectors that is fit to.
Non-volatile memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to host system 1000.Non-volatile memory module 106 comprises a plurality of physical blocks.Each physical blocks has a plurality of pages respectively, wherein belongs in the physical page of same physical blocks to be write independently and side by side to be wiped.More detailed, physical blocks is the least unit of wiping.That is each physical blocks contains the memory cell that is wiped free of in the lump of minimal amount.Physical page is programmable minimum unit.That is, physical page is the minimum unit that writes data.Each physical page generally includes data bit district and redundant digit district.The data bit district is in order to storage user's data, and the redundant digit district is in order to the data (for example, bug check and correcting code) of storage system.The configuration general knowledge that those skilled in the art knew for this reason in data bit district and redundant digit district is not described in detail at this.In this example was implemented, non-volatile memory module 106 was multilayer memory cell (Multi Level Cell, MLC) a NAND flash memory module.Yet, the invention is not restricted to this, non-volatile memory module 106 also the individual layer memory cell (Single Level Cell, SLC) NAND flash memory module, other flash memory module or other have the memory module of identical characteristics.
Power source conversion and supply circuit 110 are electrically connected to tank circuit 108 and in order to the power supply of control nonvolatile memory stores device 100.Specifically; Power source conversion and supply circuit 110 can be with received voltage (promptly; The output voltage that tank circuit 108 is provided) converts first voltage and second voltage into; First voltage is offered non-volatile memory module 106, and second voltage is offered Memory Controller 104.
Fig. 3 is the summary calcspar of the Memory Controller that exemplary embodiment illustrated according to the present invention.
Please with reference to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, HPI 204, memory interface 206 and memory buffer 208.
For example, in this exemplary embodiment, the steering order of memory management circuitry 202 is to come real the work with form of firmware.For example, memory management circuitry 202 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and these steering orders are to be burned onto in this ROM (read-only memory).When 100 runnings of portable non-volatile memory memory storage, these steering orders can be carried out to accomplish date storage method and the storage management method according to the embodiment of the invention by microprocessor unit.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can form of program code be stored in the specific region (for example, being exclusively used in the system region of storage system data in the memory module) of non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and RAS (not illustrating).Particularly; This ROM (read-only memory) has the driving code segment; And when Memory Controller 104 was enabled, microprocessor unit can be carried out this driving code segment earlier the steering order that is stored in the non-volatile memory module 106 is loaded in the RAS of memory management circuitry 202.Afterwards, microprocessor unit can turn round these steering orders to carry out the date storage method and the storage management method of exemplary embodiment of the present invention.In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can an example, in hardware be come real the work.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises bug check and correcting circuit 210.Bug check and correcting circuit 210 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.For example; When receiving, memory management circuitry 202 writes when instruction from host computer system 1000; Bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 210; ECC Code), and memory management circuitry 202 can corresponding these data that write instruction be write in the non-volatile memory module 106 with corresponding bug check and correcting code.Afterwards; When memory management circuitry 202 can read these data corresponding bug check and correcting code during reading of data simultaneously from non-volatile memory module 106, and bug check is understood according to this bug check and data execution error inspection and the correction program of correcting code to being read with correcting circuit 210.
Fig. 4 and Fig. 5 are the example schematic of the diode-capacitor storage module that exemplary embodiment illustrated according to the present invention.
It must be appreciated that when this described the running of physical blocks of non-volatile memory module 106, coming the operating physical block with speech such as " extraction ", " exchange ", " grouping ", " rotating " was notion in logic.That is to say that the physical location of the physical blocks of memory module 106 is not changed, but in logic the physical blocks of non-volatile memory module 106 is operated.
Please with reference to Fig. 4, memory management circuitry 202 can logically be grouped into the physical blocks 304 (0)～304 (R) of non-volatile memory module 106 data field 402, spare area 404, system region 406 and replace district 408.
The physical blocks that belongs to system region 406 in logic is in order to the register system data, and wherein this system data comprises about the manufacturer of memory chip and model, the physical blocks number of memory chip, physical page number of each physical blocks etc.
Belonging to the physical blocks that replaces in the district 408 in logic is the alternate physical block.For example, non-volatile memory module 106 can be reserved 4% physical blocks and uses as changing when dispatching from the factory.That is to say that when data field 402, spare area 404 were damaged with the physical blocks in the system region 406, the physical blocks of reserving in replacing district 408 was in order to replacing damaged physical blocks (that is bad physical blocks (bad block)).Therefore, if replace when still having normal physical blocks in the district 408 and the physical blocks damage taking place, memory management circuitry 202 can be extracted the physical blocks that normal physical blocks is changed damage from replace district 408.If when no normal physical blocks and generation physical blocks were damaged in the replacement district 408, then memory management circuitry 202 can be declared as write protection (write protect) state with whole nonvolatile memory stores device 100, and can't write data again.
Particularly, data field 402, spare area 404, system region 406 and replace the quantity of the physical blocks in district 408 can be according to different storer specifications and different.In addition, it must be appreciated that in the running of nonvolatile memory stores device 100, the grouping relation that physical blocks is associated to data field 402, spare area 404, system region 406 and replacement district 408 can dynamically change.For example, when being substituted the physical blocks replacement in district when the damage of the physical blocks in the spare area, the physical blocks that then replaces the district originally can be associated to the spare area.
Please with reference to Fig. 5, as stated, data field 402 is the data of coming host system 1000 to be write with the mode of rotating with the physical blocks of spare area 404.In this exemplary embodiment, memory management circuitry 202 can be beneficial in the physical blocks of storing data with the above-mentioned mode of rotating, carry out data access for host computer system 1000 in the configuration logic address.Particularly, memory management circuitry 202 can be grouped into blocks 510 (0)～510 (H) with the logical address that is provided, and blocks 510 (0)～510 (H) is mapped to the physical blocks of data field 402.For example, when nonvolatile memory stores device 100 was formatd with file system (for example, FAT 32) by the operating system of host computer system 1000, blocks 510 (0)～510 (H) mapped to the physical blocks 304 (0)～304 (D) of data field 402 respectively.That is to say that a blocks is understood a physical blocks in the mapping (enum) data district 402.At this, memory management circuitry 202 can be set up blocks-physical blocks mapping table (logical block-physical block mapping table), with the mapping relations between record blocks and the physical blocks.
Fig. 6～Fig. 8 is the example that writes data to non-volatile memory module that exemplary embodiment illustrated according to the present invention.
Please be simultaneously with reference to Fig. 6～Fig. 8; For example; In blocks 510 (0) is to map under the mapping status of physical blocks 304 (0); Write instruction and desire to write data when belonging to the logical address of blocks 510 (0) when Memory Controller 104 receives from host computer system 1000, memory management circuitry 202 can according to blocks-physical blocks mapping table recognition logic block 510 (0) be at present map to physical blocks 304 (0) and from spare area 404 extracts physical block 304 (D+1) as the replacement physical blocks physical blocks 304 (0) of rotating.Yet; When memory management circuitry 202 write to physical blocks 304 (D+1) with new data, memory management circuitry 202 can not moved all valid data in the physical blocks 304 (0) to physical blocks 304 (D+1) at once and wipe physical blocks 304 (0).Specifically; Memory management circuitry 202 can write physical page valid data before (promptly with desiring in the physical blocks 304 (0); The 0th physical page of physical blocks 304 (0) and the data in the 1st physical page) be copied in the 0th physical page and the 1st physical page of physical blocks 304 (D+1) (as shown in Figure 6), and new data write in the 2nd physical page and the 3rd physical page of physical blocks 304 (D+1) (as shown in Figure 7).At this moment, memory management circuitry 202 is promptly accomplished the running that writes.Therefore because it is invalid that the valid data in the physical blocks 304 (0) might become in next operation (for example, writing instruction), at once the valid data in the physical blocks 304 (0) are moved to physical blocks 304 (D+1) and may be caused meaningless moving.In addition, data must write to the physical page in the physical blocks in order, and therefore, memory management circuitry 202 only can be moved earlier and desire to write physical page valid data before.
In this exemplary embodiment; Temporarily keep these mother and sons' transient state relations (promptly; Physical blocks 304 (0) and physical blocks 304 (D+1)) running be called unlatchings (open) mother and child blocks, and the original physical block is called parent substance and manages block and replace physical blocks and be called the muon physics block.
Afterwards; In the time need the content of physical blocks 304 (0) and physical blocks 304 (D+1) really being merged; Memory management circuitry 202 just can be whole and to a physical blocks with the data of physical blocks 304 (D+1) with physical blocks 304 (0), promotes the service efficiency of physical blocks thus.At this, the running that merges mother and child blocks is called closes (close) mother and child blocks.For example; As shown in Figure 8, when closing mother and child blocks, memory management circuitry 202 can be with remaining valid data in the physical blocks 304 (0) (promptly; Data in the 4th physical page～(K) physical page of physical blocks 304 (0)) be copied in the 4th physical page～(K) physical page of replacement physical blocks 304 (D+1); Then spare area 404 is wiped and be associated to physical blocks 304 (0), simultaneously, (D+1) is associated to data field 402 with physical blocks 304.That is to say that memory management circuitry 202 can remap blocks 510 (0) to 304 (D+1) in blocks-physical blocks mapping table.In addition, in this exemplary embodiment, memory management circuitry 202 can be set up spare area physical blocks table (not illustrating) and write down the physical blocks that is associated to the spare area at present.What deserves to be mentioned is that memory management circuitry 202 needs to use the storage space of more memory buffer 252 to come the storage administration parameter when opening mother and child blocks, to write down more detailed store status.For example, these management parameters can write down in which physical page that the valid data that belong to blocks 510 (0) are stored in physical blocks 304 (0) and physical blocks 304 (D+1) dispersedly (as shown in Figure 7).Base this, during portable non-volatile memory memory storage 100 running, the group number of mother and child blocks is limited.Therefore; When portable non-volatile memory memory storage 100 receives when instruction of writing that comes from host computer system 1000; If having opened the group number of mother and child blocks reaches in limited time; Memory management circuitry 202 need be closed at least one group of mother and child blocks of having opened at present (that is, the mother and child blocks running is closed in execution) and write instruction to carry out this.At this, Fig. 6～running that writes shown in Figure 8 is called the pattern that generally writes.
Fig. 9 is the synoptic diagram of the tank circuit that exemplary embodiment illustrated according to the present invention.
Please with reference to Fig. 9, tank circuit 1110 comprises diode D, first resistance R 1, second resistance R 2, switch S and capacitance group C.The anode of diode D comes from the input voltage vin of host computer system 1000 in order to reception, and the negative electrode of diode D is in order to provide output voltage V out.First end of first end of first resistance R 1 and second resistance R 2 is electrically connected to the negative electrode of diode D.First end of switch S is electrically connected to second end of second resistance R 2, and the control end of switch S is electrically connected to Memory Controller 104.First end of capacitance group C is electrically connected to second end of switch S and is electrically connected to second end of first resistance R 1, and second end of capacitance group C is electrically connected to earth terminal.In this exemplary embodiment, capacitance group C can comprise a plurality of electric capacity of parallel connection.
In this exemplary embodiment, when nonvolatile memory stores device 100 was electrically connected to host computer system 1000, capacitance group C can store stand-by electric energy.The stand-by electric energy that capacitance group C stored is in order to keep the of short duration running of Memory Controller 104 and non-volatile memory module 106 when the input voltage deficiency that host computer system 1000 is provided.In this exemplary embodiment, for example, the capacity of capacitance group is 470～2200 microfarads (uF).What deserves to be mentioned is that in this exemplary embodiment, first resistance R 1 is a large amount of suction electric currents (inrush current) that caused for fear of capacitance group C when nonvolatile memory stores device 100 is electrically connected to host computer system 1000.For example, the resistance value of first resistance R 1 is 200 ohm.Particularly, first resistance R 1 can cause output voltage V out on the low side and Memory Controller 104 and non-volatile memory module 106 can't normally be operated.The base this; In this exemplary embodiment; For the first time receive the small computer standard interface that comes from host computer system 1000 (Small Computer Standard Interface, in the time of SCSI), Memory Controller 104 (or memory management circuitry 202 of Memory Controller 104) can be opened (turn on) switch S; So that closed next parallelly connected second resistance R 2 of switch S increases output voltage V out thus.For example, the resistance value of second resistance R 2 is 1 ohm.Base this, under the state that switch S is unlocked, Memory Controller 104 and non-volatile memory module 106 just can operate under operating voltage normally in the instruction according to host computer system 1000.
It must be appreciated, in exemplary embodiment of the present invention, when Memory Controller 104 (or memory management circuitry 202 of Memory Controller 104) can receive the SCSI instruction that comes from host computer system 1000 for the first time in the back that is enabled, open switch S.Yet; The invention is not restricted to this, in another exemplary embodiment of the present invention, Memory Controller 104 (for example; The memory management circuitry 202 of Memory Controller 104) also can receive for the first time in the back that is enabled come from host computer system 1000 write instruction the time, open switch S.Perhaps, in another exemplary embodiment of the present invention, after Memory Controller 104 (or memory management circuitry 202 of Memory Controller 104) can be enabled and wait for a time delay, open switch S.For example, be 3 seconds this time delay.
In exemplary embodiment of the present invention, Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can detect the detection signal of corresponding input voltage vin.And; When detection signal at a Preset Time (is for example indicated input voltage vin; 10 seconds) (for example continue in less than a predeterminated voltage; 4 volts (V)) time, Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can start and specially writes the data that pattern will be temporary in the memory buffer 208 and write in the non-volatile memory module 106.
Particularly; Write in the pattern special; Memory Controller 104 (for example; The memory management circuitry 202 of Memory Controller 104) can from spare area 404, extract a physical blocks, and the data that will be temporary in the memory buffer 208 writes in order in the physical page of the physical blocks of being extracted.Specifically, the data that are temporary in the memory buffer 208 can begin to be written in order from the 0th physical page of the physical blocks extracted.That is to say that Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can not write data (that is, as Fig. 6～shown in Figure 8, writing pattern) according to the corresponding relation of logic access address.The base this, the data that the time that Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can be less will be temporary in the memory buffer 208 write in the non-volatile memory module 106.
Write in the pattern special; Memory Controller 104 (for example; The memory management circuitry 202 of Memory Controller 104) can in the redundant digit district of the physical page of the physical blocks of being extracted, write down special marking, writing the physical blocks that pattern operates and distinguish with special with other physical blocks.In addition; The logical address that correspondence is temporary in the data in the memory buffer 208 (promptly; Map information) also can be recorded in the redundant digit district of physical page of the physical blocks of being extracted; Be beneficial to nonvolatile memory stores device 100 when restarting Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can be correctly with writing in data-moving (that is, writing again) to the physical blocks of being shone upon that pattern write with special.
It must be appreciated; In this exemplary embodiment; Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) is a record special marking and the corresponding map information that is temporary in the data in the memory buffer 208 in the redundant digit district of the physical page of the physical blocks of being extracted.Yet; The invention is not restricted to this; In another exemplary embodiment of the present invention; Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) also can extract another physical blocks as the specific physical block from spare area 404, which physical page that writes down which physical blocks is used to writes data and the corresponding map information that is temporary in the data in the memory buffer 208 that is temporary in the memory buffer 208 with the special pattern that writes.Afterwards; When nonvolatile memory stores device 100 is restarted; Memory Controller 104 (for example; The memory management circuitry 202 of Memory Controller 104) can from then on read relevant map information in the specific physical block, will write the data that pattern write and correctly move to the physical blocks of being shone upon with special thus.What deserves to be mentioned is that Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can preestablish some physical blocks and can be used as the specific physical block.For example, in an exemplary embodiment, physical blocks 304 (D+1)～physical blocks 304 (D+10) can be used as the specific physical block.The base this; When nonvolatile memory stores device 100 is restarted; Memory Controller 104 (for example; The memory management circuitry 202 of Memory Controller 104) only need confirm data in physical blocks 304 (D+1)～physical blocks 304 (D+10), just can be informed in the data that were temporary in when last time shutting down in the memory buffer 208 and whether be with special write that pattern is written into to non-volatile memory module 106, judge whether to need to carry out the running of moving data thus.
In addition; In another exemplary embodiment of the present invention; Write in the pattern special; Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) also can only use the physical page that belongs to lower page among the physical page of the physical blocks of being extracted to write the data that are temporary in the memory buffer 208.
Specifically, NAND type flash memory can be divided into SLC NAND type flash memory and MLC NAND type flash memory according to storable figure place in each memory cell.Only can carry out the able to programme of single-order when the memory cell to SLC NAND type flash memory writes (also being called (program) able to programme), so each memory cell only can be stored one data.And the physical blocks of MLC NAND type flash memory able to programme is divided into the multistage.For example, be example with 4 layers of memory cell, physical blocks able to programme was divided into for 2 stages.Phase one is the part that writes of lower page (lower page), and its physical characteristics is similar to individual layer memory cell (Single Level Cell, SLC) NAND flash memory.Subordinate phase is the page (upper page) of going up able to programme, and wherein the writing speed of lower page can be faster than the last page.Therefore, the page of each physical blocks can be divided into the page (that is the last page) and the quick page (that is lower page) at a slow speed.Similarly, in the case of 8 layers of memory cell or 16 layers of memory cell, memory cell can comprise more a plurality of pages and can be so that more the multistage writes.At this, the page that writing speed is the fastest is called lower page, and the slower page of other writing speeds is referred to as the page.For example, the last page comprises a plurality of pages with different writing speeds.In addition, in other embodiments, the last page also can be the slowest page of writing speed, perhaps writing speed the slowest with the part writing speed faster than the writing speed page of the page the most slowly.For example, in 4 layers of memory cell, lower page is the fastest and writing speed time fast page of writing speed, and the last page then is the slowest and writing speed time slow page of writing speed.In this exemplary embodiment, the physical page of physical blocks can be divided into according to its write diagnostics and belong to the page or lower page.
Base this, write the data that are temporary in the memory buffer 208 through the physical page that belongs to lower page among the physical page that only uses the physical blocks extracted, can more shorten the required time of data that is temporary in the memory buffer 208 that writes.
In addition, in exemplary embodiment of the present invention, nonvolatile memory stores device 100 disposes access pilot lamp (not illustrating), is carrying out the access running to show nonvolatile memory stores device 100.For example, this access pilot lamp is the LED lamp.
Particularly, in another exemplary embodiment of the present invention, write in the pattern special, Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) more can be closed the access pilot lamp to reduce power consumption.
What deserves to be mentioned is; In this exemplary embodiment; When detection signal indication input voltage vin continued less than predeterminated voltage in Preset Time, Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can start the special pattern that writes.Yet; The invention is not restricted to this, for example, in another exemplary embodiment of the present invention; Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) also can start the special pattern that writes according to the detection signal of the unactivated state of indicating connector 102.Specifically; At connector 102 is in the example of USB 3.0; When hypervelocity (superspeed) connection failure between nonvolatile memory stores device 100 and the host computer system 1000; Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can detect non-activation (SS.Inactive) state of connector 102, judges that thus nonvolatile memory stores device 100 possibly pulled out from host computer system 1000 undesiredly.In addition; In another exemplary embodiment of the present invention; Memory Controller 104 (for example; The memory management circuitry 202 of Memory Controller 104) also can start the special pattern that writes according to the park mode that comes from host computer system 1000 (suspend mode) signal, warm replacement (warm reset) signal or warm reset (hot reset) signal; Wherein warm reset signal is that the moving signal of putting of heat then is the signal that makes system rearrange data and system is started in system's starting point (starting point) in order to the signal of drive system again under the state that does not descend at voltage.
Figure 10 is the process flow diagram of the date storage method that exemplary embodiment illustrated according to the present invention.
Please with reference to Figure 10, during 100 runnings of nonvolatile memory stores device, the input voltage that in step S1001, comes from host computer system 1000 can be judged whether in Preset Time, continue less than predeterminated voltage.Specifically; At step S1001; Whether Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can continue to detect the input voltage that comes from host computer system 1000, in Preset Time, continue less than predeterminated voltage to judge this input voltage.
Whether when if the input voltage that comes from host computer system continues less than predeterminated voltage in Preset Time, in step S1003, can judge to keep in the memory buffer 208 has the data that do not write to as yet in the nonvolatile memory 106.
If keep in when the data that do not write to as yet in the nonvolatile memory 106 are arranged in the memory buffer 208, the data that in step S1005, are temporary in the memory buffer 208 can be written in the nonvolatile memory 106 with the special pattern that writes.If it is temporary when the data that do not write to as yet in the nonvolatile memory 106 are arranged that the input voltage that comes from host computer system continues in Preset Time less than not having in predeterminated voltage or the memory buffer 208, then step S1001 can be performed to continue to detect the input voltage that comes from host computer system.In this exemplary embodiment, flow process shown in Figure 10 can be in the running that continues after 100 activations of nonvolatile memory stores device till nonvolatile memory stores device 100 be ended running.
Figure 11 is the process flow diagram of the date storage method that another exemplary embodiment illustrated according to the present invention.
Please, during 100 runnings of nonvolatile memory stores device, in step S1101, can judge whether to detect the unactivated state of connector 102 with reference to Figure 11.Specifically, at step S1101, Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can judge whether to detect the unactivated state of connector 102.
If whether when detecting the unactivated state of connector 102, in step S1103, can judge to keep in the memory buffer 208 has the data that do not write to as yet in the nonvolatile memory 106.
If keep in when the data that do not write to as yet in the nonvolatile memory 106 are arranged in the memory buffer 208, the data that in step S1105, are temporary in the memory buffer 208 can write in the nonvolatile memory 106 with the special pattern that writes.
If not detecting does not have temporaryly when the data that do not write to as yet in the nonvolatile memory 106 are arranged in unactivated state or the memory buffer 208 of connector 102, then step S1101 can be performed to continue to detect the input voltage that comes from host computer system.Same, in this exemplary embodiment, flow process shown in Figure 11 can be in the running that continues after 100 activations of nonvolatile memory stores device till nonvolatile memory stores device 100 be ended running.
Figure 12 is the process flow diagram of the date storage method that another exemplary embodiment illustrated according to the present invention.
Please, during 100 runnings of nonvolatile memory stores device, in step S1201, can judge whether to receive the park mode signal that comes from host computer system 1000, warm reset signal or warm reset signal with reference to Figure 12.Specifically, at step S1201, Memory Controller 104 (for example, the memory management circuitry 202 of Memory Controller 104) can judge whether to receive the park mode signal that comes from host computer system 1000, warm reset signal or warm reset signal.
If whether when receiving the park mode signal that comes from host computer system 1000, warm reset signal or warm reset signal, in step S1203, can judge to keep in the memory buffer 208 has the data that do not write to as yet in the nonvolatile memory 106.
If keep in when the data that do not write to as yet in the nonvolatile memory 106 are arranged in the memory buffer 208, the data that in step S1205, are temporary in the memory buffer 208 can write in the nonvolatile memory 106 with the special pattern that writes.
Do not keep in when the data that do not write to as yet in the nonvolatile memory 106 are arranged if receive not have in the park mode signal that comes from host computer system 1000, warm reset signal or warm reset signal or the memory buffer 208, then step S1201 can be performed to continue to judge whether to receive the park mode signal that comes from host computer system 1000, warm reset signal or warm reset signal.Same, in this exemplary embodiment, flow process shown in Figure 11 can be in the running that continues after 100 activations of nonvolatile memory stores device till nonvolatile memory stores device 100 be ended running.
In sum, the loss of the data in nonvolatile memory stores device, Memory Controller and the date storage method of the exemplary embodiment of the present invention memory buffer that can avoid causing because of abnormal outage.
Though the present invention with embodiment openly as above; Right its is not in order to limit the present invention; Those skilled in the art are not breaking away from the spirit and scope of the present invention, when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appended claims person of defining.
Claims (18)
1. nonvolatile memory stores device comprises:
A connector is in order to be electrically connected to a host computer system;
One tank circuit is in order to receive an input voltage and an output voltage is provided;
One power source conversion and supply circuit electrically connect this tank circuit and in order to this output voltage is converted to one first voltage and one second voltage;
One non-volatile memory module electrically connects this power source conversion and supply circuit and operates in this first voltage;
One Memory Controller electrically connects this connector, this tank circuit and this power source conversion and supply circuit and operates in this second voltage; And
One memory buffer electrically connects this Memory Controller, in order to temporary data,
Wherein this Memory Controller writes to this non-volatile memory module in order to these data that when receiving a signal, will be temporarily stored in this memory buffer, and wherein this signal is in order to indicate this input voltage in a Preset Time, to continue less than a detection signal of a predeterminated voltage or in order to a detection signal or a park mode signal, a warm reset signal or a warm reset signal for from this host computer system, being received of the unactivated state of indicating this connector.
2. nonvolatile memory stores device as claimed in claim 1, wherein this tank circuit comprises:
One diode has an anode and a negative electrode, and this anode is in order to receive this input voltage, and this negative electrode is in order to provide this output voltage;
One first end that one first resistance and one second resistance, one first end of this first resistance are electrically connected to this negative electrode and this second resistance of this diode is electrically connected to this negative electrode of this diode;
One switch, one first end of this switch is electrically connected to one second end of this second resistance and a control end of this switch is electrically connected to this Memory Controller; And
One capacitance group, one first end of this capacitance group are electrically connected to one second end of this first resistance and one second end of this switch and one second end of this capacitance group and are electrically connected to an earth terminal,
Wherein this Memory Controller also in order to when receive the small computer standard interface SCSI instruction that comes from this host computer system the back first time that is enabled, is opened this switch.
3. nonvolatile memory stores device as claimed in claim 1, wherein this tank circuit comprises:
One diode has an anode and a negative electrode, and this anode is in order to receive this input voltage, and this negative electrode is in order to provide this output voltage;
One first end that one first resistance and one second resistance, one first end of this first resistance are electrically connected to this negative electrode and this second resistance of this diode is electrically connected to this negative electrode of this diode;
One switch, one first end of this switch is electrically connected to one second end of this second resistance and a control end of this switch is electrically connected to this Memory Controller; And
One capacitance group, one first end of this capacitance group are electrically connected to one second end of this first resistance and one second end of this switch and one second end of this capacitance group and are electrically connected to an earth terminal,
Wherein this Memory Controller also in order to receive for the first time in the back that is enabled when coming from one of this host computer system and writing instruction, is opened this switch.
4. nonvolatile memory stores device as claimed in claim 1, wherein this tank circuit comprises:
One diode has an anode and a negative electrode, and this anode is in order to receive this input voltage, and this negative electrode is in order to provide this output voltage;
One first end that one first resistance and one second resistance, one first end of this first resistance are electrically connected to this negative electrode and this second resistance of this diode is electrically connected to this negative electrode of this diode;
One switch, one first end of this switch is electrically connected to one second end of this second resistance and a control end of this switch is electrically connected to this Memory Controller; And
One capacitance group, one first end of this capacitance group are electrically connected to one second end of this first resistance and one second end of this switch and one second end of this capacitance group and are electrically connected to an earth terminal,
Wherein this Memory Controller is opened this switch also in order to after being enabled and waiting for a time delay.
5. nonvolatile memory stores device as claimed in claim 1, wherein this non-volatile memory module comprises that a plurality of physical blocks and these physical blocks are grouped into a data field and a spare area at least,
Wherein this Memory Controller extracts a physical blocks and this data that will be temporary in this memory buffer write in this physical blocks from this spare area when receiving this signal.
6. nonvolatile memory stores device as claimed in claim 5, wherein this Memory Controller only uses the physical page that belongs to a lower page among a plurality of physical pages of this physical blocks of from this spare area, being extracted to write these data that are temporary in this memory buffer when receiving this signal.
7. nonvolatile memory stores device as claimed in claim 5, wherein this Memory Controller also in order to when receiving this signal in a redundant digit district of this physical blocks record to a map information that should data.
8. nonvolatile memory stores device as claimed in claim 5, wherein this Memory Controller also in order to when receiving this signal, from this spare area, extract another physical blocks and in this another physical blocks of being extracted record to a map information that should data.
9. nonvolatile memory stores device as claimed in claim 5 also comprises an access pilot lamp,
Wherein this Memory Controller is also in order to close this access pilot lamp when receiving this signal.
10. Memory Controller comprises:
One HPI is in order to be electrically connected to a host computer system;
One memory interface is in order to be electrically connected to a non-volatile memory module;
One memory management circuitry electrically connects this HPI and this memory interface; And
One memory buffer electrically connects this memory management circuitry and in order to temporary data that come from this host computer system,
Wherein this memory management circuitry writes to this non-volatile memory module in order to these data that when receiving a signal, will be temporarily stored in this memory buffer; Wherein this signal is in order to indicate this input voltage in a Preset Time, to continue less than a detection signal of a predeterminated voltage or in order to a detection signal or a park mode signal, a warm reset signal or a warm reset signal for from this host computer system, being received of the unactivated state of indicating this connector
Wherein this memory management circuitry also is included in the switch in the tank circuit in order to unlatching.
11. a date storage method is used for a non-volatile memory module, this date storage method comprises:
Judge whether an input voltage that comes from this host computer system continues less than a predeterminated voltage in a Preset Time; And
When this input voltage that comes from this host computer system continues less than this predeterminated voltage, data that are temporarily stored in the memory buffer are write to this non-volatile memory module in this Preset Time.
12. date storage method as claimed in claim 11, wherein this non-volatile memory module has a plurality of physical blocks and these physical blocks are grouped into a data field and a spare area at least,
Wherein will be temporarily stored in the step that these data in this memory buffer write to this non-volatile memory module comprises:
From this spare area, extract a physical blocks; And
These data that are temporary in this memory buffer are write in this physical blocks.
13. date storage method as claimed in claim 12; Wherein each these physical blocks comprises that speed that a plurality of physical pages and these physical pages belong to the page on a lower page and respectively and write data to the physical page that belongs to this lower page is faster than writing data to the speed that belongs to the physical page of the page on this
Wherein will be temporary in the step that these data in this memory buffer write in this physical blocks comprises: only use the physical page that belongs to this lower page among these physical pages of this physical blocks of from this spare area, being extracted to write these data that are temporary in this memory buffer.
14. date storage method as claimed in claim 12 wherein will be temporarily stored in the step that these data in this memory buffer write to this non-volatile memory module and also comprise:
Record is to a map information that should data in a redundant digit district of this physical blocks.
15. date storage method as claimed in claim 12 wherein will be temporarily stored in the step that these data in this memory buffer write to this non-volatile memory module and also comprise:
From this spare area, extract another physical blocks and in this another physical blocks of being extracted record to a map information that should data.
16. date storage method as claimed in claim 12 wherein will be temporarily stored in the step that these data in this memory buffer write to this non-volatile memory module and also comprise:
Close an access pilot lamp.
17. a date storage method is used for a non-volatile memory module, this date storage method comprises:
Judge whether to detect a unactivated state of a connector; And
When detecting this unactivated state of this connector, data that are temporarily stored in the memory buffer are write to this non-volatile memory module.
18. a date storage method is used for a non-volatile memory module, this date storage method comprises:
Judge whether from this host computer system, to receive a park mode signal, a warm reset signal or a warm reset signal; And
When from this host computer system, receiving this park mode signal, this warm reset signal or this warm reset signal, data that are temporarily stored in the memory buffer are write to this non-volatile memory module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105279215A CN102456404A (en) | 2010-10-21 | 2010-10-21 | NVM (nonvolatile memory) storage device, memory controller and data storage method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105279215A CN102456404A (en) | 2010-10-21 | 2010-10-21 | NVM (nonvolatile memory) storage device, memory controller and data storage method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102456404A true CN102456404A (en) | 2012-05-16 |
Family
ID=46039495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105279215A Pending CN102456404A (en) | 2010-10-21 | 2010-10-21 | NVM (nonvolatile memory) storage device, memory controller and data storage method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102456404A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102831920A (en) * | 2012-07-22 | 2012-12-19 | 北京忆恒创源科技有限公司 | Power supply circuit and power supply method |
| CN104252219A (en) * | 2012-07-22 | 2014-12-31 | 北京忆恒创源科技有限公司 | Power supply circuit and power supply method |
| CN104570821A (en) * | 2013-10-09 | 2015-04-29 | 新唐科技股份有限公司 | Integrated circuit and operation method thereof |
| CN104809082A (en) * | 2014-01-29 | 2015-07-29 | 群联电子股份有限公司 | Data protection method, storage storing device and storage control unit circuit |
| CN104900267A (en) * | 2015-06-16 | 2015-09-09 | 无锡中星微电子有限公司 | Read control circuit for retention memory |
| CN105810245A (en) * | 2014-12-31 | 2016-07-27 | 群联电子股份有限公司 | Data sampling circuit module, data sampling method and memory storage device |
| CN107403644A (en) * | 2017-05-22 | 2017-11-28 | 宜鼎国际股份有限公司 | Possesses the flash memory device of abnormal power protection |
| CN110069211A (en) * | 2018-01-23 | 2019-07-30 | 纬创资通股份有限公司 | Data management circuit |
| CN110781029A (en) * | 2018-07-30 | 2020-02-11 | 慧荣科技股份有限公司 | Power-off protection method and system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101187830A (en) * | 2007-12-27 | 2008-05-28 | 华为技术有限公司 | Power off protection method, device and logic device and storage system |
| CN101552032A (en) * | 2008-12-12 | 2009-10-07 | 深圳市晶凯电子技术有限公司 | Method and device for constructing a high-speed solid state memory disc by using higher-capacity DRAM to join in flash memory medium management |
| CN101710252A (en) * | 2009-12-08 | 2010-05-19 | 成都市华为赛门铁克科技有限公司 | Power supply method and power supply device of storage system |
| CN101866320A (en) * | 2009-04-14 | 2010-10-20 | 群联电子股份有限公司 | Data management method and flash memory storage system and controller using the same |
-
2010
- 2010-10-21 CN CN2010105279215A patent/CN102456404A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101187830A (en) * | 2007-12-27 | 2008-05-28 | 华为技术有限公司 | Power off protection method, device and logic device and storage system |
| CN101552032A (en) * | 2008-12-12 | 2009-10-07 | 深圳市晶凯电子技术有限公司 | Method and device for constructing a high-speed solid state memory disc by using higher-capacity DRAM to join in flash memory medium management |
| CN101866320A (en) * | 2009-04-14 | 2010-10-20 | 群联电子股份有限公司 | Data management method and flash memory storage system and controller using the same |
| CN101710252A (en) * | 2009-12-08 | 2010-05-19 | 成都市华为赛门铁克科技有限公司 | Power supply method and power supply device of storage system |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102831920A (en) * | 2012-07-22 | 2012-12-19 | 北京忆恒创源科技有限公司 | Power supply circuit and power supply method |
| CN102831920B (en) * | 2012-07-22 | 2014-11-12 | 北京忆恒创源科技有限公司 | Power supply circuit and power supply method |
| CN104252219A (en) * | 2012-07-22 | 2014-12-31 | 北京忆恒创源科技有限公司 | Power supply circuit and power supply method |
| CN104570821A (en) * | 2013-10-09 | 2015-04-29 | 新唐科技股份有限公司 | Integrated circuit and operation method thereof |
| CN104809082A (en) * | 2014-01-29 | 2015-07-29 | 群联电子股份有限公司 | Data protection method, storage storing device and storage control unit circuit |
| CN104809082B (en) * | 2014-01-29 | 2018-02-02 | 群联电子股份有限公司 | Data guard method, memory storage apparatus and memorizer control circuit unit |
| CN105810245A (en) * | 2014-12-31 | 2016-07-27 | 群联电子股份有限公司 | Data sampling circuit module, data sampling method and memory storage device |
| CN105810245B (en) * | 2014-12-31 | 2019-08-27 | 群联电子股份有限公司 | Data-sampling circuit module, method of data samples and memorizer memory devices |
| CN104900267A (en) * | 2015-06-16 | 2015-09-09 | 无锡中星微电子有限公司 | Read control circuit for retention memory |
| CN104900267B (en) * | 2015-06-16 | 2019-01-11 | 无锡中感微电子股份有限公司 | The read control circuit of terminate-and-stay-resident |
| CN107403644A (en) * | 2017-05-22 | 2017-11-28 | 宜鼎国际股份有限公司 | Possesses the flash memory device of abnormal power protection |
| CN107403644B (en) * | 2017-05-22 | 2020-01-10 | 宜鼎国际股份有限公司 | Flash memory device with abnormal power protection |
| CN110069211A (en) * | 2018-01-23 | 2019-07-30 | 纬创资通股份有限公司 | Data management circuit |
| CN110069211B (en) * | 2018-01-23 | 2022-07-29 | 纬创资通股份有限公司 | Data management circuit |
| CN110781029A (en) * | 2018-07-30 | 2020-02-11 | 慧荣科技股份有限公司 | Power-off protection method and system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI451435B (en) | Non-volatile memory storage apparatus, memory controller and data storage method | |
| CN102456404A (en) | NVM (nonvolatile memory) storage device, memory controller and data storage method | |
| CN102073600B (en) | Data backup method, flash memory controller and flash memory storage system | |
| CN103544115B (en) | Method for writing data, Memory Controller and memory storage apparatus | |
| CN104699413A (en) | Data management method, memorizer saving device and memorizer control circuit unit | |
| CN101567220A (en) | Bad block identifying method, storage system and controller thereof for flash memory | |
| CN102193869A (en) | Memory management and write-in method, memory controller and storage system | |
| CN103678162B (en) | System data storage method, memory controller and memory storage device | |
| CN102446137B (en) | Method for writing data, Memory Controller and memorizer memory devices | |
| CN103136111A (en) | Data writing method, memorizer controller and memorizer storage device | |
| CN102567221B (en) | Data management method, memory controller and memory storage device | |
| CN102122233B (en) | Method for managing block and writing data, flash memory storage system and controller | |
| CN102402396B (en) | Combined type storage device as well as combined type storage media controller and addressing method thereof | |
| TWI536392B (en) | Non-volatile memory storage apparatus, memory controller and data storage method | |
| CN102053920B (en) | Data writing method, flash memory controller and flash memory system | |
| TWI521538B (en) | Non-volatile memory storage apparatus, memory controller and data storage method | |
| CN104238956A (en) | Method for writing data, controller of storage, and storage device of storage | |
| CN102737716A (en) | Memory storage device, memory controller and data writing method | |
| CN102467459B (en) | Data write method, memory controller and memory device | |
| CN102110056B (en) | Flash memory management method, flash memory controller and flash memory storage system | |
| CN102543184A (en) | Memory storage device, memory controller thereof and data writing method | |
| CN103019952B (en) | Method for writing data, Memory Controller and memorizer memory devices | |
| CN102591738B (en) | Data managing method, Memory Controller and in-line memory storage device | |
| CN102779551B (en) | Data writing method, storage controller and memory storage device | |
| CN102456401B (en) | Block management method, memory controller and memory storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120516 |
|
| RJ01 | Rejection of invention patent application after publication |