TWI536392B - Non-volatile memory storage apparatus, memory controller and data storage method - Google Patents

Description

Non-volatile memory storage device, memory controller and data storage method

The present invention relates to a non-volatile memory storage device, a memory controller and a data storage method, and more particularly to a method for writing data in a buffer memory when a non-volatile memory storage device is powered off. Non-volatile memory storage device, memory controller and data storage method to non-volatile memory modules.

Digital cameras, mobile phones and MP3s have grown very rapidly in recent years, and the demand for storage media has increased rapidly. Because non-volatile memory has the characteristics of non-volatile data, power saving, small size and no mechanical structure, it is suitable for portable applications and is most suitable for use in such portable battery-powered products. A flash drive is a storage device that uses NAND flash memory as a storage medium. For example, through the Universal Serial Bus (USB), the user can easily plug and drop the USB flash drive to the host to transfer digital data.

Because the data is written to the flash memory much faster than the host USB transmission speed, therefore, in general, the buffer memory will be configured in the non-volatile memory storage device to temporarily store data from the host. In particular, when the host issues a write command and a data to be written to the non-volatile memory storage device, the memory control circuit (also referred to as a memory controller) will temporarily store the data in the buffer memory. A message indicating that the write command has been completed is replied to the host, so that the host can continue to perform the next operation, thereby improving operational efficiency.

However, since the flash drive is operated by the USB through the USB Source, therefore, if the user removes the flash drive from the host while there is still data in the buffer memory, the data temporarily stored in the buffer memory will be lost. Therefore, how to write the data temporarily stored in the buffer memory to the flash memory when the non-volatile memory storage device is powered off is a problem that a person skilled in the art is working on.

The invention provides a memory storage system, a memory controller and a data A storage method capable of writing data temporarily stored in the buffer memory to the non-volatile memory module when the power is turned off.

An exemplary embodiment of the present invention provides a non-volatile memory storage device. It includes a connector, a tank circuit, a power conversion and supply circuit, a non-volatile memory module, a memory controller, and a buffer memory. The connector is for coupling to the host system. The tank circuit is configured to receive an input voltage and provide an output voltage. The power conversion and supply circuit is coupled to the energy storage circuit and is configured to convert the output voltage into the first voltage and the Two voltages. The non-volatile memory module is coupled to the power conversion and supply circuit and operates at the first voltage. The memory controller is coupled to the connector, the tank circuit and the power conversion and supply circuit and operates at the second voltage. Buffer memory is used to temporarily store data. The memory controller is configured to write the data temporarily stored in the buffer memory to the non-volatile memory module when the signal is received, wherein the signal is used to indicate that the input voltage continues to be less than a preset time for a preset period of time. The voltage detection signal is a detection signal for indicating the non-actuated state of the connector or a pause mode signal, a warm reset signal or a hot reset signal received from the host system.

In an embodiment of the invention, the energy storage circuit includes a diode, The first resistor, the second resistor, the switch and the capacitor group. The diode has an anode and a cathode, the anode is for receiving the input voltage, and the cathode is for providing the output voltage. The first end of the first resistor is coupled to the cathode of the diode and the first end of the second resistor is coupled to the cathode of the diode. The first end of the switch is coupled to the second end of the second resistor and the control end of the switch is coupled to the memory controller. The first end of the capacitor group is coupled to the second end of the first resistor and the second end of the switch, and the second end of the capacitor group is coupled to the ground.

In an embodiment of the invention, the memory controller is further used in When it is first received, it receives the Small Computer Standard Interface (SCSI) command from the host system and turns on the above switch.

In an embodiment of the invention, the memory controller is further used in When the write command from the host system is received for the first time after being enabled, the above switch is turned on.

In an embodiment of the invention, the memory controller is further used in After being enabled and waiting for a delay time, the above switch is turned on.

In an embodiment of the invention, the non-volatile memory module package described above Enclosing a plurality of physical blocks and the plurality of physical blocks are at least grouped into a data area and a spare area, wherein the memory controller extracts a physical block from the spare area when the signal is received and temporarily stores the The data in the buffer memory is written to this physical block.

In an embodiment of the invention, the memory controller is received The signal only uses the physical page belonging to the next page among the physical pages of the physical block extracted from the spare area to write the data temporarily stored in the buffer memory.

In an embodiment of the invention, the memory controller is further used in When receiving the signal, the mapping information corresponding to the written data is recorded in the redundant bit area of the physical block.

In an embodiment of the invention, the memory controller is further used in When the signal is received, another physical block is extracted from the spare area and mapping information corresponding to the written data is recorded in the extracted another physical block.

In an embodiment of the invention, the non-volatile memory storage device described above The device further includes an access indicator, wherein the memory controller is further configured to turn off the access indicator when receiving the signal.

An exemplary embodiment of the present invention provides a memory controller including a host Interface, memory interface, memory management circuit and buffer memory. The host interface is coupled to the host system. The memory interface is coupled to the non-volatile memory model group. The memory management circuit is coupled to the host interface and the memory interface. The buffer memory is coupled to the memory management circuit and is used to temporarily store data from the host system. The memory management circuit is configured to write the data temporarily stored in the buffer memory to the non-volatile memory module when the signal is received. In addition, the memory management circuit is further configured to turn on a switch included in the energy storage circuit.

In an embodiment of the invention, the memory management circuit is further used to When the write command from the host system is received for the first time after being enabled, the above switch is turned on.

In an embodiment of the invention, the memory management circuit is further used to After being enabled and waiting for a delay time, the above switch is turned on.

In an embodiment of the invention, the non-volatile memory module package described above a plurality of physical blocks are included and the physical blocks are at least grouped into a data area and a spare area, wherein the memory management circuit extracts a physical block from the spare area when the signal is received and temporarily stores The data in the buffer memory is written to this physical block.

In an embodiment of the invention, the memory management circuit is receiving At the time of the signal, only the physical pages belonging to the next page among the physical pages of the physical block extracted from the spare area are used to write the data temporarily stored in the buffer memory.

In an embodiment of the invention, the memory management circuit is further used to When the signal is received, the mapping information corresponding to the written data is recorded in the redundant bit area of the physical block.

In an embodiment of the invention, the memory management circuit is further used to Another physical block is extracted from the spare area when the signal is received and the mapping information corresponding to the written data is recorded in the extracted another physical block.

In an embodiment of the invention, the memory management circuit described above further includes An access indicator, wherein the memory controller is further configured to turn off the access indicator when receiving a signal.

An exemplary embodiment of the present invention provides a data storage method for a non-swing In the memory module. The data storage method includes determining whether an input voltage from the host system continues to be less than a preset voltage within a preset time; and when the input voltage from the host system continues to be less than a preset voltage for a preset time, the buffer is temporarily buffered. The data in the memory is written to the non-volatile memory module.

In an embodiment of the present invention, the foregoing is temporarily stored in the buffer memory. The step of writing the data to the non-volatile memory module includes: extracting the physical block from the spare area; and writing the data temporarily stored in the buffer memory to the physical block.

In an embodiment of the present invention, the foregoing physical blocks respectively include multiple The next page and multiple upper pages and write data to these lower pages are faster than writing data to these upper pages.

In an embodiment of the invention, each physical block includes a plurality of real The body page and the physical pages belong to the lower page and the upper page, respectively, and the data is written to the physical page belonging to the next page faster than the physical data written to the upper page. Moreover, the step of writing the data temporarily stored in the buffer memory into the physical block includes: using only the entity page of the next page belonging to the physical page of the physical block extracted from the spare area. Write temporarily stored in the buffer Recall the information in the body.

In an embodiment of the present invention, the foregoing is temporarily stored in the buffer memory. The step of writing the data to the non-volatile memory module further includes: recording mapping information corresponding to the written data in the redundant bit area of the physical block.

In an embodiment of the present invention, the foregoing is temporarily stored in the buffer memory. The step of writing the data to the non-volatile memory module further comprises: extracting another physical block from the spare area and recording mapping information corresponding to the written data in the extracted another physical block.

In an embodiment of the present invention, the foregoing is temporarily stored in the buffer memory. The step of writing data to the non-volatile memory module further includes: turning off the access indicator.

An exemplary embodiment of the present invention provides a data storage method for a non-swing In the memory module. The data storage method includes: determining whether the non-actuated state of the connector is detected; and writing the data temporarily stored in the buffer memory to the non-volatile memory module when the non-actuated state of the connector is detected; .

An exemplary embodiment of the present invention provides a data storage method for a non-swing In the memory module. The data storage method includes: determining whether a pause mode signal, a warm reset signal or a hot reset signal is received from the host system; and when receiving a pause mode signal, a warm reset signal or a warm reset signal from the host system Write data temporarily stored in the buffer memory to the non-volatile memory module.

Based on the above, the memory storage system, the memory controller, and the data storage method of the exemplary embodiments of the present invention can be used when the non-volatile memory storage device is powered off. Write data temporarily stored in the buffer memory to the flash memory.

The above described features and advantages of the invention will be apparent from the following description.

1000‧‧‧Host system

1100‧‧‧ computer

1102‧‧‧Microprocessor

1104‧‧‧ Random access memory

1106‧‧‧Input/output devices

1108‧‧‧System Bus

1110‧‧‧Data transmission interface

1202‧‧‧ Mouse

1204‧‧‧ keyboard

1206‧‧‧ display

1208‧‧‧Printer

1212‧‧‧USB flash drive

1214‧‧‧ memory card

1216‧‧‧ Solid State Drive

1310‧‧‧ digital camera

1312‧‧‧SD card

1314‧‧‧MMC card

1316‧‧‧ Memory Stick

1318‧‧‧CF card

1320‧‧‧Embedded storage device

100‧‧‧Non-volatile memory storage device

102‧‧‧Connector

104‧‧‧ memory controller

106‧‧‧Non-volatile memory module

108‧‧‧ Energy storage circuit

110‧‧‧Power conversion and supply circuit

202‧‧‧Memory Management Circuit

204‧‧‧Host interface

206‧‧‧ memory interface

208‧‧‧buffer memory

210‧‧‧Error checking and correction circuit

304(0)~304(R)‧‧‧ physical block

402‧‧‧Information area

404‧‧‧ spare area

406‧‧‧System Area

408‧‧‧Replaced area

510(0)~510(H)‧‧‧ logical block

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

D‧‧‧ diode

R1‧‧‧first resistance

R2‧‧‧second resistance

S‧‧ switch

C‧‧‧capacitor group

GND‧‧‧ ground terminal

FIG. 1A illustrates a host system and a non-volatile memory storage device according to an exemplary embodiment of the invention.

FIG. 1B is a schematic diagram of a computer, an input/output device, and a non-volatile memory storage device according to an exemplary embodiment of the invention.

FIG. 1C is a schematic diagram of a host system and a non-volatile memory storage device according to another exemplary embodiment of the invention.

FIG. 2 is a schematic block diagram showing the non-volatile memory storage device shown in FIG. 1A.

FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention.

4 and FIG. 5 are schematic diagrams showing an example of a management memory module according to an exemplary embodiment of the invention.

6-8 are examples of writing data to a non-volatile memory module according to an exemplary embodiment of the invention.

FIG. 9 is a schematic diagram of an energy storage circuit according to an exemplary embodiment of the invention.

FIG. 10 is a flow of a data storage method according to an exemplary embodiment of the present invention. Cheng Tu.

FIG. 11 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.

FIG. 12 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.

In general, non-volatile memory storage devices (also known as non-volatile memory) The memory storage system includes a non-volatile memory module and a memory controller (also referred to as a memory control circuit). Typically, non-volatile memory storage devices are used with host systems to enable the host system to write data to or read data from non-volatile memory storage devices.

FIG. 1A is a schematic diagram of a host system according to an exemplary embodiment of the invention. Volatile memory storage device.

Referring to FIG. 1A, the host system 1000 generally includes a computer 1100 and an input. /output (output/output, I/O) device 1106. The computer 1100 includes a microprocessor 1102, a random access memory (RAM) 1104, a system bus 1108, and a data transmission interface 1110. The input/output device 1106 includes a mouse 1202, a keyboard 1204, a display 1206, and a printer 1208 as in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the input/output device 1106, and the input/output device 1106 may further include other devices.

In the embodiment of the present invention, the non-volatile memory storage device 100 is transparent. The data transmission interface 1110 is coupled to other components of the host system 1000. The data can be written to or read from the non-volatile memory storage device 100 by the operation of the microprocessor 1102, the random access memory 1104, and the input/output device 1106. For example, the non-volatile memory storage device 100 may be a non-volatile memory storage device such as a flash drive 1212, a memory card 1214, or a solid state drive (SSD) 1216 as shown in FIG. 1B.

In general, the host system 1000 can be substantially any data storeable system. Although in the present exemplary embodiment, the host system 1000 is illustrated by a computer system, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, a video camera, a communication device, an audio player, or a video player. And other systems. For example, when the host system is a digital camera (camera) 1310, the non-volatile memory storage device 100 is used for its SD card 1312, MMC card 1314, memory stick 1316, CF card 1318 or embedded. Storage device 1320 (shown in Figure 1C). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC). It is worth mentioning that the embedded multimedia card is directly coupled to the substrate of the host system.

2 is a schematic view of the non-volatile memory storage device shown in FIG. 1A; Block diagram.

Referring to FIG. 2, the non-volatile memory storage device 100 includes a connector. 102. A memory controller 104, a non-volatile memory module 106, a tank circuit 108, and a power conversion and supply circuit 110.

The connector 102 is coupled to the memory controller 104 and coupled to the main Machine system 1000. That is, the non-volatile memory storage device 100 is connected to the corresponding port on the host system 1000 through the connector 102.

In the present exemplary embodiment, the connector 102 is a universal serial bus. (Universal Serial Bus, USB) connector. However, it must be understood that The present invention is not limited thereto. In another exemplary embodiment of the present invention, the connector 102 may also be an Institute of Electrical and Electronic Engineers (IEEE) 1394 connector, a high-speed peripheral component connection interface (Peripheral Component Interconnect). Express, PCI Express) connector, Serial Advanced Technology Attachment (SATA) connector, Secure Digital (SD) interface connector, Memory Stick (MS) interface connector, multimedia memory card ( Multi Media Card, MMC) interface connector, Compact Flash (CF) interface connector, Integrated Device Electronics (IDE) connector or other suitable connector.

The memory controller 104 is configured to perform in a hard type or a firmware type A plurality of logic gates or control commands are executed, and data is written, read, erased, etc. in the non-volatile memory module 106 according to an instruction of the host system 1000. In particular, the memory controller 104 performs the data storage method and the memory management method of the present exemplary embodiment to write, read, erase, and manage the data in the non-volatile memory module 106. Operation. The data storage method and the memory management method according to an exemplary embodiment of the present invention will be described in detail below with reference to the drawings.

The non-volatile memory module 106 is coupled to the memory controller 104, and And used to store the data written by the host system 1000. The non-volatile memory module 106 includes a plurality of physical blocks. Each physical block has a plurality of pages, respectively, wherein physical pages belonging to the same physical block can be independently written and erased simultaneously. In more detail, the physical block is the smallest unit of erasure. That is, each physical block contains one of the smallest number of erased memory cells. The entity page is the smallest unit that is stylized. That is, the physical page is the smallest unit for writing data. Each physical page typically includes a data bit area and a redundant bit area. The data bit area is used to store the user's data, and the redundant bit area is used to store system data (eg, error checking and correction codes). The configuration of the data bit area and the redundant bit area is a general knowledge known to those skilled in the art and will not be described in detail herein. In this example implementation, the non-volatile memory module 106 is a multi-level cell (MLC) NAND flash memory module. However, the present invention is not limited thereto, and the non-volatile memory module 106 may also be a single level cell (SLC) NAND flash memory module, other flash memory modules, or other components having the same characteristics. Memory module.

The tank circuit 108 is coupled to the memory controller 104. In this exemplary embodiment The power required to operate the non-volatile memory storage device 100 is provided by the host system 1000 through the connector 102. Here, the tank circuit 108 is configured to receive an input voltage from the host system 1000 through the connector 102 and provide an output voltage for supply to the memory controller 104 of the non-volatile memory storage device 100 and the non-volatile memory model. Group 106. In particular, in the present exemplary embodiment, the energy storage circuit 108 is further configured to store a backup power, and when the host system 1000 interrupts the power supply, the energy storage circuit 108 provides the backup power as an output voltage for supply to the memory control. The device 104 and the non-volatile memory module 106 serve as a short-term operation.

The power conversion and supply circuit 110 is coupled to the energy storage circuit 108 and used to The power of the non-volatile memory storage device 100 is controlled. Specifically, the power conversion and supply circuit 110 converts the received voltage (ie, the output voltage provided by the tank circuit 108) into a first voltage and a second voltage, and supplies the first voltage to the non-volatile memory. The body module 106 and provides a second voltage to the memory controller 104.

FIG. 3 is a diagram of a memory controller according to an exemplary embodiment of the invention. Summary block diagram.

Referring to FIG. 3, the memory controller 104 includes a memory management circuit. 202. The host interface 204, the memory interface 206, and the buffer memory 208.

The memory management circuit 202 is used to control the entirety of the memory controller 104. Operation to perform data writing, reading, erasing, etc. For example, the memory management circuit 202 has a plurality of control commands, and when the portable non-volatile memory storage device 100 operates, such control commands are executed to perform data storage method and memory management according to the present exemplary embodiment. method.

For example, in the present exemplary embodiment, the control of the memory management circuit 202 The instructions are implemented in a firmware version. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and such control instructions are programmed into the read-only memory. When the portable non-volatile memory storage device 100 operates, such control commands are executed by the microprocessor unit to complete the data storage method and the memory management method according to the embodiments of the present invention.

In another exemplary embodiment of the present invention, the memory management circuit 202 controls The programming instructions may also be stored in a particular area of the non-volatile memory module 106 (eg, a system area dedicated to storing system data in the memory module). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a drive code segment, and when the memory controller 104 is enabled, the microprocessor unit first executes the drive code segment to be stored in the non-volatile memory module 106. The control command is loaded into the random access memory of the memory management circuit 202. Thereafter, the microprocessor unit operates the control commands to perform the data storage method and the memory management method of the exemplary embodiments of the present invention. In addition, in another exemplary embodiment of the present invention, the control command of the memory management circuit 202 can also be implemented in a hardware format.

The host interface 204 is coupled to the memory management circuit 202 and used to connect The instructions and data transmitted by the host system 1000 are received and recognized. That is to say, the instructions and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204. In the exemplary embodiment, the host interface 204 is a USB interface of the corresponding connector 102. However, it should be understood that the present invention is not limited thereto, and the host interface 204 may also be a PATA interface, an IEEE 1394 interface, a PCI Express interface, an SD interface, an MS interface, an MMC interface, a CF interface, a SATA interface, an IDE interface, or other suitable. Data transmission interface.

The memory interface 206 is coupled to the memory management circuit 202 and is used to access the non-volatile memory module 106. That is, the data to be written to the non-volatile memory module 106 is converted to a format acceptable to the non-volatile memory module 106 via the memory interface 206.

The buffer memory 208 is coupled to the memory management circuit 202 and used to The data and instructions from the host system 1000 or the data from the non-volatile memory module 106 are temporarily stored. Here, the buffer memory 208 is a static random access memory (SRAM). However, it should be understood that the present invention is not limited thereto. In another exemplary embodiment, the buffer memory 208 may also be a Dynamic Random Access Memory (DRAM) or other suitable memory. Moreover, in another embodiment of the present example, the buffer memory 208 can also be configured independently of the memory controller 104. That is, the buffer memory 208 can be disposed outside the memory controller 104 and coupled to the memory controller 104 through the bus bar.

In an exemplary embodiment of the present invention, the memory controller 104 further includes an error. The error checking and correction circuit 210. The error checking and correction circuit 210 is coupled to the memory management circuit 202 and is used to perform error checking and correction procedures to ensure the correctness of the data. For example, when the memory management circuit 202 receives a write command from the host system 1000, the error check and correction circuit 210 generates a corresponding error check and correction code (Error Checking and Correcting Code) for the data corresponding to the write command. ECC Code), and the memory management circuit 202 writes the data corresponding to the write command and the corresponding error check and correction code to the non-volatile memory module 106. Then, when the memory management circuit 202 reads the data from the non-volatile memory module 106, the error check and correction code corresponding to the data is simultaneously read, and the error check and correction circuit 210 checks and corrects according to the error. The code performs an error check and correction procedure on the data read.

4 and FIG. 5 are management memories according to an exemplary embodiment of the present invention. An example schematic of a body module.

It must be understood that the non-volatile memory module 106 is described herein. When the block is operated, it is a logical concept to operate the physical block with words such as "extract", "exchange", "group", and "rotation". That is to say, the actual location of the physical block of the memory module 106 is not changed, but the physical block of the non-volatile memory module 106 is logically operated.

Referring to FIG. 4, the memory management circuit 202 will perform a non-volatile memory model. The physical blocks 304(0)-304(R) of group 106 are logically grouped into a data area 402, a spare area 404, a system area 406, and a replacement area 408.

The physical blocks of the data area 402 and the spare area 404 are used to store The data of the host system 1000. Specifically, the data area 402 is a physical block in which data is stored, and the physical block of the spare area 404 is a physical block used to replace the data area 402. Therefore, the physical block of the spare area 404 is empty or usable physical block, that is, no recorded data or invalid data marked as useless. That is to say, the physical block in the spare area has been erased, or the physical block extracted before the physical block in the spare area is extracted for storing data is subjected to the erase operation. Therefore, the physical block of the spare area is a physical block that can be used.

The physical block logically belonging to system area 406 is used to record system resources. The system data includes the manufacturer and model of the memory chip, the number of physical blocks of the memory chip, the number of physical pages of each physical block, and the like.

The physical block logically belonging to the replacement area 408 is a substitute physical block. For example, the non-volatile memory module 106 will reserve 4% of the physical block for replacement when it leaves the factory. That is, when the physical block 402, the spare area 404, and the physical block in the system area 406 are damaged, the physical block reserved in the replacement area 408 is used to replace the damaged physical block (ie, the bad physical area). Block (bad block). Therefore, if the normal physical block still exists in the replacement area 408 and the physical block is damaged, the memory management circuit 202 extracts the normal physical block from the replacement area 408 to replace the damaged physical block. If there is no normal physical block in the replacement area 408 and the physical block is damaged, the memory management circuit 202 declares the entire non-volatile memory storage device 100 as a write protect state, and cannot Write data.

In particular, the data area 402, the spare area 404, the system area 406, and the replacement area The number of physical blocks in 408 will vary depending on the memory specifications. In addition, it must be understood that in the operation of the non-volatile memory storage device 100, the grouping relationship of the physical block association to the data area 402, the spare area 404, the system area 406, and the replacement area 408 may dynamically change. For example, when a physical block in a spare area is damaged and replaced by a physical block of the replaced area, the physical block of the originally replaced area is associated with the spare area.

Referring to FIG. 5, as described above, the entity of the data area 402 and the spare area 404 The block stores the data written by the host system 1000 in a rotating manner. In the present exemplary embodiment, the memory management circuit 202 configures the logical address to the host system 1000 to facilitate data access in the physical block in which the data is stored in the above-described alternate manner. In particular, the memory management circuit 202 groups the provided logical addresses into logical blocks 510(0)-510(H) and maps logical blocks 510(0)~510(H) to the resources. The physical block of the material area 402. For example, when the non-volatile memory storage device 100 is formatted by the operating system of the host system 1000 in a file system (eg, FAT 32), logical blocks 510(0)-510(H) are mapped to the data area 402, respectively. Physical blocks 304(0)~304(D). That is, one logical block maps one physical block in the data area 402. Here, the memory management circuit 202 establishes a logical block-physical block mapping table to record the mapping relationship between the logical block and the physical block.

FIG. 6 to FIG. 8 are diagrams for writing data to an exemplary embodiment of the present invention. An example of a non-volatile memory module.

Please refer to FIG. 6 to FIG. 8 at the same time, for example, in the logical block 510 (0) is a mapping In the mapping state to the physical block 304(0), when the memory controller 104 receives a write command from the host system 1000 and wants to write data to a logical address belonging to the logical block 510(0), the memory The volume management circuit 202 identifies that the logical block 510(0) is currently mapped to the physical block 304(0) and the physical block 304(D+1) is extracted from the spare area 404 according to the logical block-physical block mapping table. The physical block 304(0) is rotated as a replacement physical block. However, when the memory management circuit 202 writes new data to the physical block 304 (D+1), the memory management circuit 202 does not immediately move all valid data in the physical block 304(0) to the entity. Block 304 (D+1) erases physical block 304(0). Specifically, the memory management circuit 202 will store the valid data before the entity page in the physical block 304(0) (ie, the 0th entity page of the physical block 304(0) and the 1st entity page. Data) is copied to the 0th entity page of the physical block 304 (D+1) and the 1st entity page (as shown in FIG. 6), and the new data is written to the real The second entity page of the body block 304 (D+1) is in the third entity page (as shown in FIG. 7). At this time, the memory management circuit 202 completes the operation of writing. Since the valid data in the physical block 304(0) may become invalid in the next operation (for example, a write command), the valid data in the physical block 304(0) is immediately moved to the physical block 304 (D). +1) may cause unnecessary moves. In addition, the data must be sequentially written to the physical page within the physical block. Therefore, the memory management circuit 202 only moves the valid data before the physical page is written.

In the present exemplary embodiment, temporarily maintaining the operation of the parent-child transient relationship (ie, the physical block 304(0) and the physical block 304(D+1)) is referred to as opening the parent and child blocks, and The original physical block is called the parent physical block and the replacement physical block is called the child physical block.

Thereafter, when it is necessary to actually merge the contents of the physical block 304(0) with the physical block 304(D+1), the memory management circuit 202 will place the physical block 304(0) with the physical block 304(D). The +1) data is merged into one physical block, thereby improving the efficiency of the use of the physical block. Here, the operation of merging the parent and child blocks is called closing the mother and child blocks. For example, as shown in FIG. 8, when the parent and child blocks are closed, the memory management circuit 202 will store the remaining valid material in the physical block 304(0) (ie, the fourth entity page of the physical block 304(0). ~ The material in the (K) entity page) is copied to the 4th entity page to the (K) entity page of the replacement entity block 304 (D+1), and then the physical block 304(0) is erased and Associated to spare area 404, while physical block 304 (D+1) is associated to data area 402. That is, the memory management circuit 202 will remap the logical block 510(0) to 304(D+1) in the logical block-physical block mapping table. In addition, In the present exemplary embodiment, the memory management circuit 202 creates a spare area physical block table (not shown) to record the physical blocks currently associated with the spare area. It is worth mentioning that the memory management circuit 202 needs to use more storage space of the buffer memory 252 to store management variables when the mother and child blocks are turned on to record a more detailed storage state. For example, such management variables record which physical pages of the physical block 304(0) and the physical block 304(D+1) are randomly stored in the physical block of the logical block 510(0) (FIG. 7). Shown). Accordingly, during operation of the portable non-volatile memory storage device 100, the number of groups of mother and child blocks is limited. Therefore, when the portable non-volatile memory storage device 100 receives the write command from the host system 1000, the memory management circuit 202 needs to close at least one group if the number of groups of the mother and child blocks has been reached to the upper limit. The parent and child blocks that are currently open (ie, performing the shutdown parent and child block operations) execute this write command. Here, the write operation shown in FIGS. 6 to 8 is referred to as a general write mode.

FIG. 9 is a schematic diagram of an energy storage circuit according to an exemplary embodiment of the invention. Figure.

Referring to FIG. 9, the energy storage circuit 1110 includes a diode D and a first resistor R1. The second resistor R2, the switch S and the capacitor group C. The anode of the diode D is for receiving the input voltage Vin from the host system 1000, and the cathode of the diode D is for providing the output voltage Vout. The first end of the first resistor R1 and the first end of the second resistor R2 are coupled to the cathode of the diode D. The first end of the switch S is coupled to the second end of the second resistor R2, and the control end of the switch S is coupled to the memory controller 104. The first end of the capacitor group C is coupled to the second end of the switch S and coupled to the second end of the first resistor R1. And the second end of the capacitor group C is coupled to the ground. In the present exemplary embodiment, the capacitor bank C may include a plurality of capacitors in parallel.

In the present exemplary embodiment, when the non-volatile memory storage device 100 is coupled When connected to the host system 1000, the capacitor bank C stores backup power. The backup power stored in the capacitor group C is used to maintain the short-term operation of the memory controller 104 and the non-volatile memory module 106 when the input voltage provided by the host system 1000 is insufficient. In the present exemplary embodiment, for example, the capacity of the capacitor group is 470 to 2200 microfarads (uF). It should be noted that, in the present exemplary embodiment, the first resistor R1 is to avoid a large amount of inrush current caused by the capacitor group C when the non-volatile memory storage device 100 is coupled to the host system 1000. For example, the resistance of the first resistor R1 is 200 ohms. In particular, the first resistor R1 causes the output voltage Vout to be low, so that the memory controller 104 and the non-volatile memory module 106 cannot operate normally. Therefore, in the present exemplary embodiment, the memory controller 104 (or the memory of the memory controller 104) is received when receiving the Small Computer Standard Interface (SCSI) from the host system 1000 for the first time. The body management circuit 202) turns on the switch S to close the switch S to connect the second resistor R2 in parallel, thereby increasing the output voltage Vout. For example, the resistance value of the second resistor R2 is 1 ohm. Accordingly, in a state where the switch S is turned on, the memory controller 104 and the non-volatile memory module 106 can operate according to an instruction of the host system 1000 at a normal operating voltage.

It should be understood that in an exemplary embodiment of the present invention, the memory controller 104 (or the memory management circuit 202 of the memory controller 104) may be enabled after being enabled. When the SCSI command from the host system 1000 is received for the first time, the switch S is turned on. However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also be received for the first time after being enabled. When a write command from the host system 1000 is issued, the switch S is turned on. Alternatively, in another exemplary embodiment of the present invention, the memory controller 104 (or the memory management circuit 202 of the memory controller 104) is enabled and waits for a delay time to turn on the switch S. For example, this delay time is 3 seconds.

In an exemplary embodiment of the invention, memory controller 104 (eg, memory The memory management circuit 202) of the body controller 104 detects the detection signal corresponding to the input voltage Vin. And, when the detection signal indicates that the input voltage Vin continues to be less than a predetermined voltage (for example, 4 volts (V)) for a preset time (for example, 10 seconds), the memory controller 104 (for example, a memory) The memory management circuit 202) of the controller 104 activates the special write mode to write the data temporarily stored in the buffer memory 208 to the non-volatile memory module 106.

In particular, in the special write mode, the memory controller 104 (for example, The memory management circuit 202) of the memory controller 104 extracts a physical block from the spare area 404, and sequentially stores the data temporarily stored in the buffer memory 208 in the physical page of the extracted physical block. Write. Specifically, the data temporarily stored in the buffer memory 208 is sequentially written from the 0th physical page of the extracted physical block. That is, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) does not write data according to the correspondence of the logical access addresses (ie, as shown in FIGS. 6-8). General write mode). Based on this, remember The memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) can write data temporarily stored in the buffer memory 208 to the non-volatile memory module 106 in less time.

In the special write mode, the memory controller 104 (eg, memory control) The memory management circuit 202) of the controller 104 records a special flag in the redundant bit area of the physical page of the extracted physical block to operate the physical block and other physical blocks in a special write mode. To distinguish. In addition, the logical address (ie, mapping information) corresponding to the data temporarily stored in the buffer memory 208 is also recorded in the redundant bit area of the physical page of the extracted physical block to facilitate non-volatile When the memory storage device 100 is restarted, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) can correctly move the data written in the special write mode (ie, rewrite) ) to the mapped physical block.

It must be understood that in the present exemplary embodiment, the memory controller 104 (For example, the memory management circuit 202 of the memory controller 104) is a mapping of the special mark and the corresponding data temporarily stored in the buffer memory 208 in the redundant bit area of the physical page of the extracted physical block. News. However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also extract another physical area from the spare area 404. The block acts as a special physical block to record which physical pages of the physical blocks are used to write the data temporarily stored in the buffer memory 208 and the data temporarily stored in the buffer memory 208 in a special write mode. Mapping information. Thereafter, when the non-volatile memory storage device 100 is restarted, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) will be special from this The relevant mapping information is read in the body block, thereby correctly transferring the data written in the special write mode to the mapped physical block. It is worth mentioning that the memory controller 104 (e.g., the memory management circuit 202 of the memory controller 104) pre-sets that certain physical blocks can be used as special physical blocks. For example, in an exemplary embodiment, physical block 304 (D+1) ~ physical block 304 (D+10) will be used as a special physical block. Accordingly, when the non-volatile memory storage device 100 is restarted, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) only needs to confirm the physical block 304 (D+1)~ The data in the physical block 304 (D+10) can know whether the data temporarily stored in the buffer memory 208 during the previous shutdown is written to the non-volatile memory module in the special write mode. In 106, it is judged whether or not the operation of moving the data needs to be performed.

Moreover, in another exemplary embodiment of the present invention, in the special write mode, The memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) can write the temporary storage to the buffer memory by using only the physical pages belonging to the lower page among the physical pages of the extracted physical block. Information in 208.

Specifically, the NAND type flash memory can be based on each memory cell. The number of bits stored is divided into SLC NAND type flash memory and MLC NAND type flash memory. In the writing (also called program) of the memory cells of the SLC NAND type flash memory, only a single-order stylization can be performed, so that each memory cell can store only one bit of data. The stylization of the physical block of the MLC NAND type flash memory can be divided into multiple stages. For example, taking a 4-layer memory cell as an example, an entity The stylization of the block can be divided into two phases. The first stage is the write portion of the lower page, which has physical characteristics similar to Single Level Cell (SLC) NAND flash memory. The second stage is the upper page, where the lower page will be written faster than the previous page. Therefore, the pages of each physical block can be divided into a slow page (ie, an upper page) and a fast page (ie, a lower page). Similarly, in the case of 8-layer memory cells or 16-layer memory cells, the memory cells will include more pages and will be written in more stages. Here, the page with the fastest write speed is called the next page, and the other pages with slower write speed are collectively referred to as the upper page. For example, the upper page includes multiple pages with different write speeds. In addition, in other embodiments, the upper page may also be the page with the slowest write speed, or the page with the slowest write speed and partial write speed faster than the slowest write page. For example, in a 4-layer memory cell, the lower page is the page with the fastest write speed and the faster write speed, and the upper page is the page with the slowest write speed and the slower write speed. In this exemplary embodiment, the physical page of the physical block may be classified as belonging to the upper page or the lower page according to its writing characteristics.

Based on this, by using only the entity pages of the extracted physical block By writing the data temporarily stored in the buffer memory 208 on the physical page of the next page, the time required to write the data temporarily stored in the buffer memory 208 can be further shortened.

In addition, in an exemplary embodiment of the present invention, a non-volatile memory storage device The setting 100 is provided with an access indicator (not shown) to indicate that the non-volatile memory storage device 100 is performing an access operation. For example, this access indicator is an LED light.

In particular, in another exemplary embodiment of the present invention, in the special write mode, the memory controller 104 (eg, the memory management of the memory controller 104) Path 202) will also turn off the access indicator to reduce power consumption.

It is worth mentioning that in the present exemplary embodiment, when the detection signal indicates the loss When the incoming voltage Vin continues to be less than the preset voltage for a preset time, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104) initiates the special write mode. However, the present invention is not limited thereto. For example, in another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also be inactive according to the indication connector 102. The status detection signal activates the special write mode. Specifically, in the example where the connector 102 is USB 3.0, when the superspeed connection between the non-volatile memory storage device 100 and the host system 1000 fails, the memory controller 104 (eg, memory control) The memory management circuit 202) of the device 104 detects the inactive (SS.Inactive) state of the connector 102, thereby determining that the non-volatile memory storage device 100 may be improperly removed from the host system 1000. In addition, in another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also be based on a suspend mode signal from the host system 1000. A special reset mode is initiated by a warm reset signal or a hot reset signal, wherein the warm reset signal is a signal for re-driving the system in a state where the voltage does not drop, and the thermal activation signal is A signal that causes the system to rearrange the data and initiate the system at the starting point of the system.

FIG. 10 is a diagram of a data storage method according to an exemplary embodiment of the present invention. flow chart.

Please refer to FIG. 10, during the operation period of the non-volatile memory storage device 100. Meanwhile, the input voltage from the host system 1000 in step S1001 is judged whether it continues to be less than the preset voltage for a preset time. Specifically, in step S1001, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) continuously detects the input voltage from the host system 1000 to determine whether the input voltage is preset. The duration continues to be less than the preset voltage.

If the input voltage from the host system continues to be less than the preset time When the voltage is preset, it is determined in step S1003 whether or not the data that has not been written into the non-volatile memory 106 is temporarily stored in the buffer memory 208.

If the buffer memory 208 is temporarily stored in the non-volatile memory In the case of the data in the volume 106, the data temporarily stored in the buffer memory 208 in step S1005 is written into the non-volatile memory 106 in a special write mode. If the input voltage from the host system does not continue to be less than the preset voltage within the preset time or the buffer memory 208 has no temporary storage data that has not been written into the non-volatile memory 106, then step S1001 is performed. To continue to detect the input voltage from the host system. In the present exemplary embodiment, the flow shown in FIG. 10 continues to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 ceases to operate.

FIG. 11 is a data storage device according to another exemplary embodiment of the present invention. Flow chart of the law.

Referring to FIG. 11, during the operation of the non-volatile memory storage device 100, it is determined in step S1101 whether the non-actuated state of the connector 102 is detected. Specifically, in step S1101, the memory controller 104 (for example, a memory controller) The memory management circuit 202 of 104 determines whether the non-actuated state of the connector 102 is detected.

If the non-actuated state of the connector 102 is detected, in step S1103 It is judged whether or not the data that has not been written into the non-volatile memory 106 is temporarily stored in the buffer memory 208.

If the buffer memory 208 is temporarily stored in the non-volatile memory In the case of the data in the volume 106, the data temporarily stored in the buffer memory 208 in step S1105 is written into the non-volatile memory 106 in a special write mode.

If the non-actuated state of the connector 102 or the buffer memory is not detected When there is no temporary storage of data in the non-volatile memory 106 in 208, step S1101 is executed to continue detecting the input voltage from the host system. Similarly, in this exemplary embodiment, the flow shown in FIG. 11 will continue to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 ceases to operate.

FIG. 12 is a data storage side according to another exemplary embodiment of the present invention. Flow chart of the law.

Please refer to FIG. 12, during the operation period of the non-volatile memory storage device 100. In the step S1201, it is determined whether a pause mode signal, a warm reset signal or a hot reset signal from the host system 1000 is received. Specifically, in step S1201, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) determines whether a pause mode signal, a warm reset signal, or a hot weight from the host system 1000 is received. Signal number.

If a pause mode signal from the host system 1000 is received, warm weight is received. When the signal or the hot reset signal is set, it is determined in step S1203 whether or not the data that has not been written into the non-volatile memory 106 is temporarily stored in the buffer memory 208.

If the buffer memory 208 is temporarily stored in the non-volatile memory In the case of the data in the body 106, the data temporarily stored in the buffer memory 208 in step S1205 is written into the non-volatile memory 106 in a special write mode.

If the pause mode signal from the host system 1000 is not received, warm When the reset signal or the hot reset signal or the buffer memory 208 does not temporarily store the data that has not been written into the non-volatile memory 106, the step S1201 is executed to continue to determine whether the host system 1000 is received. Pause mode signal, warm reset signal or hot reset signal. Similarly, in this exemplary embodiment, the flow shown in FIG. 11 will continue to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 ceases to operate.

In summary, the non-volatile memory storage device of the exemplary embodiment of the present invention The memory, memory controller and data storage method can avoid the loss of data in the buffer memory caused by abnormal power failure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Non-volatile memory storage device

102‧‧‧Connector

104‧‧‧ memory controller

106‧‧‧Non-volatile memory module

108‧‧‧Power conversion and supply circuit

110‧‧‧storage circuit

Claims (15)

A data storage method for a non-volatile memory module, wherein the non-volatile memory module has a plurality of physical blocks and the physical blocks are at least grouped into a data area and a spare area, The data storage method includes: determining whether a pause mode signal, a warm reset signal or a hot reset signal is received from a host system; and receiving the pause mode signal, the warm reset signal from the host system Or when the hot reset signal is received, a physical block is extracted from the spare area and a data temporarily stored in a buffer memory is written into the physical block. The data storage method of claim 1, wherein each of the physical blocks includes a plurality of physical pages and the physical pages respectively belong to a lower page and an upper page and the data is written to belong to the next page. The physical page is faster than the speed at which the data is written to the physical page belonging to the upper page, wherein the step of writing the data temporarily stored in the buffer memory into the physical block includes: using only from the The physical page belonging to the lower page among the physical pages of the physical block extracted in the spare area is used to write the data temporarily stored in the buffer memory. The data storage method of claim 1, wherein the step of writing the data temporarily stored in the buffer memory to the physical block further comprises: a redundant bit area of the physical block Record a mapping information corresponding to the data. For example, the data storage method described in claim 1 of the patent application, wherein the data storage method will be temporarily stored The step of writing the data in the buffer memory to the physical block further comprises: extracting another physical block from the spare area and recording one corresponding data in the extracted another physical block Map information. A non-volatile memory storage device includes: a connector for coupling to a host system; a storage circuit for receiving an input voltage and providing an output voltage; and a power conversion and supply circuit coupled The energy storage circuit is configured to convert the output voltage into a first voltage and a second voltage; a non-volatile memory module coupled to the power conversion and supply circuit and operating at the first voltage, wherein the non-volatile The memory module includes a plurality of physical blocks and the physical blocks are at least grouped into a data area and a spare area; a memory controller coupled to the connector, the energy storage circuit and the power conversion And a supply circuit and operating the second voltage; and a buffer memory coupled to the memory controller for temporarily storing a data, wherein the memory controller is configured to receive a pause mode from the host system a signal, a warm reset signal or a hot reset signal, extracting a physical block from the spare area and writing the data temporarily stored in the buffer memory to the extracted real Block. The non-volatile memory storage device of claim 5, wherein the energy storage circuit comprises: a diode having an anode and a cathode, the anode for receiving the input voltage, the cathode being used for Providing the output voltage; a first resistor and a second resistor, a first end of the first resistor is coupled to the cathode of the diode and a first end of the second resistor is coupled to the cathode of the diode; a switch, a first end of the switch is coupled to a second end of the second resistor, and a control end of the switch is coupled to the memory controller; and a capacitor group, the first of the capacitor group The second end of the first resistor is coupled to a second end of the switch and the second end of the capacitor is coupled to a ground end, wherein the memory controller is further configured to be enabled The first time after receiving a Small Computer Standard Interface (SCSI) command from the host system, the switch is turned on. The non-volatile memory storage device of claim 5, wherein the energy storage circuit comprises: a diode having an anode and a cathode, the anode for receiving the input voltage, the cathode being used for Providing the output voltage; a first resistor and a second resistor; a first end of the first resistor is coupled to the cathode of the diode and a first end of the second resistor is coupled to the diode a cathode of the switch; a switch having a first end coupled to a second end of the second resistor and a control end of the switch coupled to the memory controller; and a capacitor bank, the capacitor a first end of the group is coupled to a second end of the first resistor and a second end of the switch, and a second end of the capacitor group is coupled to a ground The memory controller is further configured to turn on the switch when receiving a write command from the host system for the first time after being enabled. The non-volatile memory storage device of claim 5, wherein the energy storage circuit comprises: a diode having an anode and a cathode, the anode for receiving the input voltage, the cathode being used for Providing the output voltage; a first resistor and a second resistor; a first end of the first resistor is coupled to the cathode of the diode and a first end of the second resistor is coupled to the diode a cathode of the switch; a switch having a first end coupled to a second end of the second resistor and a control end of the switch coupled to the memory controller; and a capacitor bank, the capacitor A first end of the group is coupled to a second end of the first resistor and a second end of the switch, and a second end of the capacitor group is coupled to a ground end, wherein the memory controller is further used The switch is turned on after being enabled and waiting for a delay time. The non-volatile memory storage device of claim 5, wherein the memory controller receives only the pause mode signal, the warm reset signal or the hot reset signal from the host system. The material temporarily stored in the buffer memory is written using a physical page belonging to the next page among the plurality of physical pages of the physical block extracted from the spare area. The non-volatile memory storage device of claim 5, wherein the memory controller is further configured to receive the pause mode signal, the warm reset signal or the hot reset from the host system. The signal records a mapping information corresponding to the data in a redundant bit area of the extracted physical block. The non-volatile memory storage device of claim 5, wherein the memory controller is further configured to receive the pause mode signal, the warm reset signal or the hot reset from the host system. At the time of the signal, another physical block is extracted from the spare area and a mapping information corresponding to the data is recorded in the extracted another physical block. A memory controller includes: a host interface coupled to a host system; a memory interface coupled to a non-volatile memory module, wherein the non-volatile memory module includes a physical block and the physical blocks are at least grouped into a data area and a spare area; a memory management circuit coupled to the host interface and the memory interface; and a buffer memory coupled to the memory The management circuit is configured to temporarily store a data from the host system, wherein the memory management circuit is configured to receive a pause mode signal, a warm reset signal or a warm reset signal from the host system Extracting a physical block from the spare area and writing the data temporarily stored in the buffer memory to the extracted physical block, wherein the memory management circuit is further configured to be included in a storage circuit one of switch. The memory controller of claim 12, wherein the memory management circuit uses only the pause mode signal, the warm reset signal or the warm reset signal when receiving the slave system The physical page belonging to the next page among the plurality of physical pages of the physical block extracted in the spare area is used to write the data temporarily stored in the buffer memory. The memory controller of claim 12, wherein the memory management circuit is further configured to receive the pause mode signal, the warm reset signal or the hot reset signal from the host system. A mapping information corresponding to the data is recorded in a redundant bit area of the extracted physical block. The memory controller of claim 12, wherein the memory management circuit is further configured to receive the pause mode signal, the warm reset signal or the hot reset signal from the host system. Another physical block is extracted in the spare area and a mapping information corresponding to the data is recorded in the extracted another physical block.