CN102567221B - Data management method, memory controller and memory storage device - Google Patents
Data management method, memory controller and memory storage device Download PDFInfo
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Abstract
The invention provides a data management method, a memory controller and a memory storage device. The method comprises the following steps of: at least grouping the entity units of a rewritable nonvolatile memory module into a data area and an idle area; configuring multiple logic units to map the entity units of the data area; receiving at least two updated data, wherein the at least two updated data corresponds to different logic pages of the logic units; and extracting an entity unit from the idle area and writing the at least two updated data into the same entity page of the extracted entity unit. With the adoption of the data management method, the memory controller and the memory storage device, the using efficiency of the storage space of the entity unit can be improved.
Description
Technical field
The present invention relates to a kind of data managing method, and particularly relate to a kind of for writing data to the data managing method of the physical blocks of type nonvolatile and the Memory Controller and the memorizer memory devices that use the method.
Background technology
Digital camera, mobile phone and MP3 are very rapid in growth over the years, and the demand of consumer to Storage Media is also increased rapidly.Due to type nonvolatile (rewritablenon-volatile memory) there is data non-volatile, power saving, the characteristic such as volume is little, mechanical structure, read or write speed are fast, be most suitable for portable electronic product, such as notebook computer.Solid state hard disc is exactly a kind of storage device using flash memory as Storage Media.Therefore, flash memory industry becomes a ring quite popular in electronic industry in recent years.
The storer submodule group of flash memory module has multiple solid element, each solid element is made up of one or more physical blocks (physical block), and each physical blocks has multiple physical page (physical page), when wherein writing data in physical blocks, data must be write in order according to the order of physical page.In addition, the physical page needing being written into data could again for writing data after first being erased.Particularly, physical blocks is the least unit of erasing, and physical page is the minimum unit of stylize (also known as write).Therefore, in the management of flash memory module, solid element can be divided into data field and idle district.
The solid element of data field is the data stored stored by host computer system.Specifically, the logic access address that host computer system can access by the memory management circuitry in memorizer memory devices is converted to the logical page (LPAGE) of logical block and the logical page (LPAGE) of logical block is mapped to the physical page of the solid element of data field.That is, in the management of flash memory module, the solid element of data field is regarded as by the solid element (such as, having stored the data that host computer system writes) used.Such as, memory management circuitry can use logical block-solid element mapping table to record the mapping relations of the solid element of logical block and data field, and the logical page (LPAGE) wherein in logical block is the physical page of the corresponding solid element mapped in order.
The solid element in idle district is the solid element of rotating in data field.Specifically, as mentioned above, the physical blocks of written data just can again for writing data after must being erased, therefore, the solid element in idle district be designed to write more new data to replace the solid element of mapping logic unit.Base this, the solid element in idle district is empty or spendable solid element, i.e. no record data or be labeled as invalid data useless.
That is, the solid element in data field and idle district is that the mode of rotating carrys out mapping logic unit, to store the data that host computer system writes.Such as, the memory management circuitry of memorizer memory devices can extract one or more solid element as the solid element of rotating from idle district, and when host computer system is a certain logical page (LPAGE) of corresponding a certain logical block for writing the logic access address of more new data, the memory management circuitry of memorizer memory devices can by this more new data write in the physical page of the solid element of rotating.
In addition, memory management circuitry can record the more new data that this physical page stores a certain logical page (LPAGE) in the redundant area of write physical page, and the physical page originally mapping this logical page (LPAGE) within a data area can be marked as invalid.Particularly, if when the number of solid element available in idle district is less than a predetermined threshold level, when performing write instruction, memory management circuitry must carry out data merging (Merge) program, to avoid the solid element in idle district depleted (exhaust).Specifically, in data consolidation procedure, memory management circuitry can extract an empty solid element from idle district, be copied in extracted solid element by the valid data belonging to same logical block in the solid element of the solid element of rotating and data field, the solid element of rotating in solid element and data field that stored data are all invalid data thus just can be erased and is associated to idle district.
Because of the progress on flash memory process, the design capacity of the physical page of each physical blocks is had and becomes large trend.For existing flash memory, the capacity of its each physical page mostly is 8 kilobit tuple (Kilobyte; KB).But, host computer system is sent to the write data of storage device normally in units of 4KB, therefore when the data that host computer system writes a 4KB are to the physical page of a certain 8KB of solid element, the physical page being written into 4KB data just has other 4KB space and is not used to, and causes the waste of the storage area of solid element.
Summary of the invention
The invention provides a kind of data managing method, Memory Controller and memorizer memory devices, it can write the more new data that two correspond to the Different Logic page in the same physical page of solid element, to improve the service efficiency of the storage area of the chaotic solid element of universe.
The embodiment of the present invention proposes a kind of data managing method, for managing the data writing to a type nonvolatile module, wherein this type nonvolatile module has multiple solid element, and each solid element has multiple physical page.Notebook data management method comprises the multiple logical block of configuration with the solid element of demapping section.Notebook data management method also comprises sets up logical block-solid element mapping table with the mapping relations between the solid element recording logical block and above-mentioned part.Notebook data management method also comprises reception at least two more new data, wherein these at least two the Different Logic pages more among the corresponding above-mentioned logical page (LPAGE) of new data.Data managing method also comprises an extraction solid element from above-mentioned solid element.Notebook data management method also comprise by above-mentioned at least two more new data write to the same physical page of extracted solid element.
In one embodiment of this invention, the physical page being written into above-mentioned at least two more new datas comprises first record area, second record area, the 3rd recording areas and the 4th recording areas.First record area and second record area are in order to record above-mentioned at least two the first stroke more new datas more in new data, and the 3rd recording areas and the 4th recording areas are in order to record above-mentioned at least two more in new data second more new data.
In one embodiment of this invention, the logic access address of above-mentioned the first stroke more corresponding to new data is recorded in first record area, the Part I of second logic access address more corresponding to new data is recorded in second record area, and the Part II of second logic access address more corresponding to new data is recorded in the 3rd recording areas.
In one embodiment of this invention, above-mentioned first record area separately records the first stroke more skew (offset) of new data and shade (mask), and the 4th recording areas separately records second the more skew of new data and shade.
In one embodiment of this invention, the above-mentioned physical page being written at least two more new datas comprises first record area and second record area.First record area is in order to record above-mentioned at least two the first stroke more new datas more among new data, and second record area is in order to record above-mentioned at least two more among new data second more new data.
In one embodiment of this invention, the logic access address of above-mentioned the first stroke more corresponding to new data and second logic access address more corresponding to new data are all recorded in first record area.
In one embodiment of this invention, the above-mentioned solid element be extracted is the chaotic solid element of a universe.
Exemplary embodiment of the present invention proposes a kind of Memory Controller, and for managing a type nonvolatile module, wherein this type nonvolatile module has multiple solid element, and each those solid element has multiple physical page.This Memory Controller comprises host interface, memory interface and memory management circuitry.Host interface is in order to be coupled to host computer system, and memory interface is in order to be coupled to type nonvolatile module.Memory management circuitry couples so far host interface memory interface therewith, and in order to configure multiple logical block with the solid element of demapping section, and set up logical block-solid element mapping table with the mapping relations between the solid element recording logical block and above-mentioned part.Memory management circuitry is also in order to receive at least two more new datas, and above-mentioned at least two Different Logic pages more among the corresponding above-mentioned logical page (LPAGE) of new data.Memory management circuitry also in order to extract solid element from above-mentioned solid element.Memory management circuitry also in order to by above-mentioned at least two more new data write to the same physical page of extracted solid element.
The embodiment of the present invention proposes a kind of memorizer memory devices, and it comprises connector, type nonvolatile module and Memory Controller.Type nonvolatile module has multiple solid element.Memory Controller couples so far type nonvolatile module connector therewith, and in order to configure multiple logical block with the solid element of demapping section, and set up logical block-solid element mapping table with the mapping relations between the solid element recording logical block and above-mentioned part.Memory Controller is also in order to from host system acceptance at least two more new data, and these at least two the Different Logic pages more among the corresponding above-mentioned logical page (LPAGE) of new data.Memory Controller also in order to extract solid element from above-mentioned solid element.Memory Controller also in order to by above-mentioned at least two more new data write to the same physical page of extracted solid element.
Based on above-mentioned, the embodiment of the present invention can write the more new data that two correspond to the Different Logic page, to improve the service efficiency of the storage area of solid element in the same physical page of solid element.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A is host computer system shown according to a first embodiment of the present invention and memorizer memory devices.
Figure 1B is the schematic diagram of computer, input/output device and memorizer memory devices shown by the embodiment of the present invention.
Fig. 1 C is the schematic diagram of host computer system shown by another embodiment of the present invention and memorizer memory devices.
Fig. 2 is the summary block scheme illustrating the memorizer memory devices shown in Figure 1A.
Fig. 3 is the summary block scheme of Memory Controller shown according to a first embodiment of the present invention.
Fig. 4 A is the summary block scheme of type nonvolatile module shown according to a first embodiment of the present invention.
Fig. 4 B is the example schematic of the physical page of physical blocks shown according to a first embodiment of the present invention.
Fig. 4 C is the example schematic of the physical page of physical blocks shown by another embodiment of the present invention.
Fig. 4 D is the example schematic of the physical page of physical blocks shown by another embodiment of the present invention.
Fig. 5 A and Fig. 5 B is the example schematic of management entity block shown according to a first embodiment of the present invention.
Fig. 6 A-6I is the example schematic of shown write data according to a first embodiment of the present invention.
Fig. 6 J and 6K is the example schematic of shown write data and execution data consolidation procedure according to a first embodiment of the present invention.
Fig. 7 is the process flow diagram of data managing method shown according to a first embodiment of the present invention.
Main element symbol description:
1000: host computer system
1100: computer
1102: microprocessor
1104: random access memory
1106: input/output device
1108: system bus
1110: data transmission interface
1202: mouse
1204: keyboard
1206: display
1208: printer
1212: Portable disk
1214: memory card
1216: solid state hard disc
1310: digital camera
1312:SD card
1314:MMC card
1316: memory stick
1318:CF card
1320: embedded storage device
100: memorizer memory devices
102: connector
104: Memory Controller
106: type nonvolatile module
202: memory management circuitry
204: host interface
206: memory interface
252: memory buffer
254: electric power management circuit
256: bug check and correcting circuit
410: first memory submodule group
420: second memory submodule group
410a: data bus
420a: data bus
410 (0)-410 (N), 420 (0)-420 (N): physical blocks
430: physical page
432,440: first record area
434,450: second record area
460: the three recording areas
470: the four recording areas
480,480 ': data bit element district
490,490 ': redundancy bit district
502: data field
504: idle district
506: system region
508: replace district
610 (0)-610 (S-1): solid element
710 (0)-710 (H): logical block
S702 ~ S710: the step of data managing method
ID0 ~ ID19: primary data
UD1 ~ UD15: more new data
Embodiment
In order to improve the service efficiency of the storage area of solid element, the present invention proposes a kind of data managing method, and its more new data two being corresponded to Different Logic access address writes in the same physical page of solid element.Below will describe the present invention in detail with several embodiment.
[the first embodiment]
Generally speaking, memorizer memory devices (also known as, memory storage system) comprises type nonvolatile module and controller (also known as, control circuit).Usual memorizer memory devices uses together with host computer system, data can be write to memorizer memory devices or read data from memorizer memory devices to make host computer system.
Figure 1A is host computer system shown according to a first embodiment of the present invention and memorizer memory devices.
Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Figure 1B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memorizer memory devices 100 is coupled by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memorizer memory devices 100.Such as, memorizer memory devices 100 can be the type nonvolatile storage device of Portable disk 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 1B.
Generally speaking, host computer system 1000 is to coordinate any system with storage data substantially with memorizer memory devices 100.Although in the present embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in an alternative embodiment of the invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile storage device is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 comprises embedded multi-media card (EmbeddedMMC, eMMC).It is worth mentioning that, embedded multi-media card is directly coupled on the substrate of host computer system.
Fig. 2 is the summary block scheme illustrating the memorizer memory devices shown in Figure 1A.
Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and type nonvolatile module 106.
In the present embodiment, connector 102 is compatible to advanced annex (Serial AdvancedTechnology Attachment, the SATA) standard of sequence.But, it must be appreciated, the present invention is not limited thereto, connector 102 can also be meet Institute of Electrical and Electric Engineers (Institute ofElectrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, safety digit (SecureDigital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other standards be applicable to.
Memory Controller 104 in order to perform with multiple logic gate of hardware pattern or firmware pattern implementation or steering order, and according to the instruction of host computer system 1000 carry out in type nonvolatile module 106 data write, read and the running such as to erase.In the present embodiment, Memory Controller 104 manages in order to the data managing method according to the embodiment of the present invention data being stored in type nonvolatile module 106.Data managing method according to the embodiment of the present invention will elaborate in following cooperation accompanying drawing.
Type nonvolatile module 106 is coupled to Memory Controller 104, and in order to store the data that host computer system 1000 writes.In the present embodiment, type nonvolatile module 106 is multilayer memory cell (Multi Level Cell, MLC) NAND quick-flash memory module.But, the present invention is not limited thereto, type nonvolatile module 106 also individual layer memory cell (Single Level Cell, SLC) NAND quick-flash memory module, other flash memory modules or other there is the memory module of identical characteristics.
Fig. 3 is the summary block scheme of Memory Controller shown according to a first embodiment of the present invention.
Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has multiple steering order, and when memorizer memory devices 100 operates, this little steering order can be performed and manage with the data managing method according to the present embodiment the data be stored in type nonvolatile module 106.
In the present embodiment, the steering order of memory management circuitry 202 carrys out implementation with firmware pattern.Such as, memory management circuitry 202 has microprocessor unit (not show) and ROM (read-only memory) (not shown), and this little steering order is burned onto in this ROM (read-only memory).When memorizer memory devices 100 operates, the data managing method that this little steering order can perform according to the embodiment of the present invention by microprocessor unit.
In an alternative embodiment of the invention, the steering order of memory management circuitry 202 can also source code pattern be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of type nonvolatile module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not show) and random access memory (not shown).Particularly, this ROM (read-only memory) has driving code section, and when Memory Controller 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in type nonvolatile module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order to perform the data managing method of the embodiment of the present invention.In addition, in an alternative embodiment of the invention, the steering order of memory management circuitry 202 a hardware pattern can also carry out implementation.
Host interface 204 is coupled to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In the present embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 can also be compatible to PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards be applicable to.
Memory interface 206 is coupled to memory management circuitry 202 and in order to access type nonvolatile module 106.That is, the data for writing to type nonvolatile module 106 can be converted to the receptible form of type nonvolatile module 106 via memory interface 206.
In an embodiment of the present invention, Memory Controller 104 also comprises memory buffer 252.Memory buffer 252 is coupled to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of type nonvolatile module 106.
In an embodiment of the present invention, Memory Controller 104 also comprises electric power management circuit 254.Electric power management circuit 254 is coupled to memory management circuitry 202 and in order to the power supply of control store storage device 100.
In an embodiment of the present invention, Memory Controller 104 also comprises bug check and correcting circuit 256.Bug check and correcting circuit 256 are coupled to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 256 can be that the corresponding data that this writes instruction produce corresponding bug check and correcting code (Error Checking andCorrecting Code, ECC Code), and the data of this write instruction corresponding can write in type nonvolatile module 106 with corresponding bug check and correcting code by memory management circuitry 202.Afterwards, can read bug check corresponding to these data and correcting code when memory management circuitry 202 reads data from type nonvolatile module 106, and bug check and correcting circuit 256 can according to this bug check and correcting code to read data execution error inspection and correction programs simultaneously.
Fig. 4 A is the summary block scheme of type nonvolatile module shown according to a first embodiment of the present invention.
Please refer to Fig. 4 A, type nonvolatile module 106 comprises first memory submodule group 410 and second memory submodule group 420.Such as, first memory submodule group 410 and second memory submodule group 420 are memory crystal grain (die) respectively.First memory submodule group 410 has physical blocks 410 (0)-410 (N) and second memory submodule group 420 has physical blocks 420 (0)-420 (N).Such as, first memory submodule group 410 and second memory submodule group 420 are coupled to Memory Controller 104 separately by independently data bus 410a and data bus 420a.But it must be appreciated, in an alternative embodiment of the invention, first memory submodule group 410 and second memory submodule group 420 also can couple by means of only 1 data bus and Memory Controller 104.First memory submodule group 410 has multiple physical page respectively with each physical blocks of second memory submodule group 420, and each physical page has at least one entity sector (sector), the physical page wherein belonging to same physical blocks can be written independently and side by side be erased.Such as, each physical blocks is made up of 128 physical page, and each physical page has 16 entity sectors.That is, be in the example of 512 bit groups (byte) in each entity sector, the capacity of each physical page is 8 kilobit tuples (Kilobyte, KB).But it must be appreciated, the present invention is not limited thereto, each physical blocks can be made up of 64 physical page, 256 physical page or other any physical page.
In more detail, physical blocks is the least unit of erasing.That is, each physical blocks contain minimal amount in the lump by the memory cell of erasing.Physical page is the minimum unit stylized.That is, physical page is the minimum unit of write data.But it must be appreciated, in an alternative embodiment of the invention, the least unit of write data can also be entity sector or other sizes.
It is worth mentioning that, describe for example although the embodiment of the present invention is the type nonvolatile module 106 comprising 2 storer submodule groups, the present invention is not limited thereto.Such as, in an alternative embodiment of the invention, type nonvolatile module 106 comprises 4 or 8 storer submodule groups.
Fig. 4 B is the example schematic of the physical page of physical blocks shown according to a first embodiment of the present invention.Fig. 4 C, Fig. 4 D are the example schematic of the physical page of physical blocks shown by different embodiments of the invention respectively.
Please refer to Fig. 4 B, each physical blocks 410 (0)-410 (N) and 420 (0)-420 (N) have a plurality of physical page 430.In the present embodiment, the capacity of each physical page 430 is 8KB, and comprises data bit element district 480 and redundancy bit district 490.Data bit element district 480 is in order to store user's data, and redundancy bit district 490 is in order to store the related system data of corresponding physical page 430.The data of said system, for example, bug check and correcting code (Error Checking andCorrecting Code, ECC Code) and the logic access address corresponding to user's data, skew (Offset) and shade (Mask) can be comprised.
Must understand, in other embodiments of the invention, the configuration mode of the storage data of physical page 430 not necessarily must as Fig. 4 B the mode that configures, and can be other configuration mode.For example, as shown in Figure 4 C, in an embodiment of the present invention, each physical page 430 is divided into first record area 432 and second record area 434 further.First record area 432 and second record area 434 can store the data of 4KB respectively.Wherein, the first record area 432 of same physical page 430 and the data stored by second record area 434 can correspond to same logical page (LPAGE) and also can correspond to two different logical page (LPAGE)s.Wherein, the data corresponding to two different logical page (LPAGE)s can write to same physical page 430 together.
In addition, must understand, each physical page 430 is except can being divided into two recording areas, and in other embodiments of the present invention, each physical page 430 can by the more recording areas of differentiation.Such as: each physical page 430 is divided into three, a four or more recording areas, and the data that two or more correspond to different logical page (LPAGE) can be stored.Wherein, the data corresponding to multiple different logical page (LPAGE) can write to same physical page 430 together.
In an embodiment of the present invention, physical page 430 is divided into several recording areas, and each recording areas respectively includes bit district and redundancy bit district.Please refer to Fig. 4 D, physical page 430 is divided into first record area 440, second record area 450, the 3rd recording areas 460 and the 4th recording areas 470.Wherein, first record area 440, second record area 450, the 3rd recording areas 460 and the 4th recording areas 470 respectively have data bit element district 480 ' and redundancy bit district 490 '.Each data bit element district 480 ' is in order to store user's data of 2KB, and four redundancy bit districts 490 ' are in order to store the related system data of corresponding physical page 430, such as: bug check and correcting code (ECC Code), logic access address, skew (Offset) and shade (Mask).
Fig. 5 A and Fig. 5 B is the example schematic of management entity block illustrated according to a first embodiment of the present invention.
Please refer to Fig. 5 A, physical blocks 410 (0)-410-(N) and physical blocks 420 (0)-420 (N) can be logically grouped into data field 502, idle district 504, system region 506 and replace district 508 by the memory management circuitry 202 of Memory Controller 104.
Belonging to data field 502 in logic with the physical blocks in idle district 504 is in order to store the data coming from host computer system 1000.Specifically, the physical blocks of data field 502 is the physical blocks being regarded as storage data, and the physical blocks in idle district 504 is the physical blocks in order to replacement data district 502.That is, when receiving the data that write instruction writes with wish from host computer system 1000, memory management circuitry 202 can extract physical blocks from idle district 504, and data is write in extracted physical blocks, with the physical blocks in replacement data district 502.
The physical blocks belonging to system region 506 is in logic in order to register system data.Such as, system data comprises manufacturer about type nonvolatile module and model, the physical blocks number of type nonvolatile module, the physical page number etc. of each physical blocks.
Belonging to the physical blocks replaced in district 508 is in logic replace program, with replacing damaged physical blocks for bad physical blocks.Specifically, if replace in district 508 still have normal physical blocks and the physical blocks of data field 502 is damaged time, memory management circuitry 202 can extract normal physical blocks to change the physical blocks of damage from replacement district 508.It must be appreciated, in the present embodiment, memory management circuitry 202 be replace in district 508 belong to first memory submodule group 410 normal physical blocks to replace the bad physical blocks in first memory submodule group 410, and with replace in district 508 belong to second memory submodule group 420 normal physical blocks to replace the bad physical blocks in second memory submodule group 420, make thus memory management circuitry 202 perform write instruction time still utilize data bus 410a and data bus 420a to write data in parallel simultaneously.
Please refer to Fig. 5 B, data field 502 and the physical blocks 410 (0)-410 (S-1) in idle district 504 can be grouped into multiple solid element with physical blocks 420 (0)-420 (S-1) by memory management circuitry 202, and in units of solid element, carry out management entity block.Such as, physical blocks 410 (0)-410 (S-1) and physical blocks 420 (0)-420 (S-1) can be paired to be grouped into solid element 610 (0)-610 (S-1).In the present embodiment, each solid element is made up of 2 physical blocks belonging to different storer submodule group respectively.But, it must be appreciated, the present invention is not limited thereto.In another embodiment, each solid element can be made up of a physical blocks.That is, memory management circuitry 202 manages in units of each physical blocks.Or in another embodiment, each solid element also can be made up of at least one physical blocks in same storer submodule group or different memory submodule group.
In addition, memory management circuitry 202 meeting configuration logic unit 710 (0)-710 (H) is with the solid element in mapping (enum) data district 502, wherein each logical block has the physical page of the solid element that multiple logical page (LPAGE) is answered with mapping pair in order, and each logical page (LPAGE) has the entity sector of the physical page that multiple logic sector is answered with mapping pair.In the present embodiment, memory management circuitry 202 meeting service logic unit-solid element mapping table (logical unit-physical unit mapping table) is to record the mapping relations of the solid element of logical block 710 (0)-710 (H) and data field 502.Such as, when host computer system 1000 is for accessing a certain logic access address, the logic access address that host computer system 1000 can access by memory management circuitry 202 is converted to corresponding logical block, logical page (LPAGE) or logic sector, and by logical block-solid element mapping table access data in the physical page of the solid element of correspondence.
In the present embodiment, memory management circuitry 202 can extract solid element as universe confusion (Global Random) solid element from idle district 504, and the data (be also called and upgrade data) be contained in from the write instruction of host computer system 1000 is write in the chaotic solid element of universe.In the present embodiment, memory management circuitry 202 can correspond respectively to the same physical page of data storing at the chaotic solid element of universe of the Different Logic page.Must understand ground, the solid element be extracted although above-mentioned is taken as the chaotic solid element of universe in use, and right the present invention is not as limit.In detail, memory management circuitry 202 also can from system region 506, data field 502 or replace district 508 and extract a solid element, and above-mentioned received more new data to be write in the same physical page of extracted solid element.
Specifically, when memorizer memory devices 100 receives write instruction from host computer system 1000, the data come from the write instruction of host computer system 1000 can be write in the chaotic solid element of universe in order.And, when the chaotic solid element of this universe is fully written, memory management circuitry 202 can extract solid element again as the chaotic solid element of another universe from idle district 504, to continue to write the corresponding more new data coming from the write instruction of host computer system 1000.Until when having arrived a higher limit as the number of the solid element of the chaotic solid element of universe, memory management circuitry 202 can perform data consolidation procedure, to make the data be stored in the chaotic solid element of universe become invalid data, and the chaotic solid element of the universe afterwards stored data being all invalid data associates go back to idle district 504.
Fig. 6 A-6K is the example schematic of shown write data according to a first embodiment of the present invention.
For convenience of description, in this tentation data district 502, there are 5 solid elements, idle district 504 has 4 solid elements, each solid element has 4 physical page, data for writing to each solid element must be written into according to the order of physical page, and are 3 as the higher limit of the solid element number of the chaotic solid element of universe.
Please refer to Fig. 6 A, in the original state of memorizer memory devices 100, the logical page (LPAGE) of logical block 710 (0)-710 (4) can the physical page of the solid element 610 (0)-610 (4) in mapping (enum) data district 502 in order, and idle district 504 has solid element 610 (5)-610 (8).That is, the mapping relations that memory management circuitry 202 can record between logical block 710 (0)-710 (4) and solid element 610 (0)-610 (4) in logical block-solid element mapping table, and be considered as the physical page of solid element 610 (0)-610 (4) to store the data (that is, primary data ID0-ID19) of the logical page (LPAGE) belonging to logical block 710 (0)-710 (4).It must be appreciated, when memorizer memory devices 100 just dispatches from the factory, primary data ID0-ID19 may be empty data.In addition, memory management circuitry 202 can record solid element 610 (5)-610 (8) available in idle district 504.
Please refer to Fig. 6 B, memory management circuitry 202 will upgrade the partial data of the 1st logical page (LPAGE) of logical block 710 (0) and the 0th logical page (LPAGE) of logical block 710 (1), wherein the 1st data that logical page (LPAGE) is updated of logical block 710 (0) are UD1, and the 0th of logical block 710 (1) the data that logical page (LPAGE) is updated are UD2.Above-mentioned two more new data UD1 and UD2 be respectively the more new data of the Different Logic page, therefore correspond to different logic access addresses, and the data volume of each more new data UD1 or UD2 is all not more than 4KB, therefore the total amount of data of two more new data UD1 and UD2 can not be greater than the capacity (i.e. 8KB) of single physical page, and same physical page can be write to together.More new data UD1 and UD2 is before being written into nonvolatile memory module 106, and more new data UD1 and UD2 can be temporarily stored in memory buffer 252 by memory management circuitry 202.Afterwards, memory management circuitry 202 can extract solid element 610 (5) as the chaotic solid element of first universe from idle district 504, and assign the instruction that stylizes, to write to the 0th physical page of solid element 610 (5) together with more new data UD1 with UD2 being temporary in memory buffer 252.
Please refer to Fig. 6 C, hookup 6B, memory management circuitry 202 separately upgrades the 1st logical page (LPAGE) of logical block 710 (2) and the partial data of the 2nd logical page (LPAGE), its more new data be respectively UD3 and UD4.Wherein above-mentioned two more new data UD3 and UD4 be respectively the more new data of the Different Logic page, therefore correspond to different logic access addresses.In addition, the data volume of each more new data UD3 or UD4 is also all not more than 4KB, therefore memory management circuitry 202 first more can will be temporarily stored in memory buffer 252 by new data UD3 and UD4, the 1st physical page of solid element 610 (5) will be write to again together with more new data UD3 with UD4 being temporary in memory buffer 252 afterwards.
Please refer to Fig. 6 D, hookup 6C, memory management circuitry 202 separately upgrades the 2nd logical page (LPAGE) of logical block 710 (0), its more new data be UD5.Wherein more new data UD5 is greater than 4KB and is not more than 8KB, therefore more new data UD5 can be write to the 2nd physical page of solid element 610 (5) by memory management circuitry 202 individually.
Please refer to Fig. 6 E, hookup 6D, memory management circuitry 202 separately upgrades the partial data of the 3rd logical page (LPAGE) of logical block 710 (2) and the 3rd logical page (LPAGE) of logical block 710 (1), its more new data be respectively UD6 and UD7.Wherein above-mentioned two more new data UD6 and UD7 be respectively the more new data of the Different Logic page, therefore correspond to different logic access addresses.In addition, the data volume of each more new data UD6 or UD7 is also all not more than 4KB, therefore memory management circuitry 202 first more can will be temporarily stored in memory buffer 252 by new data UD6 and UD7, the 3rd physical page of solid element 610 (5) will be write to again together with more new data UD6 with UD7 being temporary in memory buffer 252 afterwards.
Please refer to Fig. 6 F, hookup 6D, memory management circuitry 202 separately upgrades the 0th logical page (LPAGE) of logical block 710 (2), its more new data be UD8, and more new data UD8 is greater than 4KB and is not more than 8KB.Because the chaotic solid element 610 (5) of first universe is without storage area, therefore, memory management circuitry 202 can extract from idle district 504 solid element 610 (6) as the chaotic solid element of second universe and assign stylize instruction with by this more new data UD8 write to the 0th physical page of solid element 610 (6) individually.
Please refer to Fig. 6 G, hookup 6F, memory management circuitry 202 separately upgrades the 2nd logical page (LPAGE) of logical block 710 (4), its more new data be UD9.Wherein more new data UD9 is greater than 4KB and is not more than 8KB, therefore memory management circuitry 202 meeting more will write to the 1st physical page of solid element 610 (6) by new data UD9 individually.
Please refer to Fig. 6 H, hookup 6G, memory management circuitry 202 separately upgrades the partial data of the 2nd and the 3rd logical page (LPAGE) of logical block 710 (3), its more new data be respectively UD10 and UD11.Wherein above-mentioned two more new data UD10 and UD11 be respectively the more new data of the Different Logic page, therefore correspond to different logic access addresses.In addition, the data volume of each more new data UD10 or UD11 is all not more than 4KB, therefore memory management circuitry 202 first more can will be temporarily stored in memory buffer 252 by new data UD10 and UD11, the 2nd physical page of solid element 610 (6) will be write to again together with more new data UD10 with UD11 being temporary in memory buffer 252 afterwards.
Please refer to Fig. 6 I, hookup 6H, memory management circuitry 202 separately upgrades the partial data of the 1st logical page (LPAGE) of logical block 710 (3) and the 1st logical page (LPAGE) of logical block 710 (4), its more new data be respectively UD12 and UD13.Wherein above-mentioned two more new data UD12 and UD13 be respectively the more new data of the Different Logic page, therefore correspond to different logic access addresses.In addition, the data volume of each more new data UD12 or UD13 is all not more than 4KB, therefore memory management circuitry 202 first more can will be temporarily stored in memory buffer 252 by new data UD12 and UD13, the 3rd physical page of solid element 610 (6) will be write to again together with more new data UD12 with UD13 being temporary in memory buffer 252 afterwards.
By that analogy, host computer system 1000 can write in the chaotic solid element of universe for the data stored by memory management circuitry 202 in order.Particularly, when the number of the chaotic solid element of universe reaches 3, memory management circuitry 202 can perform data consolidation procedure in the lump when performing write instruction, is exhausted to prevent the solid element in idle district 504.
Fig. 6 J and 6K is the example schematic of shown write data and execution data consolidation procedure according to a first embodiment of the present invention.
Please refer to Fig. 6 J, hookup 6I, memory management circuitry 202 separately upgrades the partial data of the 3rd logical page (LPAGE) of logical block 710 (0) and the 3rd logical page (LPAGE) of logical block 710 (4), its more new data be respectively UD14 and UD15.Because the chaotic solid element 610 (6) of second universe is without storage area, therefore, memory management circuitry 202 can be extracted solid element 610 (7) as the chaotic solid element of the 3rd universe and assign the instruction that stylizes to write to the 0th physical page of solid element 610 (7) together with this more new data UD14 with UD15 from idle district 504.Particularly, owing to reaching 3 as the number of the chaotic solid element of universe, therefore, memory management circuitry 202 can perform data consolidation procedure after performing the running of the write shown in Fig. 6 J.That is, in this example, in execution this time between write order period, memory management circuitry 202 can perform data consolidation procedure in the lump.
Please refer to Fig. 6 K, when supposing that memory management circuitry 202 selects logical block 710 (0) to carry out data merging, memory management circuitry 202 can recognition logic unit 710 (0) be mapping entity unit 610 (0), extract solid element 610 (8) from idle district 504, and the valid data belonging to logical block 710 (0) in solid element 610 (0) and the chaotic solid element of universe are copied in solid element 610 (8).Specifically, the data ID 0 in solid element 610 (0) can write in the 0th physical page of solid element 610 (8) by memory management circuitry 202.Afterwards, the more new data UD1 in solid element 610 (5) writes in the 1st physical page of solid element 610 (8) together with the data be not updated in the 1st physical page of solid element 610 (0) (not namely being updated the remainder data that data UD1 upgrades in data ID 1) by memory management circuitry 202 again.Moreover the more new data UD5 in solid element 610 (5) also can write in the 2nd physical page of solid element 610 (8) together with the data be not updated in the 2nd physical page of solid element 610 (0) (not namely being updated the remainder data that data UD5 upgrades in data ID 2) by memory management circuitry 202.In addition, the more new data UD14 in solid element 610 (7) also can write in the 3rd physical page of solid element 610 (8) together with the data be not updated in the 3rd physical page of solid element 610 (0) (not namely being updated the remainder data that data UD14 upgrades in data ID 3) by memory management circuitry 202.Memory management circuitry 202 also can by solid element 610 (5) and 610 (7) in order to store the spaces mark of more new data UD1, UD5 and UD14 for invalid (as shown in oblique line).Afterwards, memory management circuitry 202 can perform to solid element 610 (0) running of erasing, in logical block-solid element mapping table, logical block 710 (0) is remapped to solid element 610 (8), and solid element 610 (0) is associated to idle district 504.
Such as, when performing next write instruction, memory management circuitry 202 can perform data consolidation procedure to logical block 710 (1), and when performing next write instruction afterwards again, memory management circuitry 202 can perform data consolidation procedure to logical block 710 (2).Therefore, before the storage area of solid element 610 (7) is filled, the data in solid element 610 (5) all can become invalid data.Base this, memory management circuitry 202 can to solid element 610 (5) perform erase running and the solid element 610 (5) after erasing is associated go back to idle district 504.
Base this, according to above-mentioned running, memory management circuitry 202 is sustainable to be associated go back to idle district 504 using the solid element storing invalid data and from idle district 504, extracts solid element as the chaotic solid element of universe.
Fig. 7 is the process flow diagram of data managing method shown according to a first embodiment of the present invention.
Please refer to Fig. 7, in step S702, the solid element of nonvolatile memory module 106 is at least grouped into data field 502 and idle district 504 by memory management circuitry 202.Then, in step S704, memory management circuitry 202 configures multiple logical block with the solid element in mapping (enum) data district 502, and sets up logical block-solid element mapping table with the mapping relations between the solid element recording logical block and data field 502.Then, in step S706, memory management circuitry 202 receives at least two more new datas, wherein above-mentioned at least two logic access addresses that more new data is corresponding different.In addition, at least two that receive more new data such as can keep in memory buffer 252.Then, in step S708, memory management circuitry 202 extracts solid element from idle district 504.The solid element be extracted such as can be used as the chaotic solid element of universe.Afterwards, in step S710, memory management circuitry 202 by above-mentioned be temporary at least two of memory buffer 252 more new data write to the same physical page of extracted solid element.
In the first embodiment of the invention, the data structure of physical page 430 as shown in Figure 4 B, wherein above-mentioned at least two more new data can be written into the data bit element district 480 of same physical page 430, and above-mentioned at least two logic access addresses more corresponding to new data can be written into the redundancy bit district 490 of same physical page 430.In addition, in an embodiment of the present invention, above-mentioned at least two skews (offset) more corresponding to new data and shade (mask) also can be written into the redundancy bit district 490 of same physical page 430.Wherein, above-mentioned skew refers to the distance of the start address of the sector of more new data relative to the logic access address of this logical page (LPAGE), and shade refers to which data is updated from the start address of the more sector of new data.Therefore, memory management circuitry 202 by being stored in the logic access address in redundancy bit district 490, skew and shade, can judge which data in corresponding logical page (LPAGE) are updated.
[the second embodiment]
The memorizer memory devices of second embodiment of the invention and host computer system are the memorizer memory devices and the host computer system that are same as the first embodiment in essence, wherein difference part is that the data structure of the physical page 430 of the second embodiment is as shown in Figure 4 C, and wherein each physical page 430 is divided into first record area 432 and second record area 434.First record area 432 and second record area 434 can store the data of 4KB respectively.Wherein, the first record area 432 of same physical page 430 and the data stored by second record area 434 can correspond to same logical page (LPAGE) and also can correspond to two different logical page (LPAGE)s.Wherein, the data corresponding to two different logical page (LPAGE)s can write to same physical page 430 together.Furthermore, above-mentioned at least two more new data can be written into first record area 432 and second record area 434 respectively, wherein first record area 432 is in order to record above-mentioned at least two the first stroke more new datas more among new data, and second record area 432 is in order to record above-mentioned at least two more among new data second more new data.In addition, first record area 432 and second record area 434 also can record the first stroke more new data and second the logic access address more corresponding to new data, skew and shade respectively, for memory management circuitry 202 judge the first stroke more new data and second more new data which data in corresponding respectively logical page (LPAGE) be updated.In addition, in an embodiment of the present invention, above-mentioned the first stroke more new data and second more new data be recorded in first record area 432 and second record area 434 respectively, and the logic access address of the first stroke more corresponding to new data and second logic access address more corresponding to new data are all recorded in first record area 432, second record area 434 does not then record second logic access address more corresponding to new data.
[the 3rd embodiment]
The memorizer memory devices of third embodiment of the invention and host computer system are the memorizer memory devices and the host computer system that are same as the first embodiment in essence, wherein difference part is that the data structure of the physical page 430 of the 3rd embodiment is as shown in Figure 4 D, wherein each physical page 430 is divided into first record area 440, second record area 450, the 3rd recording areas 460 and the 4th recording areas 470, and first record area 440, second record area 450, the 3rd recording areas 460 and the 4th recording areas 470 respectively have data bit element district 480 ' and redundancy bit district 490 '.In the present embodiment, the redundancy bit district 490 ' of first record area 440, second record area 450, the 3rd recording areas 460 and the 4th recording areas 470 is except misregistration inspection and correcting code (ECC Code), also can record the system data of 8 bit groups (8Byte), 2 bit groups (2Byte), 2 bit groups (2Byte) and 2 bit groups (2Byte) respectively again, as shown in Figure 4 D.In addition, in the present embodiment, each logic access address more corresponding to new data can represent with 4 bit groups (4Byte), and each skew more corresponding to new data and shade all can represent with 1 bit group (1Byte).Wherein above-mentioned at least two the logic access addresses of the first stroke more corresponding to new data more among new data are recorded in the redundancy bit district 490 ' of first record area 440, and the Part I (such as: the first two bit group) of the above-mentioned logic access address of at least two more among new data second more corresponding to new data is recorded in the redundancy bit district 490 ' of second record area 450, and the Part II of second logic access address more corresponding to new data (such as: latter two bit group) is recorded in the redundancy bit district 490 ' of the 3rd recording areas 460.In addition, the redundancy bit district 490 ' of first record area 440 separately records the above-mentioned the first stroke more skew of new data and shade, and the redundancy bit district 490 ' of the 4th recording areas separately records above-mentioned second the more skew of new data and shade.Therefore, memory management circuitry 202 by being stored in the logic access address in each redundancy bit district 490 ', skew and shade, can judge which data in corresponding logical page (LPAGE) are updated.It must be appreciated, this is not to be limited in which redundancy bit district 490 ' that above-mentioned at least two logic access addresses more corresponding to new data, skew and shade are stored in physical page 430, and visual other needs adjust.
In sum, the data managing method of the embodiment of the present invention can write the more new data that two correspond to Different Logic access address, to improve the service efficiency of the storage area of solid element in the same physical page of solid element.
Although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention, the those of ordinary skill in any art, when doing a little change and retouching, and does not depart from the spirit and scope of the present invention.
Claims (18)
1. a data managing method, the data of a type nonvolatile module are write to for managing a host computer system, wherein this type nonvolatile module has multiple solid element, and each those solid element has multiple physical page, this data managing method comprises:
Configure multiple logical block with those solid elements of demapping section, wherein each those logical block has multiple logical page (LPAGE);
Set up one logical block-solid element mapping table with the mapping relations between those solid elements recording those logical blocks and above-mentioned part;
Receive from least two of this host computer system more new datas, wherein these at least two the Different Logic pages more among new data those logical page (LPAGE)s corresponding;
A solid element is extracted from those solid elements; And
By these at least two more new data write to the same physical page of this extracted solid element.
2. data managing method according to claim 1, this physical page being wherein written into these at least two more new datas comprises a first record area, a second record area, one the 3rd recording areas and one the 4th recording areas, this first record area and this second record area are in order to record these at least two the first stroke more new datas more among new data, and the 3rd recording areas and the 4th recording areas are in order to record these at least two more among new data one second more new data.
3. data managing method according to claim 2, wherein the logic access address of this first stroke more corresponding to new data is recorded in this first record area, one Part I of this second the logic access address more corresponding to new data is recorded in this second record area, and a Part II of this second the logic access address more corresponding to new data is recorded in the 3rd recording areas.
4. data managing method according to claim 3, wherein this first record area separately record this first stroke more new data one skew (offset) and a shade (mask), and the 4th recording areas separately record this second more new data one skew and a shade.
5. data managing method according to claim 1, this physical page being wherein written into these at least two more new datas comprises a first record area and a second record area, this first record area is in order to record these at least two the first stroke more new datas more among new data, and this second record area is in order to record these at least two more among new data one second more new data.
6. data managing method according to claim 5, wherein the logic access address of this first stroke more corresponding to new data and this second the logic access address more corresponding to new data are all recorded in this first record area.
7. data managing method according to claim 1, this solid element be wherein extracted is the chaotic solid element of a universe.
8. a Memory Controller, for managing a type nonvolatile module, wherein this type nonvolatile module has multiple solid element, and each those solid element has multiple physical page, and this Memory Controller comprises:
One host interface, in order to be coupled to a host computer system;
One memory interface, in order to be coupled to this type nonvolatile module; And
One memory management circuitry, be coupled to this host interface and this memory interface, wherein this memory management circuitry is in order to configure multiple logical block with those solid elements of demapping section, and set up one logical block-solid element mapping table with the mapping relations between those solid elements recording those logical blocks and above-mentioned part, wherein each those logical block has multiple logical page (LPAGE)
Wherein this memory management circuitry is also in order to receive at least two more new datas, and these at least two the Different Logic pages more among new data those logical page (LPAGE)s corresponding,
Wherein this memory management circuitry also in order to extract a solid element from those solid elements,
Wherein this memory management circuitry also in order to by received these at least two more new data write to the same physical page of this extracted solid element.
9. Memory Controller according to claim 8, this physical page being wherein written into these at least two more new datas comprises a first record area, a second record area, one the 3rd recording areas and one the 4th recording areas, this first record area and this second record area are in order to record these at least two the first stroke more new datas more among new data, and the 3rd recording areas and the 4th recording areas are in order to record these at least two more among new data one second more new data.
10. Memory Controller according to claim 9, wherein the logic access address of this first stroke more corresponding to new data is recorded in this first record area, one Part I of this second the logic access address more corresponding to new data is recorded in this second record area, and a Part II of this second the logic access address more corresponding to new data is recorded in the 3rd recording areas.
11. Memory Controllers according to claim 10, wherein this first record area separately record this first stroke more new data one skew (offset) and a shade (mask), and the 4th recording areas separately record this second more new data one skew and a shade.
12. Memory Controllers according to claim 8, this physical page being wherein written into these at least two more new datas comprises a first record area and a second record area, this first record area is in order to record these at least two the first stroke more new datas more among new data, and this second record area is in order to record these at least two more among new data one second more new data.
13. 1 kinds of memorizer memory devices, comprising:
A connector, in order to be coupled to a host computer system;
One type nonvolatile module, has multiple solid element; And
One Memory Controller, be coupled to this connector and this type nonvolatile module, wherein this Memory Controller is in order to configure multiple logical block with those solid elements of demapping section, and set up one logical block-solid element mapping table with the mapping relations between those solid elements recording those logical blocks and above-mentioned part
Wherein this Memory Controller is also in order to receive at least two more new datas from this host computer system, and these at least two the Different Logic pages more among new data those logical page (LPAGE)s corresponding,
Wherein this Memory Controller also in order to extract a solid element from those solid elements,
Wherein this Memory Controller also in order to by received these at least two more new data write to the same physical page of this solid element be extracted.
14. memorizer memory devices according to claim 13, this physical page being wherein written into these at least two more new datas comprises a first record area, a second record area, one the 3rd recording areas and one the 4th recording areas, this first record area and this second record area are in order to record these at least two the first stroke more new datas more among new data, and the 3rd recording areas and the 4th recording areas are in order to record these at least two more among new data one second more new data.
15. memorizer memory devices according to claim 14, wherein the logic access address of this first stroke more corresponding to new data is recorded in this first record area, one Part I of this second the logic access address more corresponding to new data is recorded in this second record area, and a Part II of this second the logic access address more corresponding to new data is recorded in the 3rd recording areas.
16. memorizer memory devices according to claim 15, wherein this first record area separately record this first stroke more new data one skew (offset) and a shade (mask), and the 4th recording areas separately record this second more new data one skew and a shade.
17. memorizer memory devices according to claim 13, this physical page being wherein written into these at least two more new datas comprises a first record area and a second record area, this first record area is in order to record these at least two the first stroke more new datas more among new data, and this second record area is in order to record these at least two more among new data one second more new data.
18. memorizer memory devices according to claim 17, wherein the logic access address of this first stroke more corresponding to new data and this second the logic access address more corresponding to new data are all recorded in this first record area.
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