CN102053920B

CN102053920B - Data writing method, flash memory controller and flash memory system

Info

Publication number: CN102053920B
Application number: CN200910207788A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2009-10-30
Filing date: 2009-10-30
Publication date: 2012-09-05
Anticipated expiration: 2029-10-30
Also published as: CN102053920A

Abstract

The invention relates to a data writing method, a flash memory controller and a flash memory system. The data writing method is used for writing data from a host system into a flash memory chip, and comprises the following steps of: configuring a plurality of logical page addresses; grouping the logical page addresses to form a plurality of logical blocks; and recording the data scattering degree of the logical blocks. The data writing method also comprises the following steps of: receiving written data from the host system; judging a logical block to which a logical address to be written by the host system belongs; and writing the written data into the flash memory chip according to the data scattering degree of the logical block to be written, wherein the data scattering degrees of the logical blocks are less than or equal to a data scattering degree threshold of the logical blocks. By the data writing method, the flash memory controller and the flash memory system, the time for executing an instruction written by a host can be effectively shortened.

Description

Method for writing data and flash controller and flash-memory storage system

Technical field

The present invention relates to a kind of method for writing data that is used for flash memory, relate in particular to and a kind ofly can be efficiently data be write to the method for writing data of flash memory and flash controller and the flash-memory storage system that uses the method.

Background technology

Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume is little and characteristic such as no mechanical structure, the most suitable being used on the battery-powered portable electronic product.For example, solid state hard disc is exactly a kind of with the memory storage of nand flash memory as medium, and extensively is disposed in the notebook computer as main memory storage.

In general, the flash chip of flash memory device (chip) can be divided into a plurality of physical blocks, and wherein physical blocks also is divided into a plurality of physical page, is the unit of writing of flash memory and physical blocks is the unit of erasing and the physical page of flash memory.Because when stylizing the memory cell of flash memory; Only can the fill order to stylize (promptly; Only can the value of memory cell be turned to 0 by 1 formula); Therefore can't the physical page (that is, having the page of legacy data) that stylize directly be write, but can stylize again after must earlier this physical page being erased.Particularly, because erasing of flash memory be to be unit with the physical blocks, the physical page that therefore will have a legacy data when desire is carried out and is erased when operating, and must erase to the whole physical blocks under this physical page.Therefore; The physical blocks of flash chip can be divided into data field and spare area; Wherein the physical blocks of data field is the physical blocks that has been used for storing data, and the physical blocks in the spare area is the physical blocks that is not used, wherein when host computer system desires to write data to flash memory device; The control circuit of flash memory device can extract physical blocks and write data from the spare area, and the physical blocks of being extracted can be associated as the data field.And after the physical blocks of data field was performed the running of erasing (erase operation), the physical blocks of having erased can be associated as the spare area.

Because host computer system is to write with logical address, and host computer system often can not write according to the order of logical address when writing data to logical address.Base this, when flash memory device need be erased when running to physical blocks, flash memory device need spend sizable time and put valid data and invalid data in the physical blocks in order.Therefore, how being lifted at the speed that flash memory writes data is the target that these those skilled in the art endeavour.

Summary of the invention

The purpose of this invention is to provide a kind of method for writing data, it can shorten the time that writes data to flash memory effectively.

Another purpose of the present invention provides a kind of flash controller, and it can shorten the time that writes data to flash memory effectively.

Another object of the present invention provides a kind of flash-memory storage system, and it can shorten the time that writes data to flash memory effectively.

The embodiment of the invention provides a kind of method for writing data, is used for the data that come from host computer system are write to flash chip, and wherein this flash chip comprises a plurality of physical blocks, and each physical blocks has a plurality of physical page address.The notebook data wiring method comprises a plurality of logical page addresses of configuration; Logical page address is grouped into a plurality of blocks; And the data that write down each blocks degree at random, wherein the data of each blocks degree at random is the number of physical blocks that is used to store the data of the blocks that belongs to corresponding.The notebook data wiring method also comprises from host computer system receiving and writes data, wherein this to write data are one first logical page addresses that are written among the logical page address, and this first logical page address belongs to one first blocks among the blocks.The notebook data wiring method also comprises the one first physical page address of obtaining among the physical page address.The notebook data wiring method comprises that also the data degree at random of foundation first blocks and the first physical page address of being obtained write data with this and write in the flash chip, and wherein the data of each blocks degree at random is neither greater than blocks data degree threshold value at random.

The embodiment of the invention provides a kind of flash controller, is used for the data that come from host computer system are write to flash chip, and wherein this flash chip comprises a plurality of physical blocks, and each physical blocks has a plurality of physical page address.This flash controller comprises microprocessor unit, flash interface unit, host interface unit and MMU.The flash interface unit is electrically connected to microprocessor unit, in order to be electrically connected to above-mentioned flash chip.Host interface unit is electrically connected to microprocessor unit, in order to be electrically connected to host computer system.MMU is electrically connected to microprocessor unit; In order to dispose a plurality of logical page addresses; Logical page address is grouped into a plurality of blocks; And the data that write down each blocks degree at random, wherein the data of each blocks degree at random is the number of physical blocks that is used to store the data of the blocks that belongs to corresponding.In addition, host interface unit receives one and writes data from host computer system, wherein this to write data are one first logical page addresses that are written among the logical page address, and first logical page address belongs to one first blocks among the blocks.In addition, MMU is obtained one first physical page address among the physical page address.Moreover; The data degree at random of MMU foundation first blocks and the first physical page address of being obtained write data with this and write in the flash chip, and wherein the data of each blocks degree at random is neither greater than blocks data degree threshold value at random.

The embodiment of the invention provides a kind of flash-memory storage system, and it comprises flash chip, connector and flash controller.Flash chip has a plurality of physical blocks and each physical blocks has a plurality of physical page address.Connector is in order to be electrically connected to host computer system.Flash controller is electrically connected to flash chip and connector; In order to dispose a plurality of logical page addresses; Logical page address is grouped into a plurality of blocks; And write down each blocks data recorded degree at random, wherein the data of each blocks degree at random is the number of physical blocks that is used to store the data of the blocks that belongs to corresponding.In addition, flash controller receives one and writes data from host computer system, wherein this to write data are one first logical page addresses that are written among the logical page address, and this first logical page address belongs to one first blocks among the blocks.In addition, flash controller is obtained one first physical page address among the physical page address.Moreover; The data degree at random of flash controller foundation first blocks and the first physical page address of being obtained write data with this and write in the flash chip, and wherein the data of each blocks degree at random is neither greater than blocks data degree threshold value at random.

Based on above-mentioned, the data that the embodiment of the invention can be avoided being stored are too disperseed, and shorten effectively thus and carry out the time that main frame writes instruction.

For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and combines accompanying drawing to elaborate as follows.

Description of drawings

Figure 1A is the structural representation that first embodiment of the invention is used the host computer system of flash memory device.

Figure 1B is the synoptic diagram of computer, input/output device and the flash memory device of the embodiment of the invention.

Fig. 1 C is the host computer system of another embodiment of the present invention and the synoptic diagram of flash memory device.

Fig. 1 D is the structural representation of flash memory device among Figure 1A.

Fig. 2 is the structural representation of the flash controller of another embodiment of the present invention.

Fig. 3 A is the structural representation of the flash chip of first embodiment of the invention.

Fig. 3 B is the logical page address of first embodiment of the invention and the mapping synoptic diagram of physical page address.

Fig. 4 A and Fig. 4 B are the synoptic diagram that a logical page (LPAGE) of first embodiment of the invention changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table.

Fig. 5 A and Fig. 5 B are the synoptic diagram that another logical page (LPAGE) of first embodiment of the invention changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table.

Fig. 6 A and Fig. 6 B are the synoptic diagram that the another logical page (LPAGE) of first embodiment of the invention changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table.

Fig. 7 A, Fig. 7 B and Fig. 7 C are that data of first embodiment of the invention write synoptic diagram.

Fig. 8 A and Fig. 8 B are that another data of first embodiment of the invention write synoptic diagram.

Fig. 9 A and Fig. 9 B are that the another data of first embodiment of the invention write synoptic diagram.

Figure 10 is the process flow diagram of the method for writing data of first embodiment of the invention.

Figure 11 is the process flow diagram of the detailed step of step S1007 among Figure 10.

Figure 12 A and Figure 12 B are that data of second embodiment of the invention write synoptic diagram.

Figure 13 A and Figure 13 B are that another data of second embodiment of the invention write synoptic diagram.

Figure 14 A and Figure 14 B are that the another data of second embodiment of the invention write synoptic diagram.

Figure 15 is the process flow diagram of the method for writing data of second embodiment of the invention.

Figure 16 A and 16B are the process flow diagrams of the detailed step of step S1507 among Figure 15.

The main element symbol description:

1000: host computer system; 1100: computer;

1102: microprocessor; 1104: RAS;

1106: input/output device; 1108: system bus;

1110: data transmission interface; 1202: mouse;

1204: keyboard; 1206: display;

1208: printer; 1212: carry-on dish;

1214: storage card; 1216: solid state hard disc;

1310: digital camera; The 1312:SD card;

The 1314:MMC card; 1316: memory stick;

The 1318:CF card; 1320: embedded memory storage;

100: flash memory device; 102: connector;

104,104 ': flash controller; 106: flash chip;

122-(0)～122-(N): physical blocks; 202: microprocessor unit;

204: MMU; 206: host interface unit;

208: the flash interface unit; 252: memory buffer;

254: PMU; 256: error correction unit;

302: system region; 304: the memory block;

304a: data field; 304b: spare area;

306: replace the district; 350-(0)～350-(H): blocks;

410: logical page (LPAGE) changes the physical page mapping table; 420: physical page is changeed the logical page (LPAGE) mapping table;

LBA-(0)～LBA-(L): logical page address; PBA-(0)～PBA-(K): physical page address;

S1001, S1003, S1005, S1007, S1101, S1103, S1105, S1107, S1109, S1111, S1113, S1115, S1117: data write step;

S1501, S1503, S1505, S1507, S1601, S1603, S1605, S1607, S1609, S1611, S1613, S1615, S1617, S1619, S1621, S1623, S1625, S1627, S1629, S1631: data write step.

Embodiment

Generally speaking flash memory device comprises flash chip and controller (also claiming control circuit).Usually flash memory device can use with host computer system, so that host computer system can write to flash memory device or reading of data from flash memory device with data.In addition, flash memory device also being arranged is to comprise embedded flash memory and can be executed on the host computer system with substantially as the software of the controller of this embedded flash memory.

First embodiment

Figure 1A is the structural representation that first embodiment of the invention is used the host computer system of flash memory device.Figure 1B is the synoptic diagram of computer, input/output device and the flash memory device of the embodiment of the invention.Fig. 1 C is the host computer system of another embodiment of the present invention and the synoptic diagram of flash memory device.

Please with reference to Figure 1A, host computer system 1000 comprises that (input/output abbreviates as computer 1100: I/O) device 1106 with I/O.Computer 1100 comprises that (randomaccess memory abbreviates as: RAM) 1104, system bus 1108 and data transmission interface 1110 for microprocessor 1102, RAS.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 shown in Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 also can comprise other devices.

In embodiments of the present invention, flash memory device 100 is to electrically connect through data transmission interface 1110 other elements with host computer system 1000.By microprocessor 1102, RAS 1104 and input/output device 1106, processing host system 1000 can write to flash memory device 100 or reading of data from flash memory device 100 with data.For example, flash memory device 100 can be that (Solid State Drive abbreviates as: SSD) 1216 for carry-on dish 1212, storage card 1214 or solid state hard disc shown in Figure 1B.

Generally speaking, host computer system 1000 is for storing any system of data.Though in the present embodiment, host computer system 1000 is to explain with computer system, yet in another embodiment of the present invention, host computer system 1000 also can be systems such as digital camera, video camera, communicator, message player or video signal player.For example, when host computer system was digital camera 1310, flash memory device then was its employed SD card 1312, mmc card 1314, memory stick (memory stick) 1316 or CF card 1318 or embedded memory storage 1320 (shown in Fig. 1 C).Embedded memory storage 1320 comprises that (Embedded MMC abbreviates as: eMMC) the built-in multimedia card.What deserves to be mentioned is that the built-in multimedia card directly is electrically connected on the substrate of host computer system.

Please with reference to Fig. 1 D, flash memory device 100 comprises connector 102, flash controller 104 and flash chip 106.

Connector 102 is to be electrically connected to flash controller 104 and in order to be electrically connected to host computer system 1000.In the present embodiment, connector 102 is that (Serial Advanced TechnologyAttachment abbreviates as the advanced annex of sequence: SATA) connector.Yet; It must be appreciated and the invention is not restricted to this; Connector 102 also can be parallel advanced annex (Parallel Advanced Technology Attachment; Abbreviate as: PATA) connector, universal serial bus (Universal Serial Bus; Abbreviate as: USB) connector, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers; Abbreviate as: IEEE) (Peripheral ComponentInterconnect Express abbreviates as: PCI Express) (secure digital abbreviates as: SD) interface connector, memory stick (Memory Sick for connector, safe numerical digit for 1394 connectors, high-speed peripheral device connecting interface; Abbreviate as: MS) interface connector, multimedia storage card (Multi Media Card; Abbreviate as: MMC) (CompactFlash abbreviates as: CF) (Integrated DeviceElectronics abbreviates as: IDE) connector or other connectors that is fit to for interface connector, integrated driving electrical interface for interface connector, compact flash.

Flash controller 104 can be carried out with hardware pattern or real a plurality of logic locks or the steering order of doing of firmware pattern, and in flash chip 106, carries out the runnings such as writing, read and erase of data according to the instruction of host computer system 1000.Flash controller 104 comprises microprocessor unit 202, MMU 204, host interface unit 206, flash interface unit 208.

Microprocessor unit 202 is the main control unit of flash controller 104, in order to cooperative cooperatings such as MMU 204, host interface unit 206 and flash interface unit 208 to carry out the various runnings of flash memory device 100.

MMU 204 is to be electrically connected to microprocessor unit 202, and in order to carry out data writing mechanism and the block management mechanism according to present embodiment, the running of MMU 204 will combine accompanying drawing to elaborate below.

In the present embodiment, MMU 204 is to be embodied in the flash controller 104 with a firmware pattern.For example; The MMU 204 that will comprise a plurality of steering orders (for example is burned onto a formula storer; ROM (read-only memory) (Read Only Memory; Abbreviate as: ROM)) in and this formula storer is embedded in the flash controller 104, when flash memory device 100 runnings, a plurality of steering orders of MMU 204 can be carried out to accomplish according to the data writing mechanism of the embodiment of the invention machine-processed with block management by microprocessor unit 202.

In another embodiment of the present invention, the steering order of MMU 204 also can the source code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the flash chip) of flash chip 106.Same, when flash memory device 100 runnings, a plurality of steering orders of MMU 204 can be carried out by microprocessor unit 202.In addition, in another embodiment of the present invention, MMU 204 also can a hardware pattern be embodied in the flash controller 104.

Host interface unit 206 is instruction and the data that are electrically connected to microprocessor unit 202 and transmitted in order to reception and identification host computer system 1000.That is to say that instruction that host computer system 1000 is transmitted and data can be sent to microprocessor unit 202 through host interface unit 206.In the present embodiment, host interface unit 206 is that corresponding connector 102 is the SATA interface.Yet; It must be appreciated to the invention is not restricted to this that host interface unit 206 also can be PATA interface, USB interface, IEEE1394 interface, PCI Express interface, SD interface, MS interface, MMC interface, CF interface, ide interface or other data transmission interfaces that is fit to.

Flash interface unit 208 is to be electrically connected to microprocessor unit 202 and in order to access flash chip 106.That is to say that the data of desiring to write to flash chip 106 can convert 106 receptible forms of flash chip into via flash interface unit 208.

In another embodiment of the present invention, flash controller also can comprise other functional module group.Fig. 2 is the structural representation of the flash controller of another embodiment of the present invention.

Please with reference to Fig. 2; Except microprocessor unit 202, MMU 204, host interface unit 206 and flash interface unit 208, the flash controller 104 of another embodiment of the present invention ' also comprise memory buffer 252, PMU 254 and error correction unit 256.

Memory buffer 252 is to be electrically connected to microprocessor unit 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from flash chip 106.

PMU 254 be electrically connected to microprocessor unit 202 and in order to control flash memory device 100 power supply.

Error correction unit 256 is to be electrically connected to microprocessor unit 202 and in order to carry out an error-correcting routine to guarantee the correctness of data.Specifically; When receiving main frame from host computer system 1000, MMU 204 writes when instruction; Error correction unit 256 can write the bug check and correcting code (the Error Checking and CorrectingCode that data produce correspondence of instruction for corresponding this main frame; Abbreviate as: ECC Code), and MMU 204 can write data with this and writes in the flash chip 106 with corresponding error-correcting code.Afterwards, when MMU 204 can read the corresponding error-correcting code of these data during reading of data simultaneously from flash chip 106, and error correction unit 256 can be according to the data execution error correction program of this error-correcting code to being read.

Please refer again to Fig. 1 D, flash chip 106 be electrically connected to flash controller 104 and in order to the storage data.Flash chip 106 has physical blocks 122-(0)～122-(N).Physical blocks is the least unit of erasing.That is each physical blocks contains the memory cell of being erased in the lump of minimal amount.Each physical blocks has several physical page.In the present embodiment, physical page is the minimum unit that stylizes.In other words, physical page is the minimum unit that writes data or reading of data.Each physical page generally includes user data field and redundant area.The user data field is in order to storage user's data, and redundant area is in order to the data (for example, bug check and correcting code) of storage system.In the present embodiment, flash chip 106 is that (Multi Level Cell abbreviates as the multilayer memory cell: MLC) nand flash memory chip.Yet, the invention is not restricted to this, flash chip 106 also the individual layer memory cell (Single Level Cell abbreviates as: SLC) nand flash memory chip.

Fig. 3 A is the structural representation of the flash chip of first embodiment of the invention.Fig. 3 B is the logical page address of first embodiment of the invention and the mapping synoptic diagram of physical page address.It must be appreciated that when this described the running of physical blocks of flash memory, coming the application entity block with speech such as " extraction ", " exchange ", " grouping ", " rotating " was notion in logic.That is to say that the physical location of the physical blocks of flash memory does not change, but in logic the physical blocks of flash memory is operated.

Please with reference to Fig. 3 A, MMU 204 can logically be grouped into physical blocks 122-(0)～122-(N) system region (system area) 302, memory block (storage area) 304 and replace district (replacementarea) 306.

Physical blocks 122-(the 0)～122-(S) that belongs to system region 302 in logic is in order to the register system data, and this system data comprises about the number of the number of regions of the manufacturer of flash chip and model, each flash chip, physical blocks that each is regional, physical page number of each physical blocks etc.

Physical blocks 122-(the S+1)～122-(A) that belongs to memory block 304 in logic is the data that write in order to host computer system 1000.That is to say the data that flash memory device 100 can use the physical blocks that is grouped into memory block 304 to come host system 1000 practically to be write.More detailed; The physical blocks 122-of memory block 304 (S+1)～122-(A) also is grouped into data field 304a and spare area 304b; Wherein the physical blocks 122-of data field 304a (S+1)～122-(D) is the physical blocks that has been used for storing data, and the physical blocks 122-of spare area 304b (D+1)～122-(A) is the physical blocks that is not used for storing data.Specifically; When MMU 204 when 304b extracts physical blocks and writes data from the spare area; The physical blocks of being extracted can be associated as data field 304a, and can be associated as spare area 304b when the physical blocks that is associated as data field 304a is performed the physical blocks of having erased after the running of erasing.

Belonging to physical blocks 122-(the A+1)～122-(N) that replaces in the district 306 in logic is to substitute physical blocks.For example, flash chip 106 can be reserved 4% physical blocks and uses as changing when dispatching from the factory.That is to say that when system region 302 was damaged with the physical blocks in the memory block 304, being reserved in the physical blocks that replaces in the district 306 can be in order to replacing damaged physical blocks (that is bad physical blocks (bad block)).Therefore, if replace when still having available physical blocks in the district 306 and the physical blocks damage taking place, MMU 204 can extract the physical blocks that available physical blocks is changed damage from replace district 306.If when no available physical blocks and generation physical blocks were damaged in the replacement district 306, then flash memory device 100 will be declared to be write protection (write protect), and can't write data again.

Because flash memory device 100 is the data of coming the storage of host system 1000 desires with the physical blocks of using memory block 304 with rotating; Therefore MMU 204 can provide logical page address to host computer system 1000 to carry out data access; And MMU 204 can be grouped into blocks 350-(0)～350-(H) with these logical page addresses, and wherein blocks 350-(0)～50-(H) can shine upon the physical blocks (shown in Fig. 3 B) of memory block 304.For example, MMU 204 meeting service logic pages or leaves change the physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table writes down the mapping relations between logical page address and the physical page address.

Specifically, in embodiments of the present invention, when host computer system 1000 write data in the logical page address of blocks 350-(0)～350-(H), MMU 204 write to data in the physical page address of physical blocks of memory block 304.Specifically; When MMU 204 brings into use physical blocks 122-(D+1) to come data that host system 1000 desires to write; No matter host computer system 1000 is to write that logical page address, MMU can write to data the physical page address of physical blocks 122-(D+1) in order; And when MMU 204 brings into use physical blocks 122-(D+2) to come data that host system 1000 desires to write; No matter host computer system 1000 is to write that logical page address, MMU can write to data in the physical page address of physical blocks 122-(D+2) in order.That is to say; When writing the data that host computer system 1000 desires to write; MMU 204 can use the physical page address in the physical blocks to write data in order; And after the physical page address in this physical blocks is used up, just can select another physical blocks of not having the storage data (that is, from spare area 304b, extracting a physical blocks) again, and in the physical page address of the new physical blocks of selecting, continue to write in order data.In the present embodiment; After MMU 204 write to the physical page address with data, MMU 204 can upgrade logical page (LPAGE) commentaries on classics physical page mapping table and physical page is changeed the logical page (LPAGE) mapping table correctly to write down the mapping relations of logical page address and physical page address.

It must be appreciated that in the running of flash memory device 100, the mapping relations that physical blocks 122-(0)～122-(N) is grouped into system region 302, data field 304a, spare area 304b and replacement district 306 can dynamically change.That is to say, when MMU 204 data are write to originally belong to the physical blocks (for example, physical blocks 122-(D+2)) of spare area 304b after, this physical blocks can be associated as data field 304a.Perhaps, when the physical blocks among the data field 304a (or spare area 304b) is damaged and when being substituted district's physical blocks of 306 and replacing, the physical blocks that then replaces district 306 originally can be associated as data field 304a (or spare area 304b).

What deserves to be mentioned is, in an embodiment of the present invention, comprise also that in MMU 204 one can write physical page pointer (Available Physical Page Pointer), can write the physical page address in order to indicate at present.Based on this; When flash controller 104 was carried out the main frame that comes from host computer system 1000 and write instruction and write data, MMU 204 can write to data in the physical page address of flash chip 106 according to the mark that can write the physical page pointer in order.At this, can write physical blocks under the physical page address at present and be also referred to as at present and can write physical blocks.

Fig. 4 A and Fig. 4 B are the synoptic diagram that a logical page (LPAGE) of first embodiment of the invention changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table; Wherein blocks 350-(0)～350-(H) comprises logical page address LBA-(0)～LBA (L), and the physical blocks of memory block 304 comprises physical page address PBA-(0)～PBA (K).In the present embodiment; Logical page (LPAGE) commentaries on classics physical page mapping table has logical page (LPAGE) index field and physical page address field writes down the physical page address that each logical page address shines upon, and physical page is changeed, and the logical page (LPAGE) mapping table has physical page index field and the logical page address field writes down the logical page address that each physical page address is shone upon.

Please with reference to Fig. 4 A and 4B; Logic of propositions page address LBA-(0)～logical page address LBA-(L) shines upon physical page address PBA-(0)～physical page address PBA-(L) respectively; That is to say that physical page address PBA-(0)～physical page address PBA-(L) has distinguished the data that host system 1000 is write in logical page address LBA-(0)～logical page address LBA-(L).Therefore, logical page (LPAGE) change physical page mapping table 410 and physical page change logical page (LPAGE) mapping table 420 can these mapping relations of record, and can write the physical page pointer this moment and can point to physical page address PBA-(L+1).

Please with reference to Fig. 5 A and 5B; If when host computer system 1000 under the mapping relations of Fig. 4 A and Fig. 4 B desires to write data to logical page address LBA-(1); MMU 204 can write among the physical page address PBA-(L+1) according to writing the data that the physical page pointer desires host computer system 1000 to write, and can write the physical page pointer and change into and point to physical page address PBA-(L+2).At this moment; MMU 204 can be physical page address PBA-(L+1) at the map updating that logical page (LPAGE) changes in the physical page mapping table 410 logical page address LBA-(1), and the map updating that changes in the logical page (LPAGE) mapping table 420 physical page address PBA-(L+1) in physical page is logical page address LBA-(1).

Please with reference to Fig. 6 A and 6B; If when host computer system 1000 under the mapping relations of Fig. 5 A and Fig. 5 B desires to write data to logical page address LBA-(129); MMU 204 can write among the physical page address PBA-(L+2) according to writing the data that the physical page pointer desires host computer system 1000 to write, and can write the physical page pointer and change into and point to physical page address PBA-(L+3).At this moment; MMU 204 can be physical page address PBA-(L+2) at the map updating that logical page (LPAGE) changes in the physical page mapping table 410 logical page address LBA-(129), and the map updating that changes in the logical page (LPAGE) mapping table 420 physical page address PBA-(L+2) in physical page is logical page address LBA-(129) (shown in Fig. 6 B).

In addition; In embodiments of the present invention; The record that MMU 204 meeting comparison logical page (LPAGE)s change in physical page mapping table 410 and the physical page commentaries on classics logical page (LPAGE) mapping table 420 judges that which physical page address is invalid physical page address and effective physical page address; The data that wherein so-called invalid physical page address is meant wherein and is stored are invalid legacy data, and effectively the physical page address data that are meant wherein to be stored are valid data of mapping current logic page address.

For example; With Fig. 6 A and 6B is example; When desire judges whether physical page address PBA-(0) is effective physical page address; MMU 204 can change that to read physical page address PBA-(0) the logical page (LPAGE) mapping table 420 be mapping logic page address LBA-(0) from physical page, and changeing physical page mapping table 410 according to logical page address LBA-(0) from logical page (LPAGE), to read logical page address LBA-(0) be mapping physical page address PBA-(0), so physical page address PBA-(0) is effective physical page address.In addition; When desire judges whether physical page address PBA-(1) is effective physical page address; MMU 204 can be read physical page address PBA-(1) from physical page commentaries on classics logical page (LPAGE) mapping table 420 be mapping logic page address LBA-(1); And reading logical page address LBA-(1) according to logical page address LBA-(1) from logical page (LPAGE) commentaries on classics physical page mapping table 410 is mapping physical page address PBA-(L+1), so physical page address PBA-(1) is invalid physical page address.That is to say; MMU 204 can change the physical page address that logical page address shone upon of physical page mapping table 410 inquiries physical page map addresses to be judged according to physical page address to be judged through physical page commentaries on classics logical page (LPAGE) mapping table 420 and logical page (LPAGE); If physical page address to be judged is during with the physical page address matches of being inquired about; Then this physical page address to be judged is effective physical page address, otherwise then is invalid physical page address.

Since flash chip 106 be with physical blocks as the least unit of erasing, so MMU 204 can merge the data in the effective physical page address to discharge invalid physical page address through above-mentioned comparison and writes new data.For example; MMU 204 can copy to the data in effective physical page address at least one physical blocks in the physical page address of the physical blocks that does not write any data; And, can the valid data that disperse be merged and invalid physical page address discharged (below be called invalid data erase program) thus the running of erasing of this physical blocks.

For example; Carrying out the valid data merging with after discharging invalid physical page address; MMU 204 can upgrade physical page changes logical page (LPAGE) mapping tables 420, is updated to null value (for example, " NULL ") with the mapping relations with the physical page address of the physical blocks of being erased.

Particularly; As stated; Flash memory device 100 is to rotate to use physical blocks to store data; Therefore, in order to make flash memory device 100 normal operations, MMU 204 can each confirm before from spare area 304b, extracting physical blocks among the spare area 304b number whether less than a standby entity block counts threshold value.If among the spare area 304b number during less than standby entity block counts threshold value; MMU 204 can be carried out the above-mentioned invalid data program of erasing and erase with the physical blocks that will store invalid data; And the physical blocks of being erased is associated as spare area 304b, to discharge the physical blocks of storage invalid data.For example, in the present embodiment, standby entity block counts threshold setting is 5.Yet, it must be appreciated that the invention is not restricted to this, standby entity block counts threshold value can be set to other suitable numerical value.

What deserves to be mentioned is, shown in the mapping relations that above-mentioned foundation is shown in Figure 3 and Fig. 4 A, Fig. 4 B, Fig. 5 A, Fig. 5 B, Fig. 6 A and Fig. 6 B write running also can be described as with the page be the basis (page-based) the flash memory management pattern.

In the present embodiment; When MMU 204 uses with the page is the flash memory management pattern on basis (page-based) when writing data, and MMU 204 can guarantee that the data of each blocks degree at random is not more than blocks data degree threshold value at random.Specifically, because host computer system 1000 writes data in logical page address LBA-(0)～LBA (L), host computer system 1000 may not necessarily write data according to the order of logical page address LBA-(0)～LBA (L).Therefore; When flash memory device 100 through after a while write running after; The data that belong to same blocks may be stored in a plurality of physical blocks dispersedly, and wherein the data of blocks degree at random just is meant the number of the physical blocks of the data that are used to store this blocks.In the present invention, blocks data degree threshold value at random can be any positive integer greater than zero, and for example, blocks data degree threshold value at random can be 2,4,8 or 16.

In the present embodiment, when host interface unit 206 from this host computer system 1000, receive main frame write instruction and desire to write write data the time, MMU 204 can confirm that main frames write the blocks under the logical page address indicated in the instruction.At this, the present main frame that receives writes logical address indicated in the instruction and is called " being written into logical address ", and the blocks that the present main frame that receives writes under the logical address indicated in the instruction is called " being written into blocks ".For example; MMU 204 can calculate main frame according to a mathematical operation formula and write the blocks under the logical page address in the instruction, perhaps inquires about main frame according to logical address-blocks mapping table and writes the blocks under the logical page address in the instruction.And MMU 204 can be according to being written into the data degree at random of blocks, can writing physical page address and blocks data degree threshold value at random at present and decide and be used for the physical page address that this writes data.

Fig. 7 A, Fig. 7 B and Fig. 7 C are that data of first embodiment of the invention write synoptic diagram, suppose that wherein each physical blocks has 4 physical page addresses and blocks data degree threshold value at random is 2.

Please with reference to Fig. 7 A, wherein 2 physical page addresses of supposing physical blocks 122-(S+1) store the data that belong to blocks 350-(0) and in addition 2 physical page addresses store the data that belong to blocks 350-(3); The physical page address of physical blocks 122-(S+2) all stores the data that belong to blocks 350-(1); Preceding 2 physical page addresses of physical blocks 122-(D) store the data that belong to blocks 350-(2); And can write pointed can the writing at present of physical page pointer the 3rd the physical page address that the physical page address is physical blocks 122-(D) at present.

Please with reference to Fig. 7 B; When receiving main frame from host computer system 1000, host interface unit 206 writes instruction; And MMU 204 judges that it is when belonging to blocks 350-(3) that host computer systems 1000 desire to write the logical page address of data, the data degree at random that MMU 204 can decision logic block 350-(3) be 1 and can write at present the physical page pointer pointed can write the data that physical blocks 122-(D) under the physical page address does not store blocks 350-(3) at present.In the present embodiment; Because the data degree at random of blocks 350-(3) is 1; It is less than blocks data degree threshold value at random, therefore, and when belonging to the writing data and be written into physical blocks 122-(D) of blocks 350-(3); The data degree at random of blocks 350-(3) only can increase by 1 and become 2, and it does not surpass blocks data degree threshold value at random.Based on this, MMU 204 can will write the 3rd the physical page address that data write to physical blocks 122-(D).

Please with reference to Fig. 7 C; At the state shown in Fig. 7 B and can write at present in pointed can the writing at present of the physical page pointer example of the 4th physical page address that the physical page address is physical blocks 122-(D); When receiving main frame from host computer system 1000, host interface unit 206 writes instruction; And MMU 204 judges that it also is when belonging to blocks 350-(3) that host computer systems 1000 desire to write the logical page address of data; The data degree at random of MMU 204 meeting decision logic block 350-(3) is 2; It equals blocks data degree threshold value at random, and can write at present the physical page pointer pointed can write the data that physical blocks under the physical page address stores blocks 350-(3) at present.In the present embodiment; Since can write at present the physical page pointer pointed can write the data that physical blocks 122-(D) under the physical page address stores blocks 350-(3) at present; Therefore; When belonging to the writing data and be written into physical blocks 122-(D) of blocks 350-(3), the data degree at random of blocks 350-(3) still can be maintained 2, and it surpasses blocks data degree threshold value at random.Based on this, MMU 204 can will write the 4th the physical page address that data write to physical blocks 122-(D).

Fig. 8 A and Fig. 8 B are that another data of first embodiment of the invention write synoptic diagram, suppose that wherein each physical blocks has 4 physical page addresses and blocks data degree threshold value at random is 2.

Please with reference to Fig. 8 A, wherein 2 physical page addresses of supposing physical blocks 122-(S+1) store the data that belong to blocks 350-(0) and in addition 2 physical page addresses store the data that belong to blocks 350-(3); Wherein 3 physical page addresses of physical blocks 122-(S+2) store data and other 1 physical page address of belonging to blocks 350-(1) and store the data that belong to blocks 350-(3); Preceding 2 physical page addresses of physical blocks 122-(D) store the data that belong to blocks 350-(2); And can write pointed can the writing at present of physical page pointer the 3rd the physical page address that the physical page address is physical blocks 122-(D) at present.

Please with reference to Fig. 8 B; When receiving main frame from host computer system 1000, host interface unit 206 writes instruction; And MMU 204 judges that it is when belonging to blocks 350-(3) that host computer systems 1000 desire to write the logical page address of data, the data degree at random that MMU 204 can decision logic block 350-(3) be 2 and can write at present the physical page pointer pointed can write the data that physical blocks 122-(D) under the physical page address does not store blocks 350-(3) at present.In the present embodiment, MMU 204 also can judge physical blocks 122-(D) but the residue storage space whether enough storage write other data of data and blocks 350-(3).Specifically; Because the data degree at random of blocks 350-(3) can not be greater than 2; Therefore; When MMU 204 desire in physical blocks 122-(D), to write belong to blocks 350-(3) write data the time, MMU 204 must be moved and be stored in the data that belong to blocks 350-(3) in other physical blocks and be less than or equal to 2 so that the data degree at random of blocks 350-(3) is still kept.Based on this; Enough store at the residual memory space of physical blocks 122-(D) and to write data and (promptly in the physical blocks of the data that are used for stored logic block 350-(3); Physical blocks 122-(S+1) and physical blocks 122-(S+2)) among one of them physical blocks (for example; Physical blocks 122-(S+2)) belong under all data conditions of blocks 350-(3), MMU 204 can will write data and write among the physical blocks 122-(D) with all data that are stored in the blocks 350-(3) among the physical blocks 122-(S+2).That is to say; The data that belong to blocks 350-(3) that have 1 physical page address size owing to have the data that belong to blocks 350-(3) of 2 physical page address sizes among the physical blocks 122-(S+1) among the physical blocks 122-(S+2); Therefore; Can hold under the data conditions of being moved in only surplus 1 the physical page address of physical blocks 122-(D); MMU 204 can select data-moving with the 4th the physical page address of physical blocks 122-(S+2) to physical blocks 122-(D), and the 4th the physical page address label of physical blocks 122-(S+2) is shown invalid, and the data degree at random of blocks 350-(3) still is 2 thus.

Fig. 9 A and Fig. 9 B are that the another data of first embodiment of the invention write synoptic diagram, suppose that wherein each physical blocks has 4 physical page addresses and blocks data degree threshold value at random is 2.

Please with reference to Fig. 9 A, wherein 2 physical page addresses of supposing physical blocks 122-(S+1) store the data that belong to blocks 350-(0) and in addition 2 physical page addresses store the data that belong to blocks 350-(3); Wherein 3 physical page addresses of physical blocks 122-(S+2) are stored data and other 1 physical page address of belonging to blocks 350-(1) and are stored the data that belong to blocks 350-(3); Preceding 3 physical page addresses of physical blocks 122-(D) store the data that belong to blocks 350-(2); And can write pointed can the writing at present of physical page pointer the 4th the physical page address that the physical page address is physical blocks 122-(D) at present.

Please with reference to Fig. 9 B; When receiving main frame from host computer system 1000, host interface unit 206 writes instruction; And MMU 204 judges that it is when belonging to blocks 350-(3) that host computer systems 1000 desire to write the logical page address of data, the data degree at random that MMU 204 can decision logic block 350-(3) be 2 and can write at present the physical page pointer pointed can write the data that physical blocks 122-(D) under the physical page address does not store blocks 350-(3) at present.Similar above-mentioned; MMU 204 also can judge physical blocks 122-(D) but the residue storage space whether enough storage write data and be written into all data that belong to blocks 350-(3) in other physical blocks (for example, physical blocks 122-(S+1) or physical blocks 122-(S+2)).In the present embodiment; Since physical blocks 122-(D) but the residue memory space inadequate enough store and write data and (promptly in the physical blocks of the data that are used for stored logic block 350-(3); Physical blocks 122-(S+1) and physical blocks 122-(S+2)) among any physical blocks in belong to all data of blocks 350-(3); So MMU 204 can (for example extract a physical blocks from spare area 304b; And will write data and be stored in all data that one of them physical blocks among the physical blocks of the data that are used for stored logic block 350-(3) belongs to blocks 350-(3) and write among the physical blocks 122-(D+1) physical blocks 122-(D+1)).In the present embodiment, the less physical blocks of data that the first selection of MMU 204 meetings need be moved is moved, and avoids writing the required time of instruction because of moving data significantly increases the execution main frame.That is to say; In the present embodiment; MMU 204 can select data-moving with the 4th the physical page address of physical blocks 122-(S+2) to physical blocks 122-(D+1); And it is invalid that the 4th the physical page address label of physical blocks 122-(S+2) is shown, and the data degree at random of blocks 350-(3) still is 2 thus.

Please with reference to Figure 10, the host interface unit 206 of flash controller 104 receives main frame via connector 102 and writes instruction and write data from host computer system 1000 in step S1001.

MMU 204 is written into blocks according to the logical page address judgement that is written into that main frame writes instruction in step S1003, and can write the physical page address at present in 204 judgements of step S1005 MMU.For example, MMU 204 is to judge at present and can write the physical page address according to writing the physical page pointer in step S1005.

Then, MMU 204 can be according to being written into the data degree at random of blocks and can writing the physical page address at present with writing in the physical page address that data write to flash chip 106 in step S1007.

Please with reference to Figure 11, MMU 204 can judge whether the data degree at random that is written into blocks equals blocks data degree threshold value at random in step S1101.What deserves to be mentioned is; MMU 204 can make the data of each blocks degree at random be no more than blocks data degree threshold value at random; Therefore; The data degree at random that blocks in the judgement of step S1101, only can occur being written into equals blocks data degree threshold value at random or is written into the situation of the data degree at random of blocks less than blocks data degree threshold value at random, and the situation of the data degree at random of blocks greater than blocks data degree threshold value at random can not occur being written into.

If judge that in step S1101 the data degree at random that is written into blocks is not equal to blocks data degree threshold value at random (promptly; The data degree at random that is written into blocks is less than blocks data degree at random) time, then MMU 204 can will write data and writes at present and can write in the physical page address in step S1103.Afterwards, MMU 204 can upgrade the mapping relations between logical page address and the physical page address in step S1105, and flow process shown in Figure 11 can be finished.For example, MMU 204 meeting renewal logical page (LPAGE)s commentaries on classics physical page mapping tables 410 and physical page are changeed the new mapping relations that logical page (LPAGE) mapping table 420 writes down between logical page address and the physical page address in step S1105.

If in step S1101, judge when the data degree at random be written into blocks equals blocks data degree threshold value at random; Then whether MMU 204 can be judged can writing at present to store in the physical blocks (that is, can write at present under the physical page address physical blocks) and belong to the data that are written into blocks in step S1107.If can write to store in the physical blocks at present belongs to the data that are written into blocks, execution in step S1103 then.

If in step S1107, judging can write not store in the physical blocks at present belongs to the data that are written into blocks, then MMU 204 can be judged can writing one of them physical blocks that whether has enough storage spaces to store in the physical blocks to write data and be used for storing among the physical blocks of the data that are written into blocks at present and belongs to all data that are written into blocks in step S1109.

If in step S1109, judging can writing at present has enough storage spaces to store to write data and is being used for storing one of them physical blocks among the physical blocks of the data that are written into blocks when belonging to all data that are written into blocks in the physical blocks, then in step S1111 MMU 204 can will write data write to can write at present in the physical page address and will one of them physical blocks among the physical blocks that is used for storing the data that are written into blocks belong to be written into blocks all data-movings to writing in the physical blocks at present.Afterwards, step S1105 can be performed.

If in step S1109, judge can writing no enough storage spaces in the physical blocks at present and store and write data and be used for storing one of them physical blocks among the physical blocks of the data that are written into blocks when belonging to all data that are written into blocks, then in step S1113 MMU 204 understand judge the physical blocks among the spare area 304b number whether less than standby entity block counts threshold value.If the number of the physical blocks among the spare area 304b is less than standby entity block counts threshold value, then MMU 204 can be carried out the physical blocks that the invalid data program of erasing is stored invalid data with release in step S1115, and execution in step S1113.

If judge that in step S1113 the number of the physical blocks among the spare area 304b is non-less than standby entity block counts threshold value, then MMU 204 can extract a physical blocks and will write data and be used for storing one of them physical blocks among the physical blocks of the data that are written into blocks and belongs to all data that are written into blocks and write in the physical blocks of being extracted from spare area 304b in step S1117.

Second embodiment

The flash memory device of second embodiment of the invention is identical with flash memory device and the host computer system of first embodiment with host computer system in essence; Wherein the difference MMU that is first embodiment writes to flash chip according to the data degree at random of each blocks with data, and MMU writes to flash chip according to the data degree at random of each blocks and the data degree at random of each physical blocks with data in a second embodiment.Below will combine Figure 1A, Fig. 1 D, Fig. 3 A and Fig. 3 B of first embodiment to describe second embodiment.In a second embodiment, MMU 204 also is that to be similar to the mode shown in Fig. 4 A, Fig. 4 B, Fig. 5 A, Fig. 5 B, Fig. 6 A and Fig. 6 B be that flash chip 106 is managed on the basis with the page.

In the present embodiment; When MMU 204 uses with the page is the flash memory management pattern on basis when writing data, and MMU 204 can guarantee that the data degree at random that the data of each blocks degree at random is not more than blocks data degree threshold value at random and each physical blocks is not more than physical blocks data degree threshold value at random.At this, the data of physical blocks degree at random just is meant the number of the blocks under the data that this physical blocks stores.As stated; Because host computer system 1000 may not necessarily write data according to the order of logical page address; Therefore when flash memory device 100 through after a while write running after, in same physical blocks, might store the data that belong to a plurality of blocks.In the present invention, physical blocks data degree threshold value at random can be any positive integer greater than zero, and for example, physical blocks data degree threshold value at random can be 2,4,8 or 16.

Figure 12 A and Figure 12 B are that data of second embodiment of the invention write synoptic diagram, suppose that wherein it all is 2 that each physical blocks has 4 physical page addresses and blocks data degree threshold value at random and physical blocks data degree threshold value at random.

Please with reference to Figure 12 A, wherein 3 physical page addresses of supposing physical blocks 122-(S+1) store the data that belong to blocks 350-(0) and in addition 1 physical page address store the data that belong to blocks 350-(3); Wherein 3 physical page addresses of physical blocks 122-(S+2) store data and other 1 physical page address of belonging to blocks 350-(1) and store the data that belong to blocks 350-(2); Wherein 1 physical page address of physical blocks 122-(D) stores data and other 1 physical page address of belonging to blocks 350-(2) and stores the data that belong to blocks 350-(3); And can write pointed can the writing at present of physical page pointer the 3rd the physical page address that the physical page address is physical blocks 122-(D) at present.

Please with reference to Figure 12 B; When receiving main frame from host computer system 1000, host interface unit 206 writes instruction; And MMU 204 judges that it is when belonging to blocks 350-(3) that host computer systems 1000 desire to write the logical page address of data; The data degree at random of MMU 204 meeting decision logic block 350-(3) is 2; Can write the physical page pointer data degree at random that can write the physical blocks 122-(D) under the physical page address at present pointed at present is 2, and can write at present the physical page pointer pointed can write the data that physical blocks 122-(D) under the physical page address stores blocks 350-(3) at present.In the present embodiment; Owing to can write the data that the affiliated physical blocks 122-(D) in physical page address stores blocks 350-(3) at present; Therefore when writing data and be written into physical blocks 122-(D), the data degree at random of physical blocks 122-(D) still can be maintained 2 and the data degree at random of blocks 350-(3) also can be maintained 2.That is to say that the neither data degree at random greater than blocks data degree threshold value at random and each physical blocks of the data of each blocks degree at random is not more than physical blocks data degree threshold value at random.Based on this, in the present embodiment, MMU 204 can will write data and write to and can write pointed can the writing in the physical page address at present of physical page pointer at present.

Figure 13 A and Figure 13 B are that another data of second embodiment of the invention write synoptic diagram, suppose that wherein it all is 2 that each physical blocks has 4 physical page addresses and blocks data degree threshold value at random and physical blocks data degree threshold value at random.

Please with reference to Figure 13 A, wherein 2 physical page addresses of supposing physical blocks 122-(S+1) store the data that belong to blocks 350-(0) and in addition 2 physical page addresses store the data that belong to blocks 350-(3); The data that belong to blocks 350-(1) are all stored in the physical page address of physical blocks 122-(S+2); Wherein 1 physical page address of physical blocks 122-(D) stores data and other 1 physical page address of belonging to blocks 350-(2) and stores the data that belong to blocks 350-(4); And can write pointed can the writing at present of physical page pointer the 3rd the physical page address that the physical page address is physical blocks 122-(D) at present.

Please with reference to Figure 13 B; When receiving main frame from host computer system 1000, host interface unit 206 writes instruction; And MMU 204 judges that it is when belonging to blocks 350-(3) that host computer systems 1000 desire to write the logical page address of data; The data degree at random of MMU 204 meeting decision logic block 350-(3) is 1; Can write the physical page pointer data degree at random that can write the physical blocks 122-(D) under the physical page address at present pointed at present is 2, and can write at present the physical page pointer pointed can write the data that physical blocks 122-(D) under the physical page address does not store blocks 350-(3) at present.In the present embodiment; If only consider under the data degree at random of blocks 350-(3); The data that write that belong to blocks 350-(3) are to be written into physical blocks 122-(D); But because the data degree at random that can write physical blocks 122-(D) at present is 2, therefore will belong to writing the data degree at random that data write to physical blocks 122-(D) back physical blocks 122-(D) and can becoming 3 of blocks 350-(3), it can surpass physical blocks data degree threshold value at random.Therefore, in the present embodiment, MMU 204 extracts a physical blocks (for example, physical blocks 122-(D+1)) from spare area 304b, and will write data and write among the physical blocks 122-(D+1).Thus; It is 2 that MMU 204 can make the data degree at random of physical blocks 122-(D); The data degree at random of blocks 350-(3) is 2; And the data degree at random of physical blocks 122-(D+1) is 1, so that the neither data degree at random greater than blocks data degree threshold value at random and each physical blocks of the data of each blocks degree at random is not more than physical blocks data degree threshold value at random.

Figure 14 A and Figure 14 B are that the another data of second embodiment of the invention write synoptic diagram, suppose that wherein each physical blocks has 4 physical page addresses, and blocks data degree threshold value at random and physical blocks data degree threshold value at random all are 2.

Please with reference to Figure 14 A, wherein 2 physical page addresses of supposing physical blocks 122-(S+1) store the data that belong to blocks 350-(0) and in addition 2 physical page addresses store the data that belong to blocks 350-(3); Wherein 3 physical page addresses of physical blocks 122-(S+2) store data and other 1 physical page address of belonging to blocks 350-(1) and store the data that belong to blocks 350-(3); Wherein 1 physical page address of physical blocks 122-(D) stores data and other 1 physical page address of belonging to blocks 350-(2) and stores the data that belong to blocks 350-(4), and can write pointed can the writing at present of physical page pointer the 3rd the physical page address that the physical page address is physical blocks 122-(D) at present.

Please with reference to Figure 14 B; When receiving main frame from host computer system 1000, host interface unit 206 writes instruction; And MMU 204 judges that it is when belonging to blocks 350-(3) that host computer systems 1000 desire to write the logical page address of data; The data degree at random of MMU 204 meeting decision logic block 350-(3) is 2; Can write the physical page pointer data degree at random that can write the physical blocks 122-(D) under the physical page address at present pointed at present is 2, and can write at present the physical page pointer pointed can write the data that physical blocks 122-(D) under the physical page address does not store blocks 350-(3) at present.Be similar to shown in Figure 13 A and the 13B; Because can write the data degree at random of physical blocks 122-(D) at present is 2; Therefore will belong to writing of blocks 350-(3) and can make the data degree at random of physical blocks 122-(D) become 3 after data write to physical blocks 122-(D), it can surpass physical blocks data degree threshold value at random.Therefore; In the present embodiment; MMU 204 (for example extracts a physical blocks from spare area 304b; Physical blocks 122-(D+1)), and will write data and write among the physical blocks 122-(D+1), so that the data of each physical blocks degree at random is neither greater than physical blocks data degree threshold value at random.In addition; After will writing data and writing to physical blocks 122-(D+1); The data degree at random of blocks 350-(3) can become 3; Therefore MMU 204 can be in the physical blocks of the data that are used for stored logic block 350-(3) (promptly; Physical blocks 122-(S+1) and physical blocks 122-(S+2)) among any physical blocks in belong to blocks 350-(3) all data-movings to physical blocks 122-(D+1) be less than or equal to 2 so that the data degree at random of blocks 350-(3) is still kept.In the present embodiment, the less physical blocks of data that the preferential selection of MMU 204 meetings need be moved is moved, and avoids writing the required time of instruction because of moving data significantly increases the execution main frame.That is to say; MMU 204 can select data-moving with the 4th the physical page address of physical blocks 122-(S+2) to physical blocks 122-(D+1); And it is invalid that the 4th the physical page address label of physical blocks 122-(S+2) is shown, and the data degree at random of blocks 350-(3) still is 2 thus.

Please with reference to Figure 15, the host interface unit 206 of flash controller 104 receives main frame via connector 102 and writes instruction and write data from host computer system 1000 in step S1501.

MMU 204 is written into blocks according to the logical page address judgement that is written into that main frame writes instruction in step S1503, and can write the physical page address at present in 204 judgements of step S1505 MMU.Then, MMU 204 can will write in the physical page address that data write to flash chip 106 according to the data degree at random that is written into the data degree at random of blocks, can write the physical page address and can write the physical blocks under the physical page address at present at present in step S1507.

Figure 16 A and 16B are the process flow diagrams of the detailed step of step S1507 among Figure 15, and wherein the part steps of Figure 16 A is shown in (that is the step between node A and the Node B) among Figure 16 B.

Please with reference to Figure 16 A, MMU 204 can judge whether the data degree at random that can write physical blocks (that is, can write the affiliated physical blocks in physical page address at present) at present equals physical blocks data degree threshold value at random in step S1601.What deserves to be mentioned is; Be similar to the judgement of the data degree at random of blocks; MMU 204 can make the data of each physical blocks degree at random be no more than physical blocks data degree threshold value at random; Therefore; The data degree at random that physical blocks in the judgement of step S1601, only can occur equals the situation of the data degree at random of physical blocks data degree threshold value at random or physical blocks less than physical blocks data degree at random, and the situation of the data degree at random of physical blocks greater than physical blocks data degree at random can not occur.

If judge that in step S1601 the data degree at random that can write physical blocks at present is not equal to physical blocks data degree threshold value at random (promptly; The data degree at random that can write physical blocks at present is less than physical blocks data degree threshold value at random) time, the step S1603 among the execution graph 16B then.

Please with reference to Figure 16 B, MMU 204 can judge whether the data degree at random that is written into blocks equals blocks data degree threshold value at random in step S1603.

If judge that in step S1603 the data degree at random that is written into blocks is not equal to blocks data degree threshold value at random (promptly; The data degree at random that is written into blocks is less than blocks data degree at random) time, then MMU 204 can will write data and writes at present and can write in the physical page address in step S1605.Afterwards, the step S1607 among Figure 16 A can be performed (that is, the step after the Node B), and wherein MMU 204 can upgrade the mapping relations between logical page address and the physical page address in step S1607, and flow process shown in Figure 16 can be finished.For example, MMU 204 meeting renewal logical page (LPAGE)s commentaries on classics physical page mapping tables 410 and physical page are changeed the new mapping relations that logical page (LPAGE) mapping table 420 writes down between logical page address and the physical page address in step S1607.

If in step S1603, judge when the data degree at random be written into blocks equals blocks data degree threshold value at random, then whether MMU 204 can be judged can write to store in the physical blocks at present and belong to the data that are written into blocks in step S1609.If can write to store in the physical blocks at present belongs to the data that are written into blocks, execution in step S1605 then.

If in step S1609, judging can write not store in the physical blocks at present belongs to the data that are written into blocks, then MMU 204 can be judged can writing one of them physical blocks that whether has enough storage spaces to store in the physical blocks to write data and be used for storing among the physical blocks of the data that are written into blocks at present and belongs to all data that are written into blocks in step S1611.

If in step S1611, judging can writing at present has enough storage spaces to store to write data and is being used for storing one of them physical blocks among the physical blocks of the data that are written into blocks when belonging to all data that are written into blocks in the physical blocks, then in step S1613 MMU 204 can will write data write to can write at present in the physical page address and will one of them physical blocks among the physical blocks that is used for storing the data that are written into blocks belong to be written into blocks all data-movings to writing in the physical blocks at present.Afterwards, the step S1607 among Figure 16 A can be performed.

If in step S1611, judge can writing no enough storage spaces in the physical blocks at present and store and write data and be used for storing one of them physical blocks among the physical blocks of the data that are written into blocks when belonging to all data that are written into blocks, then in step S1615 MMU 204 understand judge the physical blocks among the spare area 304b number whether less than standby entity block counts threshold value.If the number of the physical blocks among the spare area 304b is non-less than standby entity block counts threshold value, then MMU 204 can extract a physical blocks and will write data and be used for storing one of them physical blocks among the physical blocks of the data that are written into blocks and belongs to all data that are written into blocks and write in the physical blocks of being extracted from spare area 304b in step S1617.Afterwards, the step S1607 among Figure 16 A can be performed.

If the number of in step S1615, judging the physical blocks among the spare area 304b is less than standby entity block counts threshold value; Then MMU 204 can be carried out the physical blocks that the invalid data program of erasing is stored invalid data with release in step S1619, and execution in step S1615.

If in step S1601, judge when the data degree at random can write physical blocks at present equals physical blocks data degree threshold value at random, then whether MMU 204 can be judged can write to store in the physical blocks at present and belong to the data that are written into blocks in step S1621.If can write to store in the physical blocks at present belongs to the data that are written into blocks, the step S1603 among the execution graph 16B then.

If judgement can write not store in the physical blocks at present and belong to the data that are written into blocks in step S1621, whether the number that then MMU 204 can be judged the physical blocks among the spare area 304b in step S1623 is less than standby entity block counts threshold value.If the number of the physical blocks among the spare area 304b is less than standby entity block counts threshold value, then MMU 204 can be carried out the invalid datas program of erasing in step S1625, discharging the physical blocks of storage invalid data, and execution in step S1623.

If judge that in step S1623 the number of the physical blocks among the spare area 304b is non-less than standby entity block counts threshold value, then MMU 204 can judge whether the data degree at random that is written into blocks equals blocks data degree threshold value at random in step S1627.If judge when the data degree at random be written into blocks is not equal to blocks data degree threshold value at random, then MMU 204 can extract a physical blocks and will write data and writes in the physical blocks of being extracted from spare area 304b in step S1629.Afterwards, step S1607 can be performed.

If in step S1627, judge when the data degree at random be written into blocks equals blocks data degree threshold value at random, then MMU 204 can extract a physical blocks and will write data and be used for storing one of them physical blocks among the physical blocks of the data that are written into blocks and belongs to all data that are written into blocks and write in the physical blocks of being extracted from spare area 304b in step S1631.Afterwards, step S1607 can be performed.

What deserves to be mentioned is; In above-mentioned enforcement, MMU 204 can be moved one of them physical blocks among the physical blocks that is used for storing the data that are written into blocks and belong to all data that are written into blocks and the data that are written into blocks degree at random is still kept be not more than blocks data degree threshold value at random.Yet; The invention is not restricted to this; In another embodiment of the present invention; When storage space was enough, a plurality of physical blocks that MMU 204 also can be moved among the physical blocks that is used for storing the data that are written into blocks belonged to all data that are written into blocks, so that it is more concentrated to be written into the data of blocks.

It must be appreciated that the simple embodiment shown in Fig. 7 A, Fig. 7 B, Fig. 7 C, Fig. 8 A, Fig. 8 B, Fig. 9 A, Fig. 9 B, Figure 12 A, Figure 12 B, Figure 13 A, Figure 13 B, Figure 14 A and Figure 14 B is used to explain the present invention, and unrestricted the present invention.In embodiments of the present invention, each physical blocks of flash chip 106 is to have 64,128,256 or multiple entity page address more.

In sum; Method for writing data according to the embodiment of the invention can decide the physical page address that is used to write data by degree at random according to the data of each blocks, and the data that can avoid effectively thus belonging to same blocks were stored in a plurality of physical blocks dispersedly.Base this, can reduce time of arrangement valid data, promote to carry out the speed that main frame writes instruction thus.In addition; According to the method for writing data of the embodiment of the invention can be according to the data of each blocks the data degree at random of degree at random and each physical blocks decide the physical page address that is used to write data, the data that can avoid belonging to same blocks thus effectively were stored in a plurality of physical blocks dispersedly and were stored the data that too much belong to the Different Logic block in the same physical blocks.Based on this, can further reduce the time of arrangement valid data, promote the speed that main frame writes instruction of carrying out thus.

What should explain at last is: above embodiment is only in order to technical scheme of the present invention to be described but not limit it; Although the present invention has been carried out detailed explanation with reference to preferred embodiment; Those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, also can not make amended technical scheme break away from the spirit and the scope of technical scheme of the present invention and these are revised or be equal to replacement.

Claims

1. the method for writing data of a flash memory; The data that are used for coming from a host computer system write to a flash chip; Wherein said flash chip comprises a plurality of physical blocks, and each said physical blocks has a plurality of physical page address, and said method for writing data comprises:

Dispose a plurality of logical page addresses;

Said a plurality of logical page addresses are grouped into a plurality of blocks;

Write down the data degree at random of each said blocks, wherein the data of each said blocks degree at random is the number of physical blocks that is used to store the data of the blocks that belongs to corresponding;

From said host computer system, receive one and write data; The wherein said data that write are to desire to be written into one first logical page address; Said first logical page address belongs to one first blocks; Said first logical page address is one of them of said a plurality of logical page addresses, and said first blocks be said a plurality of blocks one of them;

Obtain one first physical page address, the first physical page address of wherein being obtained is one of them of said a plurality of physical page address; And

According to the data degree at random of said first blocks and the first physical page address of being obtained the said write data are write in the said flash chip,

Wherein the data of each said blocks degree at random is neither greater than blocks data degree threshold value at random.

2. the method for writing data of flash memory according to claim 1 also comprises said a plurality of physical blocks are grouped into a data field and a spare area at least.

3. the method for writing data of flash memory according to claim 1 wherein comprises the step that the said write data write in the said flash chip according to the data degree at random of said first blocks and the first physical page address of being obtained:

When D1＜TH1, then the said write data are write in the first physical page address of being obtained,

Wherein D1 is the data degree at random of said first blocks, and TH1 is said blocks data degree threshold values at random.

4. the method for writing data of flash memory according to claim 2 wherein also comprises the step that the said write data write in the said flash chip according to the data degree at random of said first blocks and the first physical page address of being obtained:

When D1=TH1; Judge then whether the affiliated physical blocks in the first physical page address that is obtained stores the data of said first blocks; Wherein work as the data that the affiliated physical blocks in the first physical page address that is obtained stores said first blocks; Then the said write data are write in the first physical page address of being obtained

Wherein work as the affiliated physical blocks in the first physical page address that is obtained and do not have the data that store said first blocks; Whether the residual memory space of then judging the physical blocks under the first physical page address obtained enough writes all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks

When the residual memory space of wherein working as the physical blocks under the first physical page address obtained enough writes said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks and belongs to all data of said first blocks; All data that then the said write data write in the first physical page address of being obtained and will belong to said first blocks in one of them physical blocks among the physical blocks of the data that are used for storing said first blocks write in the physical blocks under the first physical page address of being obtained

When the residual memory space of wherein working as the physical blocks under the first physical page address obtained does not enough write said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks and belongs to all data of said first blocks; Then among the physical blocks of said spare area, select one of them physical blocks and all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks are write in the selected physical blocks

5. the method for writing data of flash memory according to claim 2 also comprises:

Write down the data degree at random of each said physical blocks, wherein the data of each said physical blocks degree at random is the number of the blocks under the data that are stored in the corresponding physical blocks.

6. the method for writing data of flash memory according to claim 5 wherein comprises the step that the said write data write in the said flash chip according to the data degree at random of said first blocks and the first physical page address of being obtained:

The data degree at random of the physical blocks under data degree at random, the first physical page address of being obtained of said first blocks of foundation and the first physical page address of being obtained writes to the said write data in the said flash chip,

Wherein the data of each said physical blocks degree at random is neither greater than physical blocks data degree threshold value at random.

7. the method for writing data of flash memory according to claim 6, wherein the data degree at random according to the physical blocks under data degree at random, the first physical page address of being obtained of said first blocks and the first physical page address obtained comprises the step that the said write data write in the said flash chip:

When D1＜TH1 and D2＜TH2, then the said write data are write in the first physical page address of being obtained,

Wherein D1 is the data degree at random of said first blocks, and TH1 is said blocks data degree threshold values at random, and D2 is the data degree at random of the physical blocks under the first physical page address of being obtained, and TH2 is said physical blocks data degree threshold values at random.

8. the method for writing data of flash memory according to claim 6, wherein the data degree at random according to the physical blocks under data degree at random, the first physical page address of being obtained of said first blocks and the first physical page address obtained comprises the step that the said write data write in the said flash chip:

When D1＜TH1 and D2=TH2; Judge then whether the affiliated physical blocks in the first physical page address that is obtained stores the data of said first blocks; Wherein work as the affiliated physical blocks in the first physical page address that is obtained and do not have the data that store said first blocks; Then among the physical blocks of said spare area, select one of them physical blocks and the said write data are write to the selected physical blocks; And work as the data that the affiliated physical blocks in the first physical page address that is obtained stores said first blocks; Then the said write data are write in the first physical page address of being obtained, wherein D1 is the data degree at random of said first blocks, and TH1 is said blocks data degree threshold values at random; D2 is the data degree at random of the physical blocks under the first physical page address of being obtained, and TH2 is said physical blocks data degree threshold values at random.

9. the method for writing data of flash memory according to claim 6, wherein the data degree at random according to the physical blocks under data degree at random, the first physical page address of being obtained of said first blocks and the first physical page address obtained comprises the step that the said write data write in the said flash chip:

When D1=TH1 and D2=TH2; Judge then whether the affiliated physical blocks in the first physical page address that is obtained stores the data of said first blocks; Wherein work as the affiliated physical blocks in the first physical page address that is obtained and do not have the data that store said first blocks; Then among the physical blocks of said spare area, select one of them physical blocks and all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks are write in the selected physical blocks, and

Physical blocks under the first physical page address of being obtained stores the data of said first blocks; Then the said write data are write in the first physical page address of being obtained; Wherein D1 is the data degree at random of said first blocks; TH1 is said blocks data degree threshold values at random, and D2 is the data degree at random of the physical blocks under the first physical page address of being obtained, and TH2 is said physical blocks data degree threshold values at random.

10. the method for writing data of flash memory according to claim 6, wherein the data degree at random according to the physical blocks under data degree at random, the first physical page address of being obtained of said first blocks and the first physical page address obtained comprises the step that the said write data write in the said flash chip:

When D1=TH1 and D2＜TH2, judge then whether the physical blocks under the first physical page address of being obtained stores the data of said first blocks,

Wherein work as the data that the affiliated physical blocks in the first physical page address that is obtained stores said first blocks, then the said write data write in the first physical page address of being obtained,

When the residual memory space of wherein working as the physical blocks under the first physical page address obtained does not enough write said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks and belongs to all data of said first blocks; Then among the physical blocks of said spare area, select one of them physical blocks and all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks are write to selected physical blocks; Wherein D1 is the data degree at random of said first blocks; TH1 is said blocks data degree threshold values at random; D2 is the data degree at random of the physical blocks under the first physical page address of being obtained, and TH2 is said physical blocks data degree threshold values at random.

11. a flash controller is used for the data that come from a host computer system are write to a flash chip, wherein said flash chip comprises a plurality of physical blocks, and each said physical blocks has a plurality of physical page address, and said flash controller comprises:

One microprocessor unit;

One flash interface unit is electrically connected to said microprocessor unit, in order to be electrically connected to said flash chip;

One host interface unit is electrically connected to said microprocessor unit, in order to be electrically connected to said host computer system; And

One MMU; Be electrically connected to said microprocessor unit; In order to dispose a plurality of logical page addresses, said a plurality of logical page addresses are grouped into a plurality of blocks, and write down the data degree at random of each said blocks; Wherein the data of each said blocks degree at random is the number of physical blocks that is used to store the data of the blocks that belongs to corresponding

Wherein said host interface unit receives one and writes data from said host computer system; The wherein said data that write are to desire to be written into one first logical page address; Said first logical page address belongs to one first blocks; Said first logical page address is one of them of said a plurality of logical page addresses, and said first blocks be said a plurality of blocks one of them

Wherein said MMU is obtained one first physical page address, and the first physical page address of wherein being obtained is one of them of said a plurality of physical page address,

Wherein said MMU writes to the said write data in the said flash chip according to the data degree at random of said first blocks and the first physical page address of being obtained,

12. flash controller according to claim 11, wherein said MMU is grouped into a data field and a spare area at least with said a plurality of physical blocks.

13. flash controller according to claim 11, wherein when D1＜TH1, then said MMU writes to the said write data in the first physical page address of being obtained,

14. flash controller according to claim 12; Wherein when D1=TH1; Then said MMU judges whether the physical blocks under the first physical page address of being obtained stores the data of said first blocks; Wherein work as the data that the affiliated physical blocks in the first physical page address that is obtained stores said first blocks, then said MMU writes to the said write data in the first physical page address of being obtained

Wherein work as the affiliated physical blocks in the first physical page address that is obtained and do not have the data that store said first blocks; Then said MMU judges whether the residual memory space of the physical blocks under the first physical page address of being obtained enough writes all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks

When the residual memory space of wherein working as the physical blocks under the first physical page address obtained enough writes said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks and belongs to all data of said first blocks; Then said MMU writes to the said write data in the first physical page address of being obtained and all data that will belong to said first blocks in one of them physical blocks among the physical blocks of the data that are used for storing said first blocks write in the physical blocks under the first physical page address of being obtained

When the residual memory space of wherein working as the physical blocks under the first physical page address obtained does not enough write said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks and belongs to all data of said first blocks; Then said MMU is selected one of them physical blocks and all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks is write in the selected physical blocks among the physical blocks of said spare area

15. flash controller according to claim 12; The one data degree at random of wherein said each said physical blocks of MMU record, wherein the data of each said physical blocks degree at random is the number of the blocks under the data that are stored in the corresponding physical blocks.

16. flash controller according to claim 15, wherein said MMU also write to the said write data in the said flash chip according to the data degree at random of the physical blocks under the first physical page address of being obtained,

17. flash controller according to claim 16, wherein when D1＜TH1 and D2＜TH2, then said MMU writes to the said write data in the first physical page address of being obtained,

18. flash controller according to claim 16; Wherein when D1＜TH1 and D2=TH2; Then said MMU judges whether the physical blocks under the first physical page address of being obtained stores the data of said first blocks; Wherein work as the affiliated physical blocks in the first physical page address that is obtained and do not have the data that store said first blocks; Then said MMU is selected one of them physical blocks and the said write data is write to the selected physical blocks among the physical blocks of said spare area, and

Physical blocks under the first physical page address of being obtained stores the data of said first blocks, and then said MMU writes to the said write data in the first physical page address of being obtained,

19. flash controller according to claim 16; Wherein when D1=TH1 and D2=TH2; Then said MMU judges whether the physical blocks under the first physical page address of being obtained stores the data of said first blocks; Wherein work as the affiliated physical blocks in the first physical page address that is obtained and do not have the data that store said first blocks; Then said MMU is selected one of them physical blocks and all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks is write in the selected physical blocks among the physical blocks of said spare area, and

20. flash controller according to claim 16, wherein when D1=TH1 and D2＜TH2, then said MMU judges whether the physical blocks under the first physical page address of being obtained stores the data of said first blocks,

Wherein work as the data that the affiliated physical blocks in the first physical page address that is obtained stores said first blocks, then said MMU writes to the said write data in the first physical page address of being obtained,

21. a flash-memory storage system comprises:

One flash chip has a plurality of physical blocks and each said physical blocks has a plurality of physical page address;

A connector is in order to be electrically connected to a host computer system; And

One flash controller; Be electrically connected to said flash chip and said connector; In order to dispose a plurality of logical page addresses, said a plurality of logical page addresses are grouped into a plurality of blocks, and write down the data degree at random of each said blocks; Wherein the data of each said blocks degree at random is the number of physical blocks that is used to store the data of the blocks that belongs to corresponding

Wherein said flash controller receives one and writes data from said host computer system; The wherein said data that write are to desire to be written into one first logical page address; Said first logical page address belongs to one first blocks; Said first logical page address is one of them of said a plurality of logical page addresses, and said first blocks be said a plurality of blocks one of them

Wherein said flash controller is obtained one first physical page address, and the first physical page address of wherein being obtained is one of them of said a plurality of physical page address,

Wherein said flash controller writes to the said write data in the said flash chip according to the data degree at random of said first blocks and the first physical page address of being obtained,

22. flash-memory storage system according to claim 21, wherein said flash controller is grouped into a data field and a spare area at least with said a plurality of physical blocks.

23. flash-memory storage system according to claim 21, wherein when D1＜TH1, then said flash controller writes to the said write data in the first physical page address of being obtained,

24. flash-memory storage system according to claim 22; Wherein when D1=TH1; Then said flash controller judges whether the physical blocks under the first physical page address of being obtained stores the data of said first blocks; Wherein work as the data that the affiliated physical blocks in the first physical page address that is obtained stores said first blocks, then said flash controller writes to the said write data in the first physical page address of being obtained

Wherein work as the affiliated physical blocks in the first physical page address that is obtained and do not have the data that store said first blocks; Then said flash controller judges whether the residual memory space of the physical blocks under the first physical page address of being obtained enough writes all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks

When the residual memory space of wherein working as the physical blocks under the first physical page address obtained enough writes said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks and belongs to all data of said first blocks; Then said flash controller writes to the said write data in the first physical page address of being obtained and all data that will belong to said first blocks in one of them physical blocks among the physical blocks of the data that are used for storing said first blocks write in the physical blocks under the first physical page address of being obtained

When the residual memory space of wherein working as the physical blocks under the first physical page address obtained does not enough write said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks and belongs to all data of said first blocks; Then said flash controller is selected one of them physical blocks and all data that said write data and one of them physical blocks among the physical blocks of the data that are used for storing said first blocks belong to said first blocks is write in the selected physical blocks among the physical blocks of said spare area

25. flash-memory storage system according to claim 22; The one data degree at random of wherein said each said physical blocks of flash controller record, wherein the data of each said physical blocks degree at random is the number of the blocks under the data that are stored in the corresponding physical blocks.

26. flash-memory storage system according to claim 25, wherein said flash controller also write to the said write data in the said flash chip according to the data degree at random of the physical blocks under the first physical page address of being obtained,

Wherein the data of each said physical blocks degree at random is not more than physical blocks data degree threshold value at random.