CN103984635A - Data writing method, memory controller and memory storage device - Google Patents

Data writing method, memory controller and memory storage device Download PDF

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Publication number
CN103984635A
CN103984635A CN201310050783.XA CN201310050783A CN103984635A CN 103984635 A CN103984635 A CN 103984635A CN 201310050783 A CN201310050783 A CN 201310050783A CN 103984635 A CN103984635 A CN 103984635A
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entity
unit
those
instance
erase
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CN103984635B (en
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黄意翔
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The invention provides a data writing method, a memory controller and a memory storage device. The method is used for controlling a rewritable nonvolatile memory module, which comprises two storage memory cells. The method comprises the following steps of: configuring a plurality of logical addresses to be mapped to at least part of entity erasing units in the two memory cells; receiving a writing command from a host system, which indicates that the data are written in one logical address; writing the data in one entity erasing unit in the two memory cells; judging which memory cell does the entity erasing unit belong to; if the entity erasing unit belongs to one memory cell, erasing one entity erasing unit in the other memory cell when the data are written in. therefore, the speed that the data are written in the memory storage device by the host system can be increased.

Description

Method for writing data, Memory Controller and memorizer memory devices
Technical field
The invention relates to a kind of method for writing data, and particularly relevant for a kind of method for writing data for duplicative non-volatile memory module, Memory Controller and memorizer memory devices.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and consumer is also increased rapidly to the demand of Storage Media.For example, because duplicative non-volatile memory module (, flash memory) has that data are non-volatile, power saving, volume be little, and the characteristic such as machinery-free structure, so be applicable to being built in above-mentioned given an example various portable multimedia devices very much.
In general, duplicative non-volatile memory module can be electrically connected to a host computer system by a transmission interface.Host computer system can write to duplicative non-volatile memory module by data by this transmission interface.And, in duplicative non-volatile memory module, can comprise a plurality of passages, thereby increase the speed of data writing in duplicative non-volatile memory module.Yet the speed of data writing has been greater than the transmission speed of transmission interface in duplicative non-volatile memory module, the speed of main frame data writing just can only be decided by the transmission speed of transmission interface.Therefore, how to increase again in the case the speed of main frame data writing, the topic that those skilled in the art are concerned about for this reason.
Summary of the invention
Exemplary embodiment of the present invention proposes a kind of method for writing data, Memory Controller and memorizer memory devices, can increase host computer system data writing to the speed of memorizer memory devices.
The present invention's one exemplary embodiment proposes a kind of method for writing data, for controlling a duplicative non-volatile memory module.This duplicative non-volatile memory module comprises first storage unit and second storage unit, and the first storage unit comprises a plurality of first instance erase units, and the second storage unit comprises a plurality of second instance erase units.This method for writing data comprises: configure a plurality of logical addresses to map at least part of first instance erase unit and at least part of second instance erase unit; Reception writes instruction from one of a host computer system, wherein writes instruction indication the first data are write to first logical address; From first instance erase unit and second instance erase unit, obtain a 3rd entity erase unit, and the first data are write to the 3rd entity erase unit; Judge that the 3rd entity erase unit belongs to the first storage unit or the second storage unit; And if the 3rd entity erase unit belongs to the first storage unit, when the first data are write to the 3rd entity erase unit, wipe one of them of second instance erase unit.
In an exemplary embodiment, above-mentioned method for writing data also comprises: if the 3rd entity erase unit belongs to the second storage unit, when the first data are write to the 3rd entity erase unit, wipe one of them of first instance erase unit.
In an exemplary embodiment, above-mentioned method for writing data also comprises: first instance erase unit and second instance erase unit are at least divided into a data field and an idle district, and wherein above-mentioned at least part of first instance erase unit and above-mentioned at least part of second instance erase unit are to belong to data field; And first scratching area and second scratching area be set.The 3rd above-mentioned entity erase unit is to belong to idle district, and the first instance erase unit being wiped free of is to belong to the first scratching area, and the second instance erase unit being wiped free of is to belong to the second scratching area.
In an exemplary embodiment, the first above-mentioned logical address is the 4th entity erase unit mapping in first instance erase unit and second instance erase unit, after the first data are write to the step of the 3rd entity erase unit, this method for writing data also comprises: judge whether the 4th entity erase unit needs to be wiped free of; If the 4th entity erase unit need to be wiped free of, judge whether an entity erase unit number of the first scratching area or the second scratching area is more than or equal to a critical value; If the entity erase unit number of the first scratching area and the second scratching area is less than critical value, the 4th entity erase unit is associated to corresponding the first scratching area or the second scratching area.
In an exemplary embodiment, above-mentioned method for writing data also comprises: if the entity erase unit number of the first scratching area or the second scratching area is more than or equal to critical value, wipe the 4th entity erase unit, and the 4th entity erase unit is associated to idle district.
In an exemplary embodiment, above-mentioned method for writing data also comprises: by the first instance erase unit being wiped free of or the second instance erase unit being wiped free of is associated to idle district.
In an exemplary embodiment, after the first data are written into the 3rd entity erase unit, the first above-mentioned scratching area comprises a plurality of first instance erase units that have been wiped free of, and the second scratching area comprises a plurality of second instance erase units that have been wiped free of.This method for writing data also comprises: alternately a first instance erase unit being wiped free of and a second instance erase unit being wiped free of are associated to idle district.
In an exemplary embodiment, each above-mentioned first instance erase unit comprises a plurality of entity sequencing unit, and each second instance erase unit comprises a plurality of entity sequencing unit.This method for writing data also comprises: according to a writing speed of duplicative non-volatile memory module and an erasing time, determine a positive integer n; The first data are write in the 3rd entity erase unit behind n entity sequencing unit, check in the first scratching area or the second scratching area whether have the entity erase unit that need to be wiped free of; And if in the first scratching area or the second scratching area, have an entity erase unit that need to be wiped free of, wipe described in execution second instance erase unit one of them step or described in wipe first instance erase unit one of them step.
In an exemplary embodiment, above-mentioned logical address is to map to alternately one of them of first instance erase unit and one of them of second instance erase unit.
With another one angle, the present invention's one exemplary embodiment proposes a kind of memorizer memory devices, comprises connector, duplicative non-volatile memory module and Memory Controller.Connector is to be electrically connected to a host computer system.Duplicative non-volatile memory module comprises first storage unit and second storage unit, and wherein the first storage unit comprises a plurality of first instance erase units, and the second storage unit comprises a plurality of second instance erase units.Memory Controller is to be electrically connected to connector and duplicative non-volatile memory module, in order to configure a plurality of logical addresses to map at least part of first instance erase unit and at least part of second instance erase unit.Memory Controller also writes instruction in order to of receiving from host computer system, and this writes instruction indication the first data are write to first logical address.Memory Controller is also in order to obtain a 3rd entity erase unit from first instance erase unit and second instance erase unit, and the first data are write to the 3rd entity erase unit.Memory Controller is also in order to judge that the 3rd entity erase unit is to belong to the first storage unit or the second storage unit.If the 3rd entity erase unit is to belong to the first storage unit, Memory Controller, in order to when the first data are write to the 3rd entity erase unit, is wiped one of them of second instance erase unit.
In an exemplary embodiment, if the 3rd entity erase unit belongs to the second storage unit, Memory Controller, in order to when the first data are write to the 3rd entity erase unit, is wiped one of them of first instance erase unit.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to be at least divided into a data field and an idle district by first instance erase unit and second instance erase unit, and wherein above-mentioned at least part of first instance erase unit and above-mentioned at least part of second instance erase unit are to belong to data field.Memory Controller is also in order to arrange first scratching area and second scratching area.The 3rd above-mentioned entity erase unit is to belong to idle district, and the first instance erase unit being wiped free of is to belong to the first scratching area, and the second instance erase unit being wiped free of is to belong to the second scratching area.
In an exemplary embodiment, the first above-mentioned logical address is the 4th entity erase unit mapping in first instance erase unit and second instance erase unit.After the first data are write to the 3rd entity erase unit, Memory Controller is also in order to judge whether the 4th entity erase unit needs to be wiped free of.If the 4th entity erase unit need to be wiped free of, Memory Controller is in order to judge whether an entity erase unit number of the first scratching area or the second scratching area is more than or equal to a critical value.If the entity erase unit number of the first scratching area and the second scratching area is less than critical value, Memory Controller is in order to be associated to corresponding the first scratching area or the second scratching area by the 4th entity erase unit.
In an exemplary embodiment, if the entity erase unit number of the first scratching area or the second scratching area is more than or equal to critical value, Memory Controller is in order to wipe the 4th entity erase unit, and the 4th entity erase unit is associated to idle district.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to by the first instance erase unit being wiped free of or the second instance erase unit being wiped free of is associated to idle district.
In an exemplary embodiment, after the first data are written into the 3rd entity erase unit, the first scratching area comprises a plurality of first instance erase units that have been wiped free of, and the second scratching area comprises a plurality of second instance erase units that have been wiped free of.Memory Controller is also in order to be associated to idle district by one of them of the first instance erase unit being wiped free of with one of them of the second instance erase unit that has been wiped free of alternately.
In an exemplary embodiment, above-mentioned each first instance erase unit comprises a plurality of entity sequencing unit, and each second instance erase unit comprises a plurality of entity sequencing unit.Memory Controller is also in order to determine a positive integer n according to a writing speed of duplicative non-volatile memory module and an erasing time.Memory Controller, also in order to behind n entity sequencing unit in the first data are write to the 3rd entity erase unit, checks in the first scratching area or the second scratching area whether have the entity erase unit that need to be wiped free of.If there is the entity erase unit that need to be wiped free of in the first scratching area or the second scratching area, Memory Controller in order to wipe described in carrying out second instance erase unit one of them operation or described in wipe first instance erase unit one of them operation.
With another one angle, the present invention's one exemplary embodiment proposes a kind of Memory Controller, for controlling a duplicative non-volatile memory module.This Memory Controller comprises host interface, memory interface and memory management circuitry.Host interface is to be electrically connected to a host computer system.Memory interface is to be electrically connected to duplicative non-volatile memory module.Duplicative non-volatile memory module comprises first storage unit and second storage unit, and wherein the first storage unit comprises a plurality of first instance erase units, and the second storage unit comprises a plurality of second instance erase units.Memory management circuitry is to be electrically connected to host interface and memory interface, in order to configure a plurality of logical addresses to map at least part of first instance erase unit and at least part of second instance erase unit.Memory management circuitry also writes instruction in order to of receiving from host computer system, and this writes instruction indication the first data are write to first logical address.Memory management circuitry is also in order to obtain a 3rd entity erase unit from first instance erase unit and second instance erase unit, and the first data are write to the 3rd entity erase unit.Memory management circuitry is also in order to judge that the 3rd entity erase unit is to belong to the first storage unit or the second storage unit.If the 3rd entity erase unit is to belong to the first storage unit, memory management circuitry, in order to when the first data are write to the 3rd entity erase unit, is wiped one of them of second instance erase unit.
In an exemplary embodiment, if the 3rd entity erase unit belongs to the second storage unit, memory management circuitry, in order to when the first data are write to the 3rd entity erase unit, is wiped one of them of first instance erase unit.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to be at least divided into a data field and an idle district by first instance erase unit and second instance erase unit, and wherein above-mentioned at least part of first instance erase unit and above-mentioned at least part of second instance erase unit are to belong to data field.Memory management circuitry is also in order to arrange first scratching area and second scratching area.The 3rd above-mentioned entity erase unit is to belong to idle district, and the first instance erase unit being wiped free of is to belong to the first scratching area, and the second instance erase unit being wiped free of is to belong to the second scratching area.
In an exemplary embodiment, the first above-mentioned logical address is the 4th entity erase unit mapping in first instance erase unit and second instance erase unit.After the first data are write to the 3rd entity erase unit, memory management circuitry is also in order to judge whether the 4th entity erase unit needs to be wiped free of.If the 4th entity erase unit need to be wiped free of, memory management circuitry is in order to judge whether an entity erase unit number of the first scratching area or the second scratching area is more than or equal to a critical value.If the entity erase unit number of the first scratching area and the second scratching area is less than critical value, memory management circuitry is in order to be associated to corresponding the first scratching area or the second scratching area by the 4th entity erase unit.
In an exemplary embodiment, if the entity erase unit number of the first scratching area or the second scratching area is more than or equal to critical value, memory management circuitry is in order to wipe the 4th entity erase unit, and the 4th entity erase unit is associated to idle district.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to by the first instance erase unit being wiped free of or the second instance erase unit being wiped free of is associated to idle district.
In an exemplary embodiment, after the first data are written into the 3rd entity erase unit, the first scratching area comprises a plurality of first instance erase units that have been wiped free of, and the second scratching area comprises a plurality of second instance erase units that have been wiped free of.Memory management circuitry is also in order to be associated to idle district by one of them of the first instance erase unit being wiped free of with one of them of the second instance erase unit that has been wiped free of alternately.
In an exemplary embodiment, above-mentioned each first instance erase unit comprises a plurality of entity sequencing unit, and each second instance erase unit comprises a plurality of entity sequencing unit.Memory management circuitry is also in order to determine a positive integer n according to a writing speed of duplicative non-volatile memory module and an erasing time.Memory management circuitry, also in order to behind n entity sequencing unit in the first data are write to the 3rd entity erase unit, checks in the first scratching area or the second scratching area whether have the entity erase unit that need to be wiped free of.If there is the entity erase unit that need to be wiped free of in the first scratching area or the second scratching area, memory management circuitry in order to wipe described in carrying out second instance erase unit one of them operation or described in wipe first instance erase unit one of them operation.
Based on above-mentioned, the method for writing data that exemplary embodiment of the present invention proposes, memorizer memory devices and Memory Controller, can carry out simultaneously and write and the operation of wiping, thereby increase host computer system, data write to the speed of memorizer memory devices.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A is the summary calcspar of the shown host computer system of an exemplary embodiment and memorizer memory devices;
Figure 1B is the schematic diagram of the shown computer of an exemplary embodiment, input/output device and memorizer memory devices;
Fig. 1 C is the schematic diagram of the shown host computer system of an exemplary embodiment and memorizer memory devices;
Fig. 2 is the summary calcspar that the memorizer memory devices shown in Figure 1A is shown;
Fig. 3 is the summary calcspar of the shown Memory Controller of an exemplary embodiment;
Fig. 4 is the example schematic of the shown management duplicative of exemplary embodiment non-volatile memory module;
Fig. 5 is the schematic diagram that an exemplary embodiment illustrates the first scratching area and the second scratching area;
Fig. 6 A and Fig. 6 B are the process flow diagrams that an exemplary embodiment explanation writes the first data;
Fig. 7 is the process flow diagram that an exemplary embodiment illustrates method for writing data;
Fig. 8 A and Fig. 8 B are that the second exemplary embodiment illustrates the process flow diagram that writes the first data.
Description of reference numerals:
1000: host computer system;
1100: computer;
1102: microprocessor;
1104: random access memory;
1106: input/output device;
1108: system bus;
1110: data transmission interface;
1202: mouse;
1204: keyboard;
1206: display;
1208: printer;
1212: portable disk;
1214: storage card;
1216: solid state hard disc;
1310: digital camera;
1312:SD card;
1314:MMC card;
1316: memory stick;
1318:CF card;
1320: embedded storage device;
100: memorizer memory devices;
102: connector;
104: Memory Controller;
106: duplicative non-volatile memory module;
210,220: storage unit;
212 (0)~212 (A), 222 (0)~222 (B): entity erase unit;
202: memory management circuitry;
204: host interface;
206: memory interface;
252: memory buffer;
254: electric power management circuit;
256: bug check and correcting circuit;
402: data field;
404: idle district;
406: system region;
408: replace district;
410 (0)~410 (I): logical address;
420: the first data;
510: the first scratching areas;
520: the second scratching areas;
S602, S604, S606, S608, S610, S612, S614, S616, S618, S620, S622, S624, S626, S628, S630, S632, S634, S636, S638, S640, S642, S702, S704, S706, S708, S710, S712, S802, S804: step.
Embodiment
Generally speaking, memorizer memory devices (also claiming memory storage system) comprises duplicative non-volatile memory module and controller (also claiming control circuit).Conventionally memorizer memory devices is to use together with host computer system, so that host computer system can write to data memorizer memory devices or reading out data from memorizer memory devices.
Figure 1A is the summary calcspar of the shown host computer system of an exemplary embodiment and memorizer memory devices.
Figure 1B is the schematic diagram of the shown computer of an exemplary embodiment, input/output device and memorizer memory devices.
Fig. 1 C is the schematic diagram of the shown host computer system of an exemplary embodiment and memorizer memory devices.
Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memorizer memory devices 100 is to be electrically connected by data transmission interface 1110 and other elements of host computer system 1000.By microprocessor 1102, random access memory 1104, data can be write to memorizer memory devices 100 or reading out data from memorizer memory devices 100 with the running of input/output device 1106.For example, memorizer memory devices 100 can be the duplicative non-volatile memory storage device of portable disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 as shown in Figure 1B etc.
Generally speaking, host computer system 1000 is to coordinate substantially any system with storage data with memorizer memory devices 100.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, music player or video player in another exemplary embodiment of the present invention.For example, in host computer system, be digital camera (video camera) 1310 o'clock, duplicative non-volatile memory storage device is its SD card 1312 using, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is to be directly electrically connected on the substrate of host computer system.
Fig. 2 is the summary calcspar that the memorizer memory devices shown in Figure 1A is shown.
Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and duplicative non-volatile memory module 106.
In this exemplary embodiment, connector 102 is to be compatible to high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard.Yet, it must be appreciated, the invention is not restricted to this, connector 102 can be also to meet advanced annex (the Serial Advanced Technology Attachment of sequence, SATA) standard, advanced annex arranged side by side (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Ins t i tute of Electrical and Electronic Engineers, IEEE) 1394 standards, USB (universal serial bus) (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, a hypervelocity generation (Ultra High Speed-I, UHS-I) interface standard, hypervelocity two generations (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, built-in multimedia memory card (Embedded Multimedia Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UPS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other applicable standards.
Memory Controller 104 is a plurality of logic gates or the steering order with hardware pattern or firmware pattern implementation in order to execution, and according to the instruction of host computer system 1000, in duplicative non-volatile memory module 106, carries out the runnings such as writing, read and wipe of data.
Duplicative non-volatile memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to store host computer system 1000.Duplicative non-volatile memory module 106 comprises storage unit 210 (also claiming the first storage unit) and storage unit 220 (also claiming the second storage unit).Storage unit 210 comprises entity erase unit 212 (0)~212 (A) (also claiming first instance erase unit), and storage unit 220 comprises entity erase unit 222 (0)~222 (B) (also claiming second instance erase unit).Storage unit 210 can be carried out the operation of reading, write and wiping independently with storage unit 220.For example, storage unit 210 is to be electrically connected to Memory Controller 104 by least one first passage, and storage unit 220 is to be electrically connected to Memory Controller 104 by least one second channel, and first passage is different from second channel.Or storage unit 210 is controlled by least one first enable signal (also claiming CE signal), and storage unit 220 is controlled by least one second enable signal, and the first enable signal is different from the second enable signal.In other words, during operation that storage unit 210 reads, writes or wipe in execution, storage unit 220 also can be carried out the operation of reading, writing or wipe.And the performed operation of storage unit 210 can be different from the operation performed to storage unit 220.On the other hand, storage unit 210 and storage unit 220 can belong to different memory crystal grain (die), or belong to identical memory crystal grain, and the present invention is also not subject to the limits.
Each entity erase unit has respectively a plurality of entity sequencing unit, and the entity sequencing unit that belongs to same entity erase unit can be write independently and side by side be wiped.For example, each entity erase unit is comprised of 128 entity sequencing unit.Yet, it must be appreciated, the invention is not restricted to this, each entity erase unit can be comprised of 64 entity sequencing unit, 256 entity sequencing unit or other arbitrarily individual entity sequencing unit.
Again specifically, entity erase unit is the least unit of wiping.That is, the memory cell being wiped free of in the lump that each entity erase unit contains minimal amount.The minimum unit that entity sequencing unit is sequencing.That is the minimum unit that, entity sequencing unit is data writing.Each entity sequencing unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises a plurality of entities access address in order to store user's data, and redundancy ratio special zone for example, in order to the data (, control signal and error correcting code) of stocking system.In this exemplary embodiment, in the data bit district of each entity sequencing unit, can comprise 4 entity access addresses, and the size of an entity access address is 512 bit byte, B).Yet, in other exemplary embodiment, in data bit district, also can comprise 8,16 or the more or less entity access address of number, the present invention does not limit size and the number of entity access address.For example, entity erase unit is physical blocks, and entity sequencing unit is physical page or entity fan.
In this exemplary embodiment, duplicative non-volatile memory module 106 is multistage memory cell (Multi Level Cell, MLC) NAND type flash memory module, in a memory cell, can store at least 2 Bit datas.Yet, the invention is not restricted to this, duplicative non-volatile memory module 106 is single-order memory cell (Single Level Cell also, SLC) NAND type flash memory module, Complex Order memory cell (Trinary Level Cell, TLC) NAND type flash memory module, other flash memory module or other have the memory module of identical characteristics.
Fig. 3 is the summary calcspar of the shown Memory Controller of an exemplary embodiment.
Please refer to Fig. 3, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has a plurality of steering orders, and when memorizer memory devices 100 running, these a little steering orders can be performed to carry out the runnings such as writing, read and wipe of data.While below describing the operation of memory management circuitry 202, be equal to the operation of describing Memory Controller 104, and repeat no more.
In this exemplary embodiment, the steering order of memory management circuitry 202 is to carry out implementation with firmware pattern.For example, memory management circuitry 202 has microprocessor unit (not shown and ROM (read-only memory) (not shown), and these a little steering orders are to be burned onto in this ROM (read-only memory).When memorizer memory devices 100 running, these a little steering orders can be carried out to carry out by microprocessor unit the runnings such as writing, read and wipe of data.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can procedure code pattern for example be stored in, in the specific region (, being exclusively used in the system region of storage system data in memory module) of duplicative non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has the code of driving, and when Memory Controller 104 is enabled, microprocessor unit can first be carried out this and drive code section that the steering order being stored in duplicative non-volatile memory module 106 is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can turn round these a little steering orders to carry out the runnings such as writing, read and wipe of data.
In addition,, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can a hardware pattern be carried out implementation.For example, memory management circuitry 202 comprises microcontroller, Memory Management Unit, storer writing unit, storer reading unit, memory erase unit and data processing unit.Memory Management Unit, storer writing unit, storer reading unit, memory erase unit and data processing unit are to be electrically connected to microcontroller.Wherein, Memory Management Unit is in order to manage the entity erase unit of duplicative non-volatile memory module 106; Storer writing unit writes instruction data are write in duplicative non-volatile memory module 106 in order to duplicative non-volatile memory module 106 is assigned; Storer reading unit is in order to assign reading command with reading out data from duplicative non-volatile memory module 106 to duplicative non-volatile memory module 106; Memory erase unit is in order to assign erasing instruction so that data are wiped from duplicative non-volatile memory module 106 to duplicative non-volatile memory module 106; And data processing unit wants to write to the data of duplicative non-volatile memory module 106 and the data that read from duplicative non-volatile memory module 106 in order to process.
Host interface 204 is instruction and the data that are electrically connected to memory management circuitry 202 and transmit in order to reception and identification host computer system 1000.That is to say, the instruction that host computer system 1000 transmits and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is to be compatible to PCI Express standard.Yet, it must be appreciated and the invention is not restricted to this, host interface 204 can be to be also compatible to SATA standard, PATA standard, IEEE1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other applicable data transmission standards.
Memory interface 206 is to be electrically connected to memory management circuitry 202 and in order to access duplicative non-volatile memory module 106.That is to say, the data of wanting to write to duplicative non-volatile memory module 106 can be converted to 106 receptible forms of duplicative non-volatile memory module by memory interface 206.
In the present invention's one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.
Memory buffer 252 is to be electrically connected to memory management circuitry 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from duplicative non-volatile memory module 106.
Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.
Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives while writing instruction from host computer system 1000, bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 corresponding these data that write instruction can be write in duplicative non-volatile memory module 106 with corresponding bug check and correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code during reading out data from duplicative non-volatile memory module 106 simultaneously, and bug check and correcting circuit 256 can be according to this bug check and correcting code to read data execution error inspection and correction programs.
Fig. 4 is the example schematic of the shown management duplicative of exemplary embodiment non-volatile memory module.
It must be appreciated, when this describes the running of entity erase unit of duplicative non-volatile memory module 106, with " division ", " extraction ", " association " and etc. word to carry out application entity erase unit be concept in logic.That is to say, the physical location of the entity erase unit in duplicative non-volatile memory module 106 is not changed, but in logic the entity erase unit of duplicative non-volatile memory module 106 is operated.
Please refer to Fig. 4, Memory Controller 104 can logically be divided into a plurality of regions by the entity erase unit of duplicative non-volatile memory module 106 212 (0)~212 (A), 222 (0)~222 (B), for example, be data field 402, idle district 404, system region 406 and replacement district 408.
Data field 402 is the data that come from host computer system 1000 in order to store with the entity erase unit in idle district 404.Specifically, data field 402 is entity erase units of storage data, and the entity erase unit in idle district 404 is the entity erase units in order to replacement data district 402.Therefore, the entity erase unit in idle district 404 be sky or spendable entity erase unit, i.e. no record data or be labeled as invalid data useless.That is to say, the entity erase unit in idle district 404 has been performed wipes running, or the entity erase unit in idle district 404 is extracted for before storage data, and the entity erase unit extracting can first be performed and wipe running.Therefore, the entity erase unit of the entity erase unit in idle district 404 for being used.
The entity erase unit that belongs in logic system region 406 is in order to register system data, and wherein this system data comprises about the manufacturer of memory chip and model, the entity erase unit number of memory chip, the entity sequencing unit number of each entity erase unit etc.
Belonging in logic the entity erase unit replacing in district 408 is to substitute entity erase unit.For example, duplicative non-volatile memory module can be reserved 4% entity erase unit and uses as changing when dispatching from the factory.That is to say, when the entity erase unit in data field 402,404Yu system region, idle district 406 is damaged, the entity erase unit of reserving in replacing district 408 is in order to replacing damaged entity erase unit (that is, bad entity erase unit (bad block)).Therefore, if when still having normal entity erase unit in replacement district 408 and the damage of entity erase unit occurring, Memory Controller 104 can extract the entity erase unit that normal entity erase unit is changed damage from replace district 408.If when replacing in district 408 without normal entity erase unit and the damage of entity erase unit occurring, Memory Controller 104 can be declared as write protection (write protect) state by whole memorizer memory devices 100, and data writing again.In another exemplary embodiment, replace district 408 and also can share the entity erase unit that comprises invalid data with idle district 404.
Particularly, the quantity of the entity erase unit in data field 402, idle district 404, system region 406 and replacement district 408 can be different according to different storer specifications.In addition, it must be appreciated, in the running of memorizer memory devices 100, the grouping relation that entity erase unit is associated to data field 402, idle district 404, system region 406 and replacement district 408 can dynamically change.For example, the entity erase unit in idle district 404 damages and the entity erase unit that is substituted district 408 while replacing, and the entity erase unit that originally replaces district 408 can be associated to idle district 404.In this exemplary embodiment, system region 406 and replacement district 408 have comprised the entity erase unit of part in storage unit 210 and storage unit 220.Yet in other exemplary embodiment, system region 406 also can only include the entity erase unit in storage unit 210 or storage unit 220 with replacement district 408, the present invention is also not subject to the limits.
Memory Controller 104 can be beneficial to carry out data access in the entity erase unit of storage data in configuration logic address 410 (0)~410 (I).For example, for example, when memorizer memory devices 100 (is passed through a file system by the operating system in host computer system 1000, while FAT32) formaing, logical address 410 (0)~410 (I) can map to the entity erase unit of data field 402 respectively.At this, memory management circuitry 202 can be set up logical address-entity erase unit mapping table (logical address-physical erasing unit mapping table), to record the mapping relations between logical address and entity erase unit.In this exemplary embodiment, the size of a logical address is same as the size of an entity erase unit, and logical address also can be called as logical block addresses (logical block address, LBA).Yet in other exemplary embodiment, the size of a logical address can be also the size of an entity sequencing unit or other are big or small, the present invention is also not subject to the limits.
In this exemplary embodiment, when memory management circuitry 202 configuration logic address 410 (0)~410 (I), logical address 410 (0)~410 (I) is to map to alternately entity erase unit in storage unit 210 and an entity erase unit in storage unit 220.For example, logical address 410 (0) is to map to entity erase unit 212 (0), logical address 410 (1) is to map to entity erase unit 222 (0), and logical address 410 (2) is to map to entity erase unit 212 (1), by that analogy.Yet in other exemplary embodiment, memory management circuitry 202 also can map to the entity erase unit in data field 402 with noninterlace or other modes by logical address 410 (0)~410 (I), the present invention is also not subject to the limits.
When host computer system 1000 will write to memorizer memory devices 100 by data, host computer system 1000 can transmit one write instruction to memory management circuitry 202, and this writes instruction meeting indication data are write to which logical address.For example, the instruction that writes that host computer system 1000 transmits is that indication writes to logical address 410 (0) (also claiming the first logical address) by the first data 420.In other words, host computer system 1000 is data in novel entities erase unit 212 (0) (also claiming the 4th entity erase unit) more.Memory management circuitry 202, after receiving this and writing instruction, can be extracted an entity erase unit (also claiming the 3rd entity erase unit) from idle district 404, and the first data 420 are write so far in the middle of the 3rd entity erase unit.Memory management circuitry 202 so far the 3rd entity erase unit that also logical address 410 (0) can be remapped, and the 3rd entity erase unit is associated to data field 402.Specifically, memory management circuitry 202 can these the 3rd entity erase units of judgement be to belong to entity erase unit 212 (0)~212 (A) in storage unit 210 or the entity erase unit 222 (0)~22 (B) in storage unit 220.If this 3rd entity erase unit be belong to storage unit 210 entity erase unit (for example, entity erase unit 212 (C)), when the first data 420 being write so far to the 3rd entity erase unit, memory management circuitry 202 is at least one the entity erase unit in eraseable memory unit 220 simultaneously.If this 3rd entity erase unit be belong to storage unit 220 entity erase unit (for example, entity erase unit 222 (D)), when the first data 420 being write so far to the 3rd entity erase unit, memory management circuitry 202 is at least one the entity erase unit in eraseable memory unit 210 simultaneously.That is to say, when memory management circuitry 202 writes to one of them of storage unit 210 and storage unit 220 by the first data 420, can wipe at least one the entity erase unit in another one storage unit simultaneously.Below will lift an exemplary embodiment describes in detail.
Fig. 5 is the schematic diagram that an exemplary embodiment illustrates the first scratching area and the second scratching area.
Please refer to Fig. 5, except above-mentioned region, memory management circuitry 202 also can logically arrange the first scratching area 510 and the second scratching area 520.When memorizer memory devices 100 is formatted, in the first scratching area 510 and the second scratching area 520, do not have any entity erase unit.Along with the running of memory management circuitry 202, need to be wiped free of but the entity erase unit that is not also wiped free of can be associated in the first scratching area 510 or the second scratching area 520.Specifically, in the first scratching area 510, only the entity erase unit that belongs to storage unit 210 can be placed, and only the entity erase unit that belongs to storage unit 220 can be placed in the second scratching area 520.And the number that memory management circuitry 202 can limit entity erase unit in the first scratching area 510 and the second scratching area 520 can not surpass a critical value.
With above-mentioned example, after the first data 420 being write to an entity erase unit in idle district 404, in entity erase unit 212 (0), the data of part have become invalid data, and memory management circuitry 202 can judge whether entity erase unit 212 (0) needs to be wiped free of.For example, data all in entity erase unit 212 (0) have become invalid data, and memory management circuitry 202 can need to be wiped free of by judgement entity erase unit 212 (0).If entity erase unit 212 (0) need to be wiped free of, memory management circuitry 202 can judgement entity erase unit 212 (0) be corresponding to the first scratching area 510 or the second scratching area 520.At this, because entity erase unit 212 (0) is to belong to storage unit 210, so memory management circuitry 202 can judgement entity erase unit 212 (0) be corresponding to the first scratching area 510.Next, memory management circuitry 202 can judge whether the entity erase unit number (that is, the number of entity erase unit in the first scratching area 510) of the first scratching area 510 is more than or equal to above-mentioned critical value.If the entity erase unit number of the first scratching area 510 is less than this critical value, memory management circuitry 202 can be associated to the first scratching area 510 by entity erase unit 212 (0).On the contrary, if the entity erase unit number of the first scratching area 510 is more than or equal to this critical value, memory management circuitry 202 can be wiped entity erase unit 212 (0) and entity erase unit 212 (0) is associated to idle district 404.Similarly, the entity erase unit being wiped free of when needs (for example, entity erase unit 222 (0)) be while belonging to the second scratching area 520, memory management circuitry 202 can judge whether the entity erase unit number of the second scratching area 520 is more than or equal to this critical value, thereby judges whether this entity erase unit to be associated to the second scratching area 520.That is when if the entity erase unit number of the first scratching area 510 and the second scratching area 520 is less than critical value, the entity erase unit that need to be wiped free of can be associated to the first scratching area 510 or the second scratching area 520.If when the first corresponding scratching area 510 or the entity erase unit number of the second scratching area 520 are more than or equal to critical value, the entity erase unit that need to be wiped free of can be wiped free of and be associated to idle district.
What in the first scratching area 510 and the second scratching area 520, place as mentioned above, is need to be wiped free of but the entity erase unit that is not also wiped free of.Therefore, when memory management circuitry 202 writes to a 3rd entity erase unit in idle district 404 by the first data 420, memory management circuitry 202 is from the first scratching area 510 or the second scratching area 520, to obtain an entity erase unit that will be wiped free of.Specifically, for example, if the 3rd entity erase unit (, entity erase unit 212 (C)) is to belong to storage unit 210, memory management circuitry 202 can be wiped at least one entity erase unit in the second scratching area 520.Or for example, if the 3rd entity erase unit (, entity erase unit 222 (D)) is to belong to storage unit 220, memory management circuitry 202 can be wiped at least one entity erase unit in the first scratching area 510.
In addition,, after the first data 420 are write to the 3rd entity erase unit, one or more entity erase unit being wiped free of in during writing can be stored management circuit 202 and be associated to idle district 404.In an exemplary embodiment, memory management circuitry 202 can write many stroke counts according to this after, the entity erase unit that these are wiped free of is associated to idle district 404 alternately.Specifically, after one or more data being write to the entity erase unit in idle district, the first scratching area 510 may comprise the entity erase unit that one or more has been wiped free of, and the second scratching area 520 also may comprise the entity erase unit that one or more has been wiped free of.Memory management circuitry 202 can be selected an entity erase unit being wiped free of from one of them of the first scratching area 510 and the second scratching area 520, and the entity erase unit that this has been wiped free of is associated to the district 404 of leaving unused.Next, memory management circuitry 202 can be selected an entity erase unit being wiped free of from another scratching area, and the entity erase unit that this has been wiped free of is associated to idle district 404.Yet, in another exemplary embodiment, memory management circuitry 202 also can once all be associated to the entity erase unit being wiped free of in the first scratching area 510 idle district 404 or once the entity erase unit being wiped free of in the second scratching area 520 is all associated to idle district 404 when upgrading system information.This time point that upgrades system information can be in memory management circuitry 202, to upgrade the time point of above-mentioned logical address-entity erase unit mapping table, or upgrades the time point of other system information, and the present invention is also not subject to the limits.
In an exemplary embodiment, memory management circuitry 202 can be a writing speed and erasing time of non-volatile memory module 106 to decide a positive integer n according to making carbon copies.Memory management circuitry 202 can, after the first data 420 are often write to n entity sequencing unit, just check in the first scratching area 510 and the second scratching area 520 whether have the entity erase unit that need to be wiped free of.For instance, if it is 20ms that duplicative non-volatile memory module 106 is wiped a required time of entity erase unit, and it is 4ms that duplicative non-volatile memory module 106 writes to a required time of entity sequencing unit by data, these memory management circuitry 202 these positive integer n of meeting setting are 5 or 5 multiple.
Fig. 6 A and Fig. 6 B are the process flow diagrams that an exemplary embodiment explanation writes the first data.
Please refer to Fig. 6 A, what memory management circuitry 202 can receive that an indication writes the first data 420 writes instruction (step S602), and extracts a 3rd entity erase unit (step S604) from idle district 404.Memory management circuitry 202 can judge whether this 3rd entity erase unit belongs to storage unit 210 (step S606).If this 3rd entity erase unit is to belong to storage unit 210, memory management circuitry 202 can a parameter x of setting be positive integer n (step S608).Next, in step S610, memory management circuitry 202 can judge whether the second scratching area 520 has entity erase unit and the parameter x that need to be wiped free of whether to equal positive integer n.If the result of step S610 is yes, memory management circuitry 202 can be wiped the entity erase unit (step S612) in the second scratching area 520, and setting variable x is 0 (step S614).In step S616, memory management circuitry 202 can write to an entity sequencing unit in the 3rd entity erase unit by the first data 420, and parameter x is added to 1.In step S618, memory management circuitry 202 can judge that this writes instruction and whether is finished.If the result of step S618 is no, memory management circuitry 202 can be got back to step S610.
If the result of step S606 is no, memory management circuitry 202 can setting variable x be n (step S620).In step S622, memory management circuitry 202 can judge whether the first scratching area 510 has entity erase unit and the parameter x that need to be wiped free of whether to equal positive integer n.If the result of step S622 is yes, memory management circuitry 202 can be wiped the entity erase unit (step S624) in the first scratching area 510, and setting variable x is 0 (step S626).In step S628, memory management circuitry 202 can write to an entity sequencing unit in the 3rd entity erase unit by the first data 420, and parameter x is added to 1.In step S630, memory management circuitry 202 can judge that this writes instruction and whether is finished.If the result of step S630 is no, memory management circuitry 202 can be got back to step S622.
Please refer to Fig. 6 B, next, memory management circuitry 202 can check the entity erase unit (step S632) in storage unit 210 and storage unit 220, and judges whether the entity erase unit (step S634) that need to be wiped free of.For example, as shown in Figure 5, if there is no valid data in entity erase unit 212 (0), memory management circuitry 202 can the entity erase unit of judgement entity erase unit 212 (0) for being wiped free of.Yet, if the first data 420 are to write to a plurality of entity erase units, in during writing, also may produce the entity erase unit that a plurality of needs are wiped free of.The present invention is not limited in the entity erase unit of judging in step S634 to be had several.If the result of step S634 is yes, in step S636, memory management circuitry 202 can this entity erase unit that need to be wiped free of of judgement be to correspond to the first scratching area 510 or the second scratching area 520, and judge whether the first scratching area 510 of this correspondence or the second scratching area 520 have expired (that is, its entity erase unit number is more than or equal to a critical value).If the result of step S636 is yes, memory management circuitry 202 can be wiped the entity erase unit that above-mentioned needs are wiped free of, and this entity erase unit is associated to idle district 404 (step S640).If the result of step S636 is no, the entity erase unit that memory management circuitry 202 can need to be wiped free of this is associated to corresponding the first scratching area 510 or the second scratching area 520 (step S638).Finally, in step S642, the entity erase unit (that is the entity erase unit that, step 612 or step S624 wipe) that memory management circuitry 202 can be wiped during writing is associated to idle district 404.
Fig. 7 is the process flow diagram that an exemplary embodiment illustrates method for writing data.
Please refer to Fig. 7, in step S702, configure a plurality of logical addresses to map to entity erase unit at least part of in entity erase unit at least part of in storage unit 210 and storage unit 220.
In step S704, receive the instruction that writes from host computer system, wherein write instruction indication the first data are write to a logical address.
In step S706, in the entity erase unit from storage unit 210 and storage unit 220, obtain a 3rd entity erase unit, and the first data are write to so far the 3rd entity erase unit.
In step S708, judgement the 3rd entity erase unit is to belong to storage unit 210 or storage unit 220.
If the result of step S708 is " storage unit 210 ", in step S710, when the first data are write to the 3rd entity erase unit, an entity erase unit in eraseable memory unit 220.
If the result of step S708 is " storage unit 220 ", in step S712, when the first data are write to the 3rd entity erase unit, an entity erase unit in eraseable memory unit 210.
Yet in Fig. 7, each step has described in detail as above, just repeats no more at this.In Fig. 7, each step can be a plurality of procedure codes by implementation, for example, by a processor (, Memory Controller 104) performed.Or each step can be one or more circuit by implementation in Fig. 7, the present invention does not limit by each step in software or mode implementation Fig. 7 of hardware.In addition, each step of Fig. 7 above-mentioned exemplary embodiment of can arranging in pairs or groups is implemented together, or each step of Fig. 7 also can be implemented separately, and the present invention is also not subject to the limits.
Please refer to back Fig. 2, in this exemplary embodiment, duplicative non-volatile memory module 106 has comprised two storage unit, and the writing speed of one of them storage unit (it can comprise one or more passage) has just been greater than the transmission speed of connector 102.Therefore, carry out to write with the operation of wiping together and can avoid after data are write, memory management circuitry 202 need to be spent more the time again and carry out the operation of wiping.Yet in other exemplary embodiment, duplicative non-volatile memory module 106 also can comprise y storage unit, wherein the writing speed of m storage unit has just been greater than the transmission speed of connector 102.When memory management circuitry 202 writes to one of them of m storage unit by data, can wipe at least one the entity erase unit in all the other y-m storage unit.Above-mentioned y and m are positive integer, and m is less than y, but the present invention does not limit the numerical value of y and m.
The second exemplary embodiment
The second exemplary embodiment and the first exemplary embodiment are similar, at this, difference are only described.In the second exemplary embodiment, memory management circuitry 202, after receiving and writing instruction, can be analyzed this number that writes the entity sequencing unit that instruction will write and whether be more than or equal to positive integer n.
Fig. 8 A and Fig. 8 B are that the second exemplary embodiment illustrates the process flow diagram that writes the first data.
Please refer to Fig. 8 A, in step S602, after memory management circuitry 202 receives and writes instruction, memory management circuitry 202 can be analyzed this and write instruction, and obtain this and write instruction and want to write the first data to t entity sequencing unit, wherein t is positive integer.In step S802, memory management circuitry 202 can judge whether positive integer t is more than or equal to positive integer n.If the result of step S802 is yes, memory management circuitry 202 can continue step S604, and remaining step is identical with Fig. 6 A.If the result of step S802 is no, in step S804, memory management circuitry 202 can be extracted one the 3rd entity erase unit from idle district, and the first data are write to t entity sequencing unit in the 3rd entity erase unit.After step S804, memory management circuitry 202 can be carried out each step in Fig. 8 B, and each step that it is same as Fig. 6 B, just repeats no more at this.
Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.。

Claims (25)

1. a method for writing data, be used for controlling a duplicative non-volatile memory module, wherein this duplicative non-volatile memory module comprises one first storage unit and one second storage unit, this first storage unit comprises a plurality of first instance erase units, and this second storage unit comprises a plurality of second instance erase units, it is characterized in that, this method for writing data comprises:
Configure a plurality of logical addresses to map to those at least part of first instance erase units and those at least part of second instance erase units;
Reception writes instruction from one of a host computer system, and wherein this writes instruction indication one first data are write to one first logical address in those logical addresses;
From those first instance erase units and those second instance erase units, obtain one the 3rd entity erase unit, and these first data are write to the 3rd entity erase unit;
Judge that the 3rd entity erase unit is to belong to this first storage unit or this second storage unit; And
If the 3rd entity erase unit belongs to this first storage unit, when these first data are write to the 3rd entity erase unit, wipe one of them of those second instance erase units.
2. method for writing data according to claim 1, is characterized in that, also comprises:
If the 3rd entity erase unit belongs to this second storage unit, when these first data are write to the 3rd entity erase unit, wipe one of them of those first instance erase units.
3. method for writing data according to claim 2, is characterized in that, also comprises:
Those first instance erase units and those second instance erase units are at least divided into a data field and an idle district, and wherein these those at least part of first instance erase units and this those at least part of second instance erase units belong to this data field; And
One first scratching area and one second scratching area are set,
Wherein the 3rd entity erase unit belongs to this idle district, and one of them belongs to this first scratching area this of those first instance erase units, and those second instance erase units this one of them belong to this second scratching area.
4. method for writing data according to claim 3, it is characterized in that, this first logical address is one the 4th entity erase unit mapping among those first instance erase units and those second instance erase units, after these first data are write to the step of the 3rd entity erase unit, this method for writing data also comprises:
Judge whether the 4th entity erase unit needs to be wiped free of;
If the 4th entity erase unit need to be wiped free of, judge whether an entity erase unit number of this first scratching area or this second scratching area is more than or equal to a critical value;
If this entity erase unit number of this first scratching area and this second scratching area is less than this critical value, the 4th entity erase unit is associated to this first scratching area or this second scratching area.
5. method for writing data according to claim 4, is characterized in that, also comprises:
If this entity erase unit number of this first scratching area or this second scratching area is more than or equal to this critical value, wipes the 4th entity erase unit, and the 4th entity erase unit is associated to this idle district.
6. method for writing data according to claim 3, is characterized in that, also comprises:
By those first instance erase units this one of them or those second instance erase units this one of them be associated to this idle district.
7. method for writing data according to claim 3, it is characterized in that, after these first data are written into the 3rd entity erase unit, this first scratching area comprises a plurality of first instance erase units that have been wiped free of, and this second scratching area comprises a plurality of second instance erase units that have been wiped free of, and this method for writing data also comprises:
One of them of one of them of the first instance erase unit alternately those being wiped free of and the second instance erase unit that those have been wiped free of is associated to this idle district.
8. method for writing data according to claim 3, it is characterized in that, each those first instance erase unit comprises a plurality of entity sequencing unit, and each those second instance erase unit comprises a plurality of entity sequencing unit, and this method for writing data also comprises:
According to a writing speed of this duplicative non-volatile memory module and an erasing time, determine a positive integer n;
When these first data are write to n entity sequencing unit of those entity sequencing unit in the 3rd entity erase unit, check in this first scratching area or this second scratching area whether have the entity erase unit that need to be wiped free of; And
If while having the entity erase unit that need to be wiped free of in this first scratching area or this second scratching area, wipe described in execution those second instance erase units this one of them step or described in wipe those first instance erase units this one of them step.
9. method for writing data according to claim 3, it is characterized in that, each those first instance erase unit comprises a plurality of entity sequencing unit, each those second instance erase unit comprises a plurality of entity sequencing unit, and from this, write instruction acquisition indication and write t entity sequencing unit, wherein t is positive integer, and this method for writing data also comprises:
According to a writing speed of this duplicative non-volatile memory module and an erasing time, determine a positive integer n;
Judge whether this positive integer t is more than or equal to this positive integer n;
If this positive integer t is less than this positive integer n, these first data are write to the 3rd entity erase unit;
If this positive integer t is more than or equal to this positive integer n, described in execution, obtain the step of the 3rd entity erase unit, the described step that these first data is write to the 3rd entity erase unit, and described judgement the 3rd entity erase unit is to belong to this first storage unit or the step of this second storage unit.
10. method for writing data according to claim 1, is characterized in that, those logical addresses are to map to alternately one of them of those first instance erase units and one of them of those second instance erase units.
11. 1 kinds of memorizer memory devices, is characterized in that, comprising:
A connector, in order to be electrically connected to a host computer system;
One duplicative non-volatile memory module, comprises one first storage unit and one second storage unit, and wherein this first storage unit comprises a plurality of first instance erase units, and this second storage unit comprises a plurality of second instance erase units; And
One Memory Controller, is electrically connected to this connector and this duplicative non-volatile memory module, in order to configure a plurality of logical addresses to map to those at least part of first instance erase units and those at least part of second instance erase units,
Wherein, this Memory Controller writes instruction in order to receive from one of this host computer system, and wherein this writes instruction indication one first data are write to one first logical address in those logical addresses,
Wherein, this Memory Controller is in order to obtain one the 3rd entity erase unit from those first instance erase units and those second instance erase units, and these first data are write to the 3rd entity erase unit,
Wherein, this Memory Controller is in order to judge that the 3rd entity erase unit is to belong to this first storage unit or this second storage unit,
If the 3rd entity erase unit belongs to this first storage unit, this Memory Controller, in order to when these first data are write to the 3rd entity erase unit, is wiped one of them of those second instance erase units.
12. memorizer memory devices according to claim 11, it is characterized in that, if the 3rd entity erase unit belongs to this second storage unit, this Memory Controller, in order to when these first data are write to the 3rd entity erase unit, is wiped one of them of those first instance erase units.
13. memorizer memory devices according to claim 12, it is characterized in that, this Memory Controller is also in order to be at least divided into a data field and an idle district by those first instance erase units and those second instance erase units, wherein these those at least part of first instance erase units and this those at least part of second instance erase units belong to this data field
Wherein, this Memory Controller is also in order to arrange one first scratching area and one second scratching area, wherein the 3rd entity erase unit belongs to this idle district, one of them belongs to this first scratching area this of those first instance erase units, and those second instance erase units this one of them belong to this second scratching area.
14. memorizer memory devices according to claim 13, it is characterized in that, this first logical address is one the 4th entity erase unit mapping among those first instance erase units and those second instance erase units, after these first data are write to the 3rd entity erase unit, this Memory Controller is also in order to judge whether the 4th entity erase unit needs to be wiped free of
If the 4th entity erase unit need to be wiped free of, this Memory Controller is also in order to judge whether an entity erase unit number of this first scratching area or this second scratching area is more than or equal to a critical value,
If this entity erase unit number of this first scratching area and this second scratching area is less than this critical value, this Memory Controller is in order to be associated to the 4th entity erase unit this first scratching area or this second scratching area.
15. memorizer memory devices according to claim 14, it is characterized in that, if this entity erase unit number of this first scratching area or this second scratching area is more than or equal to this critical value, this Memory Controller is in order to wipe the 4th entity erase unit, and the 4th entity erase unit is associated to this idle district.
16. memorizer memory devices according to claim 13, is characterized in that, this Memory Controller also in order to by those first instance erase units this one of them or those second instance erase units this one of them be associated to this idle district.
17. memorizer memory devices according to claim 13, it is characterized in that, after these first data are written into the 3rd entity erase unit, this first scratching area comprises a plurality of first instance erase units that have been wiped free of, and this second scratching area comprises a plurality of second instance erase units that have been wiped free of, this Memory Controller is also associated to this idle district in order to one of them of the first instance erase unit that alternately those has been wiped free of and one of them of second instance erase unit that those have been wiped free of.
18. memorizer memory devices according to claim 13, it is characterized in that, each those first instance erase unit comprises a plurality of entity sequencing unit, each those second instance erase unit comprises a plurality of entity sequencing unit, and this Memory Controller is also in order to determine a positive integer n according to a writing speed of this duplicative non-volatile memory module and an erasing time
Wherein, this Memory Controller is during also in order to n entity sequencing unit of those entity sequencing unit in these first data are write to the 3rd entity erase unit, check in this first scratching area or this second scratching area and whether have the entity erase unit that need to be wiped free of
If while having the entity erase unit that need to be wiped free of in this first scratching area or this second scratching area, this Memory Controller in order to wipe described in carrying out those second instance erase units this one of them operation or described in wipe those first instance erase units this one of them operation.
19. 1 kinds of Memory Controllers, for controlling a duplicative non-volatile memory module, is characterized in that, this Memory Controller comprises:
One host interface, in order to be electrically connected to a host computer system;
One memory interface, in order to be electrically connected to this duplicative non-volatile memory module, wherein this duplicative non-volatile memory module comprises one first storage unit and one second storage unit, wherein this first storage unit comprises a plurality of first instance erase units, and this second storage unit comprises a plurality of second instance erase units; And
One memory management circuitry, is electrically connected to this host interface and this memory interface, in order to configure a plurality of logical addresses to map to those at least part of first instance erase units and those at least part of second instance erase units,
Wherein, this memory management circuitry writes instruction in order to receive from one of this host computer system, and wherein this writes instruction indication one first data are write to one first logical address in those logical addresses,
Wherein, this memory management circuitry is in order to obtain one the 3rd entity erase unit from those first instance erase units and those second instance erase units, and these first data are write to the 3rd entity erase unit,
Wherein, this memory management circuitry is in order to judge that the 3rd entity erase unit is to belong to this first storage unit or this second storage unit,
If the 3rd entity erase unit belongs to this first storage unit, this memory management circuitry, in order to when these first data are write to the 3rd entity erase unit, is wiped one of them of those second instance erase units.
20. Memory Controllers according to claim 19, it is characterized in that, if the 3rd entity erase unit belongs to this second storage unit, this memory management circuitry, in order to when these first data are write to the 3rd entity erase unit, is wiped one of them of those first instance erase units.
21. Memory Controllers according to claim 20, it is characterized in that, this memory management circuitry is also in order to be at least divided into a data field and an idle district by those first instance erase units and those second instance erase units, wherein these those at least part of first instance erase units and this those at least part of second instance erase units belong to this data field
Wherein, this memory management circuitry is also in order to arrange one first scratching area and one second scratching area, wherein the 3rd entity erase unit belongs to this idle district, one of them belongs to this first scratching area this of those first instance erase units, and those second instance erase units this one of them belong to this second scratching area.
22. Memory Controllers according to claim 21, it is characterized in that, this first logical address is one the 4th entity erase unit mapping among those first instance erase units and those second instance erase units, after these first data are write to the 3rd entity erase unit, this memory management circuitry is also in order to judge whether the 4th entity erase unit needs to be wiped free of
If the 4th entity erase unit need to be wiped free of, this memory management circuitry is also in order to judge whether an entity erase unit number of this first scratching area or this second scratching area is more than or equal to a critical value,
If this entity erase unit number of this first scratching area and this second scratching area is less than this critical value, this memory management circuitry is in order to be associated to the 4th entity erase unit one of them of this first scratching area and this second scratching area.
23. Memory Controllers according to claim 22, it is characterized in that, if this entity erase unit number of this first scratching area or this second scratching area is more than or equal to this critical value, this memory management circuitry is in order to wipe the 4th entity erase unit, and by associated this idle district of the 4th entity erase unit.
24. Memory Controllers according to claim 21, it is characterized in that, after these first data are written into the 3rd entity erase unit, this first scratching area comprises a plurality of first instance erase units that have been wiped free of, and this second scratching area comprises a plurality of second instance erase units that have been wiped free of, this memory management circuitry is also associated to this idle district in order to one of them of the first instance erase unit that alternately those has been wiped free of and one of them of second instance erase unit that those have been wiped free of.
25. Memory Controllers according to claim 21, it is characterized in that, each those first instance erase unit comprises a plurality of entity sequencing unit, each those second instance erase unit comprises a plurality of entity sequencing unit, and this memory management circuitry is also in order to determine a positive integer n according to a writing speed of this duplicative non-volatile memory module and an erasing time
Wherein, this memory management circuitry is during also in order to n entity sequencing unit of those entity sequencing unit in these first data are write to the 3rd entity erase unit, check in this first scratching area or this second scratching area and whether have the entity erase unit that need to be wiped free of
If while having the entity erase unit that need to be wiped free of in this first scratching area or this second scratching area, this memory management circuitry in order to wipe described in carrying out those second instance erase units this one of them operation or described in wipe those first instance erase units this one of them operation.
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