CN103984635B - Method for writing data, Memory Controller and memorizer memory devices - Google Patents

Method for writing data, Memory Controller and memorizer memory devices Download PDF

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Publication number
CN103984635B
CN103984635B CN201310050783.XA CN201310050783A CN103984635B CN 103984635 B CN103984635 B CN 103984635B CN 201310050783 A CN201310050783 A CN 201310050783A CN 103984635 B CN103984635 B CN 103984635B
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entity
unit
erasing unit
erasing
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CN103984635A (en
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黄意翔
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The present invention provides a kind of method for writing data, Memory Controller and memorizer memory devices.The method is used to control reproducible nonvolatile memorizer module, and it includes two memory cell.The method includes：Multiple logical addresses are configured to map at least part of entity erasing unit in above-mentioned two memory cell；The write instruction from host computer system is received, its instruction is write data into an above-mentioned logical address；The entity that this data is write into above-mentioned two memory cell wipes unit；Judge this entity erasing unit is which memory cell belonged to；And if this entity erasing unit belongs to one of memory cell, when writing data into, wiping the entity erasing unit in another memory cell.It is thus possible to increase host computer system writes data to the speed of memorizer memory devices.

Description

Method for writing data, Memory Controller and memorizer memory devices
Technical field
The invention relates to a kind of method for writing data, and it is non-volatile for duplicative in particular to one kind Method for writing data, Memory Controller and the memorizer memory devices of memory module.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage The demand of media also rapidly increases.Because reproducible nonvolatile memorizer module (for example, flash memory) has data Non-volatile, power saving, small volume, and without characteristics such as mechanical structures, so being especially suitable for being built in above-mentioned illustrated various In portable multimedia device.
In general, reproducible nonvolatile memorizer module can be electrically connected to a master by a coffret Machine system.Host computer system can be write data into by this coffret to reproducible nonvolatile memorizer module.Also, can Multiple passages can be included in manifolding formula non-volatile memory module, so as to increase in reproducible nonvolatile memorizer module Write the speed of data.However, when the speed that data are write in reproducible nonvolatile memorizer module has been above transmission The transmission speed of interface, then main frame write-in data speed just can only be decided by the transmission speed of coffret.Therefore, how The speed that main frame writes data is further added by the case of this, is this art personnel topic of concern.
The content of the invention
Exemplary embodiment of the present invention proposes a kind of method for writing data, Memory Controller and memorizer memory devices, can To increase the speed that host computer system writes data to memorizer memory devices.
An exemplary embodiment of the invention proposes a kind of method for writing data, for controlling a duplicative non-volatile memories Device module.This reproducible nonvolatile memorizer module includes first memory cell and second memory cell, the One memory cell includes multiple first instances and wipes unit, and the second memory cell includes multiple second instances and wipes unit. This method for writing data includes：Multiple logical addresses are configured to map at least part of first instance erasing unit and at least portion The second instance erasing unit divided；The write instruction from a host computer system is received, wherein write instruction is indicated the first number According to write-in to first logical address；It is real with obtaining one the 3rd in second instance erasing unit from first instance erasing unit Body wipes unit, and writes first data into the 3rd entity erasing unit；Judge that the 3rd entity erasing unit belongs to first Memory cell or the second memory cell；And if the 3rd entity erasing unit belongs to the first memory cell, and the first data are write When entering to the 3rd entity erasing unit, one of erasing second instance erasing unit.
In an exemplary embodiment, above-mentioned method for writing data also includes：If the 3rd entity erasing unit belongs to second Memory cell, when writing first data into the 3rd entity erasing unit, one of erasing first instance erasing unit.
In an exemplary embodiment, above-mentioned method for writing data also includes：First instance is wiped into unit and second in fact Body erasing unit is at least divided into a data field and an idle area, wherein above-mentioned at least part of first instance erasing unit with it is upper It is to belong to data field to state at least part of second instance erasing unit；And first scratching area and one second erasing are set Area.Above-mentioned the 3rd entity erasing unit is to belong to idle area, and the first instance erasing unit being wiped free of is to belong to the first erasing Area, and the second instance erasing unit being wiped free of is to belong to the second scratching area.
In an exemplary embodiment, the first above-mentioned logical address is to map to first instance erasing unit and second instance Wipe unit in the 4th entity erasing unit, write first data into the 3rd entity wipe unit the step of it Afterwards, this method for writing data also includes：Judge whether the 4th entity erasing unit needs to be wiped free of；If the 4th entity wipes unit Need to be wiped free of, judge whether the entity erasing unit number of the first scratching area or the second scratching area is critical more than or equal to one Value；If the entity erasing unit number of the first scratching area and the second scratching area is less than critical value, the 4th entity erasing unit is closed It is coupled to corresponding the first scratching area or the second scratching area.
In an exemplary embodiment, above-mentioned method for writing data also includes：If the first scratching area or the second scratching area Entity erasing unit number is more than or equal to critical value, erasing the 4th entity erasing unit, and the 4th entity erasing unit is closed It is coupled to idle area.
In an exemplary embodiment, above-mentioned method for writing data also includes：The first instance being wiped free of is wiped into unit Or the second instance erasing unit being wiped free of is associated to idle area.
In an exemplary embodiment, it is written into the first data to the 3rd entity erasing unit, the first above-mentioned wiping Units are wiped except area includes multiple first instances being wiped free of, and the second scratching area includes multiple the second realities being wiped free of Body wipes unit.This method for writing data also includes：A first instance being wiped free of alternately is wiped into unit and one The second instance erasing unit being wiped free of is associated to idle area.
In an exemplary embodiment, above-mentioned each first instance erasing unit includes multiple entity program units, And each second instance erasing unit includes multiple entity program units.This method for writing data also includes：According to can One writing speed of manifolding formula non-volatile memory module and an erasing time determine a positive integer n；Write first data into Whether into the 3rd entity erasing unit after n entity program unit, checking to have in the first scratching area or the second scratching area needs The entity to be wiped free of erasing unit；And if the entity erasing in need being wiped free of is single in the first scratching area or the second scratching area Member, the step of performing one of described erasing second instance erasing unit or erasing first instance erasing unit One of them the step of.
In an exemplary embodiment, above-mentioned logical address be alternately map to first instance erasing unit wherein it One wipes one of unit with second instance.
For another angle, an exemplary embodiment of the invention proposes a kind of memorizer memory devices, including connection Device, reproducible nonvolatile memorizer module and Memory Controller.Connector is to be electrically connected to a host computer system. Reproducible nonvolatile memorizer module includes first memory cell and second memory cell, wherein the first storage Unit includes multiple first instances and wipes unit, and the second memory cell includes multiple second instances and wipes unit.Memory Controller is electrically connected to connector and reproducible nonvolatile memorizer module, to configure multiple logical addresses to reflect It is incident upon at least part of first instance erasing unit and wipes unit with least part of second instance.Memory Controller is also used to A write instruction from host computer system is received, this write instruction indicates to write first data into one first logically Location.Memory Controller is also used to wipe with obtaining the 3rd entity in second instance erasing unit from first instance erasing unit Except unit, and write first data into the 3rd entity erasing unit.Memory Controller is also to judge that the 3rd entity is wiped Except unit is to belong to the first memory cell or the second memory cell.If the 3rd entity erasing unit is to belong to the first storage list Member, Memory Controller is used to when writing first data into the 3rd entity erasing unit, erasing second instance erasing unit One of.
In an exemplary embodiment, if the 3rd entity erasing unit belongs to the second memory cell, Memory Controller is used to When writing first data into the 3rd entity erasing unit, one of erasing first instance erasing unit.
In an exemplary embodiment, above-mentioned Memory Controller by first instance also to wipe unit and second instance Erasing unit is at least divided into a data field and an idle area, wherein above-mentioned at least part of first instance erasing unit with it is above-mentioned At least part of second instance erasing unit is to belong to data field.Memory Controller also to set first scratching area with One the second scratching area.Above-mentioned the 3rd entity erasing unit is to belong to idle area, and the first instance erasing unit being wiped free of is Belong to the first scratching area, and the second instance erasing unit being wiped free of is to belong to the second scratching area.
In an exemplary embodiment, the first above-mentioned logical address is to map to first instance erasing unit and second instance Wipe the 4th entity erasing unit in unit.Writing first data into the 3rd entity erasing unit, storage Device controller is also to judge whether the 4th entity erasing unit needs to be wiped free of.If the 4th entity erasing unit needs to be wiped Remove, Memory Controller is to judge that an entity of the first scratching area or the second scratching area wipes whether unit number is more than or equal to One critical value.If the entity erasing unit number of the first scratching area and the second scratching area is less than critical value, Memory Controller is used So that the 4th entity erasing unit is associated to corresponding the first scratching area or the second scratching area.
In an exemplary embodiment, face if the entity erasing unit number of the first scratching area or the second scratching area is more than or equal to Dividing value, Memory Controller is associated to idle area to wipe the 4th entity erasing unit, and by the 4th entity erasing unit.
In an exemplary embodiment, above-mentioned Memory Controller also to by the first instance being wiped free of wipe unit or It is that the second instance erasing unit being wiped free of is associated to idle area.
In an exemplary embodiment, it is written into the first data to the 3rd entity erasing unit, the first scratching area bag Multiple first instance erasing units being wiped free of are included, and the second scratching area includes multiple second instance erasings being wiped free of Unit.Memory Controller by the first instance being wiped free of also alternately to wipe one of unit with being wiped free of Second instance erasing one of unit association to idle area.
In an exemplary embodiment, above-mentioned each first instance erasing unit includes multiple entity program units, often One second instance erasing unit includes multiple entity program units.Memory Controller is also used to non-easily according to duplicative One writing speed of the property lost memory module and an erasing time determine a positive integer n.Memory Controller is also used to by the One data write after n entity program unit, checks the first scratching area or the second scratching area into the 3rd entity erasing unit In whether it is in need be wiped free of entity erasing unit.If the entity in need being wiped free of in the first scratching area or the second scratching area Wipe unit, Memory Controller is to perform the operation of erasing second instance erasing one of the unit or described Wipe the operation of one of first instance erasing unit.
For another angle, an exemplary embodiment of the invention proposes a kind of Memory Controller, for controlling one Reproducible nonvolatile memorizer module.This Memory Controller includes HPI, memory interface and memory management Circuit.HPI is to be electrically connected to a host computer system.Memory interface is that to be electrically connected to duplicative non- Volatile.Reproducible nonvolatile memorizer module includes first memory cell and one second storage Unit, wherein the first memory cell, which includes multiple first instances, wipes unit, and the second memory cell includes multiple second in fact Body wipes unit.Memory management circuitry is electrically connected to HPI and memory interface, to configure it is multiple logically Unit is wiped with least part of second instance in location to map at least part of first instance erasing unit.Memory management electricity Road is also to receive a write instruction from host computer system, and this write instruction indicates to write first data into one first Logical address.Memory management circuitry is also used to obtain one the from first instance erasing unit and second instance erasing unit Three entities wipe unit, and write first data into the 3rd entity erasing unit.Memory management circuitry is also to judge 3rd entity erasing unit is to belong to the first memory cell or the second memory cell.If the 3rd entity erasing unit is to belong to the One memory cell, memory management circuitry is used to when writing first data into the 3rd entity erasing unit, and erasing second is real One of body erasing unit.
In an exemplary embodiment, if the 3rd entity erasing unit belongs to the second memory cell, memory management circuitry is used So that when writing first data into the 3rd entity erasing unit, erasing first instance wipes one of unit.
In an exemplary embodiment, above-mentioned memory management circuitry by first instance also to wipe unit and second in fact Body erasing unit is at least divided into a data field and an idle area, wherein above-mentioned at least part of first instance erasing unit with it is upper It is to belong to data field to state at least part of second instance erasing unit.Memory management circuitry is also to set one first erasing Area and second scratching area.Above-mentioned the 3rd entity erasing unit is to belong to idle area, and the first instance erasing being wiped free of is single Member is to belong to the first scratching area, and the second instance erasing unit being wiped free of is to belong to the second scratching area.
In an exemplary embodiment, the first above-mentioned logical address is to map to first instance erasing unit and second instance Wipe the 4th entity erasing unit in unit.Writing first data into the 3rd entity erasing unit, storage Device management circuit is also to judge whether the 4th entity erasing unit needs to be wiped free of.If the 4th entity erasing unit needs to be wiped Remove, memory management circuitry is to judge whether the entity erasing unit number of the first scratching area or the second scratching area is more than In a critical value.If the entity erasing unit number of the first scratching area and the second scratching area is less than critical value, memory management electricity Road is the 4th entity erasing unit is associated to corresponding the first scratching area or the second scratching area.
In an exemplary embodiment, face if the entity erasing unit number of the first scratching area or the second scratching area is more than or equal to Dividing value, memory management circuitry is associated to idle to wipe the 4th entity erasing unit, and by the 4th entity erasing unit Area.
In an exemplary embodiment, above-mentioned memory management circuitry by the first instance being wiped free of also to wipe unit Or the second instance erasing unit being wiped free of is associated to idle area.
In an exemplary embodiment, it is written into the first data to the 3rd entity erasing unit, the first scratching area bag Multiple first instance erasing units being wiped free of are included, and the second scratching area includes multiple second instance erasings being wiped free of Unit.Memory management circuitry by the first instance being wiped free of also alternately to wipe one of unit with being wiped One of second instance erasing unit removed is associated to idle area.
In an exemplary embodiment, above-mentioned each first instance erasing unit includes multiple entity program units, often One second instance erasing unit includes multiple entity program units.Memory management circuitry is also used to non-according to duplicative One writing speed of volatile and an erasing time determine a positive integer n.Memory management circuitry is also used to Write first data into and after n entity program unit, check the first scratching area or the second wiping into the 3rd entity erasing unit Except whether the entity in need being wiped free of wipes unit in area.If in need in the first scratching area or the second scratching area be wiped free of Entity wipes unit, memory management circuitry to perform erasing second instance erasing one of the unit operation or It is the operation of one of the erasing first instance erasing unit.
Based on above-mentioned, method for writing data, memorizer memory devices and memory that exemplary embodiment of the present invention is proposed Controller, the operation of write-in and erasing can be performed simultaneously, write data into so as to increase host computer system to memory storage dress The speed put.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make Carefully it is described as follows.
Brief description of the drawings
Figure 1A is the schematic block diagram of host computer system shown by an exemplary embodiment and memorizer memory devices；
Figure 1B is the schematic diagram of computer shown by an exemplary embodiment, input/output device and memorizer memory devices；
Fig. 1 C are the schematic diagrames of host computer system shown by an exemplary embodiment and memorizer memory devices；
Fig. 2 is the schematic block diagram for showing the memorizer memory devices shown in Figure 1A；
Fig. 3 is the schematic block diagram of the Memory Controller shown by an exemplary embodiment；
Fig. 4 is the example schematic of the management reproducible nonvolatile memorizer module shown by an exemplary embodiment；
Fig. 5 is the schematic diagram that an exemplary embodiment shows the first scratching area and the second scratching area；
Fig. 6 A and Fig. 6 B are the flow charts that an exemplary embodiment illustrates to write the first data；
Fig. 7 is the flow chart that an exemplary embodiment shows method for writing data；
Fig. 8 A and Fig. 8 B are that the second exemplary embodiment shows to write the flow chart of the first data.
Description of reference numerals：
1000：Host computer system；
1100：Computer；
1102：Microprocessor；
1104：Random access memory；
1106：Input/output device；
1108：System bus；
1110：Data transmission interface；
1202：Mouse；
1204：Keyboard；
1206：Display；
1208：Printer；
1212：Portable disk；
1214：Storage card；
1216：Solid state hard disc；
1310：Digital camera；
1312：SD card；
1314：Mmc card；
1316：Memory stick；
1318：CF cards；
1320：Embedded storage device；
100：Memorizer memory devices；
102：Connector；
104：Memory Controller；
106：Reproducible nonvolatile memorizer module；
210、220：Memory cell；
212 (0)~212 (A), 222 (0)~222 (B)：Entity wipes unit；
202：Memory management circuitry；
204：HPI；
206：Memory interface；
252：Buffer storage；
254：Electric power management circuit；
256：Error checking and correcting circuit；
402：Data field；
404：Idle area；
406：System area；
408：Replace area；
410 (0)~410 (I)：Logical address；
420：First data；
510：First scratching area；
520：Second scratching area；
S602、S604、S606、S608、S610、S612、S614、S616、S618、S620、S622、S624、S626、 S628、S630、S632、S634、S636、S638、S640、S642、S702、S704、S706、S708、S710、S712、S802、 S804：Step.
Embodiment
In general, memorizer memory devices (also referred to as, memory storage system) include duplicative non-volatile memories Device module and controller (also referred to as, controlling circuit).Being commonly stored device storage device is used together with host computer system, so that main frame System can write data into memorizer memory devices or be read from memorizer memory devices data.
Figure 1A is the schematic block diagram of host computer system shown by an exemplary embodiment and memorizer memory devices.
Figure 1B is the schematic diagram of computer shown by an exemplary embodiment, input/output device and memorizer memory devices.
Fig. 1 C are the schematic diagrames of host computer system shown by an exemplary embodiment and memorizer memory devices.
Figure 1A is refer to, host computer system 1000 generally comprises computer 1100 and input/output (input/output, I/O) Device 1106.Computer 1100 includes microprocessor 1102, random access memory (random access memory, RAM) 1104th, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes mouse 1202, the key such as Figure 1B Disk 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Figure 1B 1106, input/output device 1106 can also include other devices.
In embodiments of the present invention, memorizer memory devices 100 are by data transmission interface 1110 and host computer system 1000 other elements are electrically connected with.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106 Running can write data into memorizer memory devices 100 or read data from memorizer memory devices 100.For example, depositing Reservoir storage device 100 can be portable disk 1212, storage card 1214 or solid state hard disc (Solid State as shown in Figure 1B Drive, SSD) 1216 grades type nonvolatile storage device.
In general, host computer system 1000 is that substantially can coordinate to store appointing for data with memorizer memory devices 100 Meaning system.Although in this exemplary embodiment, host computer system 1000 is explained with computer system, however, of the invention another Host computer system 1000 can be digital camera, video camera, communicator, music player or video playback in one exemplary embodiment The systems such as device.For example, when host computer system is digital camera (video camera) 1310, type nonvolatile storage dress Put is then its used SD card 1312, mmc card 1314, memory stick (memory stick) 1316, CF cards 1318 or embedded Storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 include embedded multi-media card (Embedded MMC, eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 is the schematic block diagram for showing the memorizer memory devices shown in Figure 1A.
Fig. 2 is refer to, it is non-that memorizer memory devices 100 include connector 102, Memory Controller 104 and duplicative Volatile 106.
In this exemplary embodiment, connector 102 is to be compatible to high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard.However, it is necessary to be appreciated that, the present invention is not limited In this, connector 102 can also be meet the advanced annex of sequence (Serial Advanced Technology Attachment, SATA) standard, side by side advanced annex (Parallel Advanced Technology Attachment, PATA) standard, electrically With Electronic Engineering Association (Ins t i tute of Electrical and Electronic Engineers, IEEE) 1394 standards, USB (Universal Serial Bus, USB) standard, secure digital (Secure Digital, SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) interface standard, ultrahigh speed two generations (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, built-in multimedia memory card (Embedded Multimedia Card, EMMC) interface standard, general flash memory (Universal Flash Storage, UPS) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other suitable standards.
Memory Controller 104 is to perform multiple logic gates with hardware pattern or firmware pattern implementation or control to refer to Order, and according to the instruction of host computer system 1000 carried out in reproducible nonvolatile memorizer module 106 data write-in, The running such as reading and erasing.
Reproducible nonvolatile memorizer module 106 is electrically connected to Memory Controller 104, and to store The data that host computer system 1000 is write.Reproducible nonvolatile memorizer module 106 includes memory cell 210 (also referred to as the One memory cell) and memory cell 220 (also referred to as the second memory cell).Memory cell 210 includes entity erasing unit 212 (0) ~212 (A) (also referred to as first instance erasing unit), and memory cell 220 include entity erasing unit 222 (0)~222 (B) ( Claim second instance erasing unit).Memory cell 210 can independently perform the behaviour of reading, write-in and erasing with memory cell 220 Make.For example, memory cell 210 is to be electrically connected to Memory Controller 104 by least one first passage, and memory cell 220 be to be electrically connected to Memory Controller 104 by least one second channel, and first passage is different from second and led to Road.Or, memory cell 210 is controlled by least one first enable signal (also referred to as CE signals), and memory cell 220 is Controlled by least one second enable signal, and the first enable signal is different from the second enable signal.In other words, store Unit 210 is when performing the operation of reading, write-in or erasing, and memory cell 220 can also perform the behaviour of reading, write-in or erasing Make.Also, the operation performed by memory cell 210 can be differently configured to the operation performed by memory cell 220.On the other hand, Memory cell 210 and memory cell 220 may belong to different memory crystal grains (die), or belong to identical memory crystal grain, It is of the invention and not subject to the limits.
Each entity erasing unit has a plurality of entity program units respectively, and it is single to belong to same entity erasing The entity program unit of member can be written independently and simultaneously be wiped.For example, each entity erasing unit is by 128 Entity program unit is constituted.However, it is necessary to be appreciated that, the invention is not restricted to this, each entity erasing unit is can be by 64 entity program units, 256 entity program units or other any entity program units are constituted.
Again specifically, entity erasing unit is the least unit of erasing.That is, each entity erasing unit contains minimum The memory cell being wiped free of in the lump of number.Entity program unit is the minimum unit of sequencing.That is, entity program unit is Write the minimum unit of data.Each entity program unit generally includes data bit area and redundancy ratio special zone.Data bit Area includes the data multiple entity access addresses to store user, and redundancy ratio special zone is used to the data (example of stocking system Such as, control signal and error correcting code).In this exemplary embodiment, in the data bit area of each entity program unit Can be comprising 4 entity access addresses, and the size of an entity access address is 512 bit byte, B).However, in other models In example embodiment, 8,16 or the more or less entity access addresses of number, the present invention can be also included in data bit area It is not intended to limit the size and number of entity access address.For example, entity erasing unit is physical blocks, and entity program Unit is that physical page or entity are fanned.
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multistage memory cell (Multi Level Cell, MLC) at least two bit data can be stored in the memory cell of NAND type flash memory module, i.e., one.However, The invention is not restricted to this, reproducible nonvolatile memorizer module 106 may also be single-order memory cell (Single Level Cell, SLC) NAND type flash memory module, Complex Order memory cell (Trinary Level Cell, TLC) NAND quick flashing Memory module, other flash memory modules or other there is the memory module of identical characteristic.
Fig. 3 is the schematic block diagram of the Memory Controller shown by an exemplary embodiment.
Fig. 3 is refer to, Memory Controller 104 includes memory management circuitry 202, HPI 204 and connect with memory Mouth 206.
Memory management circuitry 202 is used to the overall operation of control memory controller 104.Specifically, memory pipe Managing circuit 202 has multiple control instructions, and when memorizer memory devices 100 are operated, this little control instruction can be performed The runnings such as write-in, reading and erasing to carry out data.When describing the operation of memory management circuitry 202 below, it is equal to and retouches The operation of Memory Controller 104 is stated, and is repeated no more.
In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with firmware pattern.For example, Memory management circuitry 202 has microprocessor unit (not shown and read-only storage (not shown), and this little control instruction It is to be programmed in so far read-only storage.When memorizer memory devices 100 are operated, this little control instruction can be by microprocessor list The runnings such as write-in, reading and erasing of the member to perform to carry out data.
In another exemplary embodiment of the invention, the control instruction of memory management circuitry 202 can also procedure code pattern The specific region of reproducible nonvolatile memorizer module 106 is stored in (for example, being exclusively used in storage system in memory module The system area of data) in.In addition, memory management circuitry 202 has microprocessor unit (not shown), read-only storage (not Show) and random access memory (not shown).Particularly, this read-only storage has driving code, and when memory control When device 104 is enabled, microprocessor unit, which can first carry out this driving code section, will be stored in type nonvolatile Control instruction in module 106 is loaded into the random access memory of memory management circuitry 202.Afterwards, microprocessor list The runnings such as the write-in, reading and erasing that member can operate this little control instruction to carry out data.
In addition, in another exemplary embodiment of the invention, the control instruction of memory management circuitry 202 can also a hardware Pattern carrys out implementation.For example, memory management circuitry 202 include microcontroller, MMU, memory write unit, Memory reading unit, memory erasing unit and data processing unit.MMU, memory write unit, deposit Reservoir reading unit, memory erasing unit and data processing unit are electrically connected to microcontroller.Wherein, memory management Unit wipes unit to manage the entity of reproducible nonvolatile memorizer module 106；Memory write unit is to right Reproducible nonvolatile memorizer module 106 assigns write instruction to write data into type nonvolatile In module 106；Memory reading unit is to assign reading instruction to reproducible nonvolatile memorizer module 106 with from can Data are read in manifolding formula non-volatile memory module 106；Memory wipes unit to be deposited to duplicative is non-volatile Memory modules 106 assign erasing instruction to wipe data from reproducible nonvolatile memorizer module 106；And at data Reason unit to handle be intended to write it is to the data of reproducible nonvolatile memorizer module 106 and non-volatile from duplicative The data read in property memory module 106.
HPI 204 is electrically connected to memory management circuitry 202 and to receive and identification host computer system 1000 instructions transmitted and data.That is, the instruction that host computer system 1000 is transmitted can be by HPI with data 204 are sent to memory management circuitry 202.In this exemplary embodiment, HPI 204 is to be compatible to PCI Express Standard.However, it is necessary to be appreciated that the invention is not restricted to this, HPI 204 can also be compatible to SATA standard, PATA marks Standard, IEEE1394 standards, USB standard, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative Property memory module 106.That is, the data for being intended to write to reproducible nonvolatile memorizer module 106 can be by depositing Memory interface 206 is converted to the receptible form of the institute of reproducible nonvolatile memorizer module 106.
In an exemplary embodiment of the invention, Memory Controller 104 also includes buffer storage 252, power management electricity Road 254 and error checking and correcting circuit 256.
Buffer storage 252 is electrically connected to memory management circuitry 202 and is configured to temporarily store come from host computer system 1000 data and the data for instructing or coming from reproducible nonvolatile memorizer module 106.
Electric power management circuit 254 is electrically connected to memory management circuitry 202 and stores dress to control memory Put 100 power supply.
Error checking is electrically connected to memory management circuitry 202 and to perform wrong inspection with correcting circuit 256 Look into correction program to ensure the correctness of data.Specifically, when memory management circuitry 202 connects from host computer system 1000 When receiving write instruction, error checking can produce corresponding mistake for the data of this corresponding write instruction with correcting circuit 256 and examine Look into and correcting code (Error Checking and Correcting Code, ECC Code), and memory management circuitry 202 The data of this corresponding write instruction can be write to type nonvolatile with corresponding error checking and correcting code In module 106.Afterwards, when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106 The corresponding error checking of this data and correcting code can be read simultaneously, and error checking can be according to this mistake with correcting circuit 256 Check and error checking and correction program are performed to the data read with correcting code.
Fig. 4 is the example schematic of the management reproducible nonvolatile memorizer module shown by an exemplary embodiment.
It will be appreciated that the entity for being described herein reproducible nonvolatile memorizer module 106 wipes the fortune of unit When making, with " division ", " extraction ", " association " and etc. word to carry out application entity erasing unit be concept in logic.That is, can answer The physical location for writing the erasing unit of the entity in formula non-volatile memory module 106 is not changed, but pair can be answered in logic The entity erasing unit for writing formula non-volatile memory module 106 is operated.
Fig. 4 is refer to, Memory Controller 104 can wipe the entity of reproducible nonvolatile memorizer module 106 Unit 212 (0)~212 (A), 222 (0)~222 (B) are logically divided into multiple regions, for example, data field 402, idle area 404th, system area 406 and substitution area 408.
The entity erasing unit of data field 402 and idle area 404 is to store the data for coming from host computer system 1000. Specifically, data field 402 is the entity erasing unit for having stored data, and the entity erasing unit in idle area 404 is to be used to The entity erasing unit in replacement data area 402.Therefore, the entity erasing unit in idle area 404 is wiped for empty or workable entity Except unit, i.e. no record data or labeled as invalid data useless.That is, the entity erasing in idle area 404 Unit has been performed erasing running, or when the entity erasing unit in idle area 404 is extracted for before storing data, institute The entity erasing unit of extraction can first be performed erasing running.Therefore, the entity erasing unit in idle area 404 can be used Entity wipes unit.
The entity erasing unit for logically belonging to system area 406 is to be used to record system data, wherein this system data bag Include and wipe unit number, each entity on the manufacturer of memory chip and the entity of model, memory chip and wipe unit Entity program unit number etc..
It is to substitute entity erasing unit to logically belong to replace the entity erasing unit in area 408.For example, duplicative is non- The entity erasing unit that volatile can reserve 4% when dispatching from the factory is used as replacing.That is, working as data field 402nd, when idle area 404 is damaged with the entity erasing unit in system area 406, the entity erasing reserved in substitution area 408 is single Member is to replacing damaged entity erasing unit (that is, bad entity erasing unit (bad block)).Therefore, if substitution area When still having normal entity erasing unit in 408 and occurring entity erasing unit damage, Memory Controller 104 can be from substitution Normal entity erasing unit is extracted in area 408 and wipes unit to change the entity of damage.If replacing in area 408 without normal When entity wipes unit and occurs entity erasing unit damage, then Memory Controller 104 can be by whole memory storage device 100 are declared as write protection (write protect) state, and can not write data again.In another exemplary embodiment, substitution Area 408 also can share the entity comprising invalid data with idle area 404 and wipe unit.
Particularly, the entity in data field 402, idle area 404, system area 406 and substitution area 408 wipes the quantity meeting of unit It is different according to different memory specifications.Further, it is necessary to be appreciated that, in the running of memorizer memory devices 100, The packet relation that entity erasing unit associates to data field 402, idle area 404, system area 406 and substitution area 408 can be dynamically Change.For example, when the entity erasing unit in idle area 404 is damaged and the entity in substituted area 408 wipes unit substitution, then The entity erasing unit in the area 408 of substitution originally can be associated to idle area 404.In this exemplary embodiment, system area 406 is with taking Include memory cell 210 for area 408 and the entity of part in memory cell 220 wipes unit.However, implementing in other examples In example, the entity erasing that system area 406 can be also only included with substitution area 408 in memory cell 210 or memory cell 220 is single Member, it is of the invention and not subject to the limits.
Memory Controller 104 can configure logical address 410 (0)~410 (I) in favor of in the entity erasing of storage data Data access is carried out in unit.For example, when memorizer memory devices 100 by the operating system in host computer system 1000 pass through one When file system (for example, FAT32) is formatted, logical address 410 (0)~410 (I) can respectively map to data field 402 Entity wipes unit.Here, memory management circuitry 202 can set up logical address-entity erasing unit mapping table (logical Address-physical erasing unit mapping table), to record between logical address and entity erasing unit Mapping relations.In this exemplary embodiment, the size of a logical address is same as the size that an entity wipes unit, i.e., Logical address is also referred to as logical block addresses (logical block address, LBA).However, implementing in other examples In example, the size of a logical address can also be the size or other sizes of an entity program unit, and the present invention is not Limit herein.
In this exemplary embodiment, when memory management circuitry 202 configures logical address 410 (0)~410 (I), logic Address 410 (0)~410 (I) are the entity erasing units and memory cell 220 alternately mapped in memory cell 210 In an entity erasing unit.For example, logical address 410 (0) is to map to entity erasing unit 212 (0), logical address 410 (1) are to map to entity erasing unit 222 (0), and logical address 410 (2) is to map to entity erasing unit 212 (1), by that analogy.However, in other exemplary embodiments, memory management circuitry 202 can also be by logical address 410 (0) The entity that~410 (I) are mapped in data field 402 with noninterlace or other modes wipes unit, of the invention and not subject to the limits.
When host computer system 1000 will be write data into memorizer memory devices 100, host computer system 1000 can transmit one Individual write instruction is to memory management circuitry 202, and this write instruction can indicate write data into which logical address. For example, the write instruction that host computer system 1000 is transmitted is to indicate to write the first data 420 to logical address 410 (0) (also referred to as the One logical address).In other words, host computer system 1000 be will more novel entities erasing unit 212 (0) (also referred to as the 4th entity erasing Unit) in data.Memory management circuitry 202 can extract one after this write instruction is received from idle area 404 Entity erasing unit (also referred to as the 3rd entity erasing unit), and the first data 420 are write into so far the 3rd entity erasing unit It is central.Memory management circuitry 202 logical address 410 (0) can also be remapped so far the 3rd entity erasing unit, and will 3rd entity erasing unit is associated to data field 402.Specifically, memory management circuitry 202 can judge that this 3rd entity is wiped Except unit be belong in memory cell 210 entity erasing unit 212 (0)~212 (A) or memory cell 220 in entity Wipe unit 222 (0)~22 (B).If this 3rd entity erasing unit is the entity erasing unit for belonging to memory cell 210 (for example, entity erasing unit 212 (C)), then when the first data 420 are write into so far the 3rd entity erasing unit, memory Manage at least one entity erasing unit in the simultaneously erased memory cell 220 of the meeting of circuit 202.If the erasing of this 3rd entity is single Member is the entity erasing unit (for example, entity erasing unit 222 (D)) for belonging to memory cell 220, then by the first data 420 When writing so far the 3rd entity erasing unit, memory management circuitry 202 understands at least one in simultaneously erased memory cell 210 Entity wipes unit.That is, memory management circuitry 202 writes the first data 420 to memory cell 210 and storage list During member one of 220, at least one entity erasing unit in another simultaneously erased memory cell of meeting.It will lift below One exemplary embodiment is described in detail.
Fig. 5 is the schematic diagram that an exemplary embodiment shows the first scratching area and the second scratching area.
Fig. 5 is refer to, in addition to above-mentioned region, memory management circuitry 202 can also logically set the first erasing The scratching area 520 of area 510 and second.When memorizer memory devices 100 are formatted, the first scratching area 510 and the second scratching area Do not have any entity erasing unit in 520.As the running of memory management circuitry 202 is, it is necessary to be wiped free of but without quilt The entity erasing unit of erasing can be associated in the first scratching area 510 or the second scratching area 520.Specifically, the first erasing The entity erasing unit for belonging to memory cell 210 can be only placed in area 510, and only can place to belong to and deposit in the second scratching area 520 The entity erasing unit of storage unit 220.Also, memory management circuitry 202 can limit the first scratching area 510 and the second scratching area The number of entity erasing unit is no more than a critical value in 520.
For above-mentioned example, the first data 420 are being write to the entity erasing unit in idle area 404, The data of part turn into invalid data in entity erasing unit 212 (0), and memory management circuitry 202 can judge that entity is wiped Whether unit 212 (0), which needs, is wiped free of.For example, wipe data all in unit 212 (0) when entity turns into invalid data, Then memory management circuitry 202 can judge that entity wipes unit 212 (0) and needs to be wiped free of.If entity erasing unit 212 (0) is needed Be wiped free of, then memory management circuitry 202 can judge entity wipe unit 212 (0) correspond to the first scratching area 510 or Second scratching area 520.Here, because entity erasing unit 212 (0) is to belong to memory cell 210, therefore memory management circuitry 202 can judge that entity wipes unit 212 (0) and corresponds to the first scratching area 510.Next, memory management circuitry 202 can be sentenced Whether the entity erasing unit number (that is, the number of entity erasing unit in the first scratching area 510) of disconnected first scratching area 510 is big In equal to above-mentioned critical value.If the entity erasing unit number of the first scratching area 510 is less than the critical value, memory management Circuit 202 can wipe entity unit 212 (0) association to the first scratching area 510.If on the contrary, the entity of the first scratching area 510 Wipe unit number and be more than or equal to the critical value, then memory management circuitry 202 can wipe entity erasing unit 212 (0) and By entity erasing unit 212 (0) association to idle area 404.Similarly, when the entity erasing unit for needing to be wiped free of is (for example, real Body erasing unit 222 (0)) it is that when belonging to the second scratching area 520, memory management circuitry 202 can judge the second scratching area 520 Whether entity erasing unit number is more than or equal to the critical value, so as to determine whether to associate this entity erasing unit to second Scratching area 520.That is, if the entity erasing unit number of the first scratching area 510 and the second scratching area 520 is less than critical value, The first scratching area 510 or the second scratching area 520 can be associated to by needing the entity being wiped free of to wipe unit.If corresponding first wipes , it is necessary to the entity erasing being wiped free of when being more than or equal to critical value except the entity erasing unit number of the scratching area 520 of area 510 or second Unit can be wiped free of and be associated to idle area.
As described above, the first scratching area 510 is wiped free of with needs are placed in the second scratching area 520 but is not wiped free of also Entity erasing unit.Therefore, when memory management circuitry 202 writes the first data 420 to one the 3rd of idle area 404 When entity wipes unit, memory management circuitry 202 is to obtain one from the first scratching area 510 or the second scratching area 520 to want The entity erasing unit being wiped free of.Specifically, if the 3rd entity erasing unit (for example, entity erasing unit 212 (C)) is category In memory cell 210, then memory management circuitry 202 can wipe at least one entity in the second scratching area 520 and wipe unit.Or Person, if the 3rd entity erasing unit (for example, entity erasing unit 222 (D)) is to belong to memory cell 220, memory management Circuit 202 can wipe at least one entity in the first scratching area 510 and wipe unit.
In addition, the first data 420 are being write to the 3rd entity erasing unit after, address period be wiped free of one or Multiple entity erasing units can be stored by management circuit 202 and associate to idle area 404.In an exemplary embodiment, memory Circuit 202 is managed alternately to associate the entity erasing unit that these are wiped free of to idle area after many pen datas are write 404.Specifically, one or more data are being write to the entity erasing unit in idle area, the first scratching area 510 may Can include one or more be wiped free of entities erasing units, and the second scratching area 520 may also include one or more by The entity erasing unit of erasing.Memory management circuitry 202 can from the first scratching area 510 and the second scratching area 520 wherein it One selects the entity being wiped free of an erasing unit, and the entity erasing unit that this has been wiped free of is associated to idle area 404.Next, memory management circuitry 202 can select the entity being wiped free of an erasing unit from another scratching area, And the entity erasing unit that this has been wiped free of is associated to idle area 404.However, in another exemplary embodiment, memory Manage circuit 202 once can also wipe unit when updating system information by the entity being wiped free of in the first scratching area 510 All association wipes the association of unit whole to the spare time to idle area 404 or once by the entity being wiped free of in the second scratching area 520 Put area 404.This time point for updating system information can be that above-mentioned logical address-reality is updated in memory management circuitry 202 Body is wiped the time point of unit mapping table, or updates the time point of other systems information, of the invention and not subject to the limits.
In an exemplary embodiment, memory management circuitry 202 can be non-volatile memory module 106 according to that can make carbon copies A writing speed and an erasing time determine a positive integer n.Memory management circuitry 202 can be by the first data 420 Often write after n entity program unit, just check in the first scratching area 510 and the second scratching area 520 whether quilt in need The entity erasing unit of erasing.For example, if reproducible nonvolatile memorizer module 106 wipes an entity erasing list Member required time is 20ms, and reproducible nonvolatile memorizer module 106 is write data into an entity program Time needed for changing unit is 4ms, then this memory management circuitry 202 can set the multiple that this positive integer n is 5 or 5.
Fig. 6 A and Fig. 6 B are the flow charts that an exemplary embodiment illustrates to write the first data.
Fig. 6 A are refer to, memory management circuitry 202 can receive a write instruction for indicating the first data 420 of write-in (step S602), and extract a 3rd entity erasing unit (step S604) from idle area 404.Memory management circuitry 202 can judge whether this 3rd entity erasing unit belongs to memory cell 210 (step S606).If this 3rd entity wipes unit It is to belong to memory cell 210, then memory management circuitry 202 can set a parameter x as positive integer n (step S608).Connect down Come, in step S610, memory management circuitry 202 can judge that the entity whether in need being wiped free of of the second scratching area 520 is wiped Except whether unit and parameter x are equal to positive integer n.If step S610 result is yes, memory management circuitry 202 can wipe Entity erasing unit (step S612) in two scratching areas 520, and parameter x is set as 0 (step S614).In step In S616, memory management circuitry 202 can write the first data 420 to the 3rd entity the entity program wiped in unit Change unit, and parameter x is added 1.In step S618, whether memory management circuitry 202 can judge this write instruction Through being finished.If step S618 result is no, memory management circuitry 202 can return to step S610.
If step S606 result is no, memory management circuitry 202 can set parameter x as n (step S620).In step In rapid S622, memory management circuitry 202 can judge the entity erasing unit whether in need being wiped free of of the first scratching area 510 simultaneously And whether parameter x is equal to positive integer n.If step S622 result is yes, memory management circuitry 202 can wipe the first scratching area Entity erasing unit (step S624) in 510, and parameter x is set as 0 (step S626).In step S628, deposit Reservoir management circuit 202 can write the first data 420 to the 3rd entity the entity program unit wiped in unit, and And parameter x is added 1.In step S630, memory management circuitry 202 can judge whether this write instruction has been finished. If step S630 result is no, memory management circuitry 202 can return to step S622.
Fig. 6 B are refer to, next, memory management circuitry 202 can be checked in memory cell 210 and memory cell 220 Entity erasing unit (step S632), and judge whether the entity erasing unit (step S634) in need being wiped free of.For example, If as shown in figure 5, without valid data in entity erasing unit 212 (0), memory management circuitry 202 can judge reality The entity erasing unit that body erasing unit 212 (0) is wiped free of for needs.If however, the first data 420 are write to multiple realities Body wipes unit, then may also produce multiple entity erasing units for needing to be wiped free of in address period.The present invention is not intended to limit The entity erasing unit judged in step S634 has several.If step S634 result is yes, in step S636, storage Device management circuit 202 can judge that the entity erasing unit that this needs is wiped free of is that correspondence to the first scratching area 510 or second is wiped Except area 520, and judge this whether full (that is, its entity erasing of corresponding first scratching area, 510 or second scratching area 520 Unit number is more than or equal to a critical value).If step S636 result is yes, memory management circuitry 202 can wipe above-mentioned Need the entity being wiped free of to wipe unit, and this entity erasing unit is associated to idle area 404 (step S640).If step S636 result is no, and the entity erasing unit that this needs can be wiped free of by memory management circuitry 202 is associated to corresponding First scratching area 510 or the second scratching area 520 (step S638).Finally, in step S642, memory management circuitry 202 The entity that address period can be wiped is wiped unit (that is, the entity that step 612 or step S624 are wiped wipes unit) and closed It is coupled to idle area 404.
Fig. 7 is the flow chart that an exemplary embodiment shows method for writing data.
Fig. 7 is refer to, in step S702, configures multiple logical addresses to map in memory cell 210 at least partly Entity erasing unit and memory cell 220 at least part of entity erasing unit.
In step S704, the write instruction from host computer system is received, wherein write instruction indicates to write the first data Enter to a logical address.
In step S706, one the 3rd is obtained from the entity erasing unit in memory cell 210 and memory cell 220 Entity wipes unit, and writes first data into so far the 3rd entity erasing unit.
In step S708, judge that the 3rd entity erasing unit is to belong to memory cell 210 or memory cell 220.
If step S708 result is " memory cell 210 " in step S710, is write first data into the 3rd in fact When body wipes unit, the entity erasing unit in erasing memory cell 220.
If step S708 result is " memory cell 220 " in step S712, is write first data into the 3rd entity When wiping unit, the entity erasing unit in erasing memory cell 210.
However, each step has been described in detail as above in Fig. 7, just repeat no more herein.Each step can be implemented as in Fig. 7 Multiple procedure codes, it is performed by a processor (for example, Memory Controller 104).Or, each step can be by reality in Fig. 7 As one or more circuits, the present invention is not intended to limit each step in mode implementation Fig. 7 with software or hardware.In addition, Fig. 7 is each The step above-mentioned exemplary embodiment that can arrange in pairs or groups is implemented together, or, each steps of Fig. 7 can also individually be implemented, and the present invention is not Limit herein.
Fig. 2 is refer to back, in this exemplary embodiment, reproducible nonvolatile memorizer module 106 includes two Memory cell, and the writing speed of one of memory cell (it may include one or more passages) is just more than connector 102 transmission speed.Therefore, the operation of write-in and erasing is performed together to be avoided after writing data into, memory pipe Reason circuit 202 needs again the operations for taking time to perform erasing more.However, in other exemplary embodiments, duplicative is non-volatile Property memory module 106 may also comprise y memory cell, the writing speed of wherein m memory cell is just more than connector 102 Transmission speed.When memory management circuitry 202 is write data into one of m memory cell, remaining can be wiped At least one entity erasing unit in y-m memory cell.Above-mentioned y and m is positive integer, and m is less than y, but the present invention It is not intended to limit y and m numerical value.
Second exemplary embodiment
Second exemplary embodiment is similar with the first exemplary embodiment, and difference is only illustrated herein.Implement in the second example In example, memory management circuitry 202 can analyze this write instruction entity program to be write after write instruction is received Whether the number for changing unit is more than or equal to positive integer n.
Fig. 8 A and Fig. 8 B are that the second exemplary embodiment shows to write the flow chart of the first data.
Fig. 8 A are refer to, in step S602, memory management circuitry 202 is received after write instruction, memory pipe Reason circuit 202 can analyze this write instruction, and obtain this write instruction and be intended to write the first data to t entity program list Member, wherein t are positive integer.In step S802, it is just whole that memory management circuitry 202 can judge whether positive integer t is more than or equal to Number n.If step S802 result is yes, memory management circuitry 202 may proceed to step S604, remaining the step of with Fig. 6 A phases Together.If step S802 result is no, in step S804, it is real that memory management circuitry 202 can extract one the 3rd from idle area Body wipes unit, and writes first data into the 3rd entity the t entity program unit wiped in unit.In step After S804, memory management circuitry 202 can carry out each step in Fig. 8 B, and it is same as Fig. 6 B each step, herein just not Repeat again.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to The technical scheme described in foregoing embodiments can so be modified, or which part or all technical characteristic are entered Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology The scope of scheme..

Claims (25)

1. a kind of method for writing data, for controlling a reproducible nonvolatile memorizer module, wherein the duplicative is non- Volatile includes one first memory cell and one second memory cell, and first memory cell includes multiple first Entity wipes unit, and second memory cell includes multiple second instances and wipes unit, it is characterised in that the data write Method includes：
Configure multiple logical addresses with map at least part of those first instances erasing unit with it is at least part of those the Two entities wipe unit；
The write instruction from a host computer system is received, the wherein write instruction indicates to write one first data to those to patrol Collect one first logical address in address；
From those first instances erasing unit with obtaining one the 3rd entity erasing unit in those second instances erasing unit, and First data are write to the 3rd entity and wipe unit；
Judge that the 3rd entity erasing unit is to belong to first memory cell or second memory cell；And
If the 3rd entity erasing unit belongs to first memory cell, first data are write to the 3rd entity and wipe single When first, one of those second instances erasing unit is wiped,
When wherein first memory cell performs write operation or erasing operation, second memory cell performs write operation simultaneously Or erasing operation.
2. method for writing data according to claim 1, it is characterised in that also include：
If the 3rd entity erasing unit belongs to second memory cell, first data are write to the 3rd entity and wipe single When first, one of those first instances erasing unit is wiped.
3. method for writing data according to claim 2, it is characterised in that also include：
Those first instances erasing unit is at least divided into a data field and an idle area with those second instances erasing unit, Wherein at least part of those first instances erasing unit belongs to this with least part of those second instances erasing unit Data field；And
One first scratching area and one second scratching area are set,
Wherein the 3rd entity erasing unit belongs to the idle area, and those first instances wipe one of this of unit and belong to this First scratching area, and those second instances erasing unit this one of them belong to second scratching area.
4. method for writing data according to claim 3, it is characterised in that first logical address be map to those One entity wipes unit and one the 4th entity erasing unit among those second instances erasing unit, is write by first data Enter to after the step of the 3rd entity erasing unit, the method for writing data also includes：
Judge whether the 4th entity erasing unit needs to be wiped free of；
If the 4th entity erasing unit needs to be wiped free of, first scratching area or the entity erasing of second scratching area are judged Whether unit number is more than or equal to a critical value；
If the entity erasing unit number of first scratching area and second scratching area is less than the critical value, by the 4th entity Erasing unit is associated to first scratching area or second scratching area.
5. method for writing data according to claim 4, it is characterised in that also include：
If the entity erasing unit number of first scratching area or second scratching area is more than or equal to the critical value, wipe this Four entities wipe unit, and the 4th entity erasing unit is associated to the idle area.
6. method for writing data according to claim 3, it is characterised in that also include：
Those first instances are wiped to one of them pass of one of this of unit or those second instances erasing unit It is coupled to the idle area.
7. method for writing data according to claim 3, it is characterised in that be written into first data to the 3rd in fact After body erasing unit, first scratching area includes multiple first instance erasing units being wiped free of, and second erasing Area includes multiple second instance erasing units being wiped free of, and the method for writing data also includes：
The first instance that those have been wiped free of alternately is wiped into the second instance that one of unit has been wiped free of with those The association of one of unit is wiped to the idle area.
8. method for writing data according to claim 3, it is characterised in that each those first instances erasing unit includes Multiple entity program units, and those each second instances erasing unit includes multiple entity program units, the data Wiring method also includes：
One positive integer n is determined according to a writing speed of the reproducible nonvolatile memorizer module and an erasing time；
First data are write to the 3rd entity to n entity program list for wiping those entity program units in unit When first, check whether the entity in need being wiped free of wipes unit in first scratching area or second scratching area；And
If the entity in need being wiped free of wipes unit in first scratching area or second scratching area, performing the erasing should A little second instances erasing units this one of them the step of or the erasing those first instances erasing unit this wherein One of the step of.
9. method for writing data according to claim 3, it is characterised in that each those first instances erasing unit includes Multiple entity program units, each those second instances erasing unit includes multiple entity program units, and is write from this Enter instruction and obtain instruction t entity program unit of write-in, wherein t is positive integer, and the method for writing data also includes：
One positive integer n is determined according to a writing speed of the reproducible nonvolatile memorizer module and an erasing time；
Judge whether positive integer t is more than or equal to the positive integer n；
If positive integer t is less than the positive integer n, first data are write to the 3rd entity and wipe unit；
If positive integer t be more than or equal to the positive integer n, perform it is described acquirement the 3rd entity erasing unit the step of, it is described will The step of first data are write to the 3rd entity erasing unit, and the judgement the 3rd entity erasing unit is to belong to The step of first memory cell or second memory cell.
10. method for writing data according to claim 1, it is characterised in that those logical addresses are alternately to map to One of those first instances erasing unit wipes one of unit with those second instances.
11. a kind of memorizer memory devices, it is characterised in that including：
A connector, is electrically connected to a host computer system；
One reproducible nonvolatile memorizer module, including one first memory cell and one second memory cell, wherein this One memory cell includes multiple first instances and wipes unit, and second memory cell includes multiple second instances and wipes single Member；And
One Memory Controller, is electrically connected to the connector and the reproducible nonvolatile memorizer module, to configure Multiple logical addresses are wiped with mapping at least part of those first instances erasing unit with those at least part of second instances Except unit,
Wherein, the Memory Controller is indicated to receive the write instruction from the host computer system, the wherein write instruction One first logical address that one first data are write into those logical addresses,
Wherein, the Memory Controller is used to from those first instances erasing unit with being obtained in those second instances erasing unit One the 3rd entity wipes unit, and first data are write to the 3rd entity erasing unit,
Wherein, the Memory Controller to judge the 3rd entity erasing unit be belong to first memory cell or this Two memory cell,
If the 3rd entity erasing unit belongs to first memory cell, the Memory Controller by first data to write When entering to the 3rd entity erasing unit, one of those second instances erasing unit is wiped,
When wherein first memory cell performs write operation or erasing operation, second memory cell performs write operation simultaneously Or erasing operation.
12. memorizer memory devices according to claim 11, it is characterised in that if the 3rd entity erasing unit belongs to Second memory cell, the Memory Controller is used to, when first data are write to the 3rd entity erasing unit, wipe Except one of those first instances erasing unit.
13. memorizer memory devices according to claim 12, it is characterised in that the Memory Controller was also to should A little first instances erasing units are at least divided into a data field and an idle area with those second instances erasing unit, and wherein this is extremely Least a portion of those first instances erasing unit belongs to the data field with least part of those second instances erasing unit,
Wherein, the Memory Controller is also to set one first scratching area and one second scratching area, and wherein the 3rd entity is wiped Except unit belongs to the idle area, those first instances wipe one of this of unit and belong to first scratching area, and those Second instance wipes one of this of unit and belongs to second scratching area.
14. memorizer memory devices according to claim 13, it is characterised in that first logical address is to map to this A little first instances erasing units wipe one the 4th entity erasing unit among unit with those second instances, first are counted by this After write-in to the 3rd entity erasing unit, whether the Memory Controller is also to judge the 4th entity erasing unit Need to be wiped free of,
If the 4th entity erasing unit needs to be wiped free of, the Memory Controller also to judge first scratching area or this Whether the entity erasing unit number of two scratching areas is more than or equal to a critical value,
If the entity erasing unit number of first scratching area and second scratching area is less than the critical value, memory control Device is the 4th entity erasing unit is associated to first scratching area or second scratching area.
15. memorizer memory devices according to claim 14, it is characterised in that if first scratching area or second wiping Except the entity erasing unit number in area is more than or equal to the critical value, the Memory Controller is to wipe the erasing of the 4th entity Unit, and the 4th entity erasing unit is associated to the idle area.
16. memorizer memory devices according to claim 13, it is characterised in that the Memory Controller was also to should A little first instances erasing units this one of them or those second instances erasing unit one of them association to the spare time Put area.
17. memorizer memory devices according to claim 13, it is characterised in that first data be written into this Three entities erasing unit after, first scratching area include it is multiple be wiped free of first instances erasing units, and this second Scratching area include it is multiple be wiped free of second instances erasing units, the Memory Controller also to alternately by those by One of second instance erasing unit that one of first instance erasing unit of erasing has been wiped free of with those is closed It is coupled to the idle area.
18. memorizer memory devices according to claim 13, it is characterised in that those each first instances wipe unit Including multiple entity program units, each those second instances erasing unit includes multiple entity program units, and should Memory Controller according to a writing speed of the reproducible nonvolatile memorizer module with an erasing time also to determine A fixed positive integer n,
Wherein, the Memory Controller is also used to writing first data into those entities into the 3rd entity erasing unit During n entity program unit of programmed cell, check in first scratching area or second scratching area whether quilt in need The entity erasing unit of erasing,
If the entity in need being wiped free of wipes unit in first scratching area or second scratching area, the Memory Controller To this one of them the operation or the erasing that perform those second instances of erasing erasing unit, those are first real The operation of one of them of body erasing unit.
19. a kind of Memory Controller, for controlling a reproducible nonvolatile memorizer module, it is characterised in that this is deposited Memory controller includes：
One HPI, is electrically connected to a host computer system；
One memory interface, is electrically connected to the reproducible nonvolatile memorizer module, and wherein the duplicative is non- Volatile includes one first memory cell and one second memory cell, and wherein first memory cell includes multiple First instance wipes unit, and second memory cell includes multiple second instances and wipes unit；And
One memory management circuitry, is electrically connected to the HPI and the memory interface, to configure multiple logical addresses Unit is wiped with those at least part of second instances to map at least part of those first instances erasing unit,
Wherein, the memory management circuitry refers to receive the write instruction from the host computer system, the wherein write instruction Show one first logical address for writing one first data into those logical addresses,
Wherein, the memory management circuitry is used to wipe unit with taking in those second instances erasing unit from those first instances One the 3rd entity erasing unit is obtained, and first data are write to the 3rd entity erasing unit,
Wherein, the memory management circuitry is to judge that the 3rd entity erasing unit is to belong to first memory cell or be somebody's turn to do Second memory cell,
If the 3rd entity erasing unit belongs to first memory cell, the memory management circuitry is used to by first data When write-in to the 3rd entity wipes unit, one of those second instances erasing unit is wiped,
When wherein first memory cell performs write operation or erasing operation, second memory cell performs write operation simultaneously Or erasing operation.
20. Memory Controller according to claim 19, it is characterised in that if the 3rd entity erasing unit belongs to this Second memory cell, the memory management circuitry is used to, when first data are write to the 3rd entity erasing unit, wipe Except one of those first instances erasing unit.
21. Memory Controller according to claim 20, it is characterised in that the memory management circuitry was also to should A little first instances erasing units are at least divided into a data field and an idle area with those second instances erasing unit, and wherein this is extremely Least a portion of those first instances erasing unit belongs to the data field with least part of those second instances erasing unit,
Wherein, the memory management circuitry is also to set one first scratching area and one second scratching area, wherein the 3rd entity Erasing unit belongs to the idle area, and those first instances wipe one of this of unit and belong to first scratching area, and should A little second instances wipe one of this of units and belong to second scratching area.
22. Memory Controller according to claim 21, it is characterised in that first logical address is to map to those First instance wipes unit and those second instances and wipes one the 4th entity erasing unit among unit, by first data After write-in to the 3rd entity erasing unit, whether the memory management circuitry is also to judge the 4th entity erasing unit Need to be wiped free of,
If the 4th entity erasing unit needs to be wiped free of, the memory management circuitry is also to judge first scratching area or be somebody's turn to do Whether the entity erasing unit number of the second scratching area is more than or equal to a critical value,
If the entity erasing unit number of first scratching area and second scratching area is less than the critical value, the memory management Circuit is the 4th entity erasing unit is associated to one of first scratching area and second scratching area.
23. Memory Controller according to claim 22, it is characterised in that if first scratching area or second erasing The entity erasing unit number in area is more than or equal to the critical value, and the memory management circuitry is to wipe the erasing of the 4th entity Unit, and the 4th entity erasing unit is associated into the idle area.
24. Memory Controller according to claim 21, it is characterised in that be written into first data to the 3rd After entity erasing unit, first scratching area includes multiple first instance erasing units being wiped free of, and second wiping Wipe units except area includes multiple second instances for being wiped free of, the memory management circuitry also to alternately by those by One of second instance erasing unit that one of first instance erasing unit of erasing has been wiped free of with those is closed It is coupled to the idle area.
25. Memory Controller according to claim 21, it is characterised in that those each first instances wipe unit bag Multiple entity program units are included, each those second instances erasing unit includes multiple entity program units, and this is deposited Reservoir management circuit according to a writing speed of the reproducible nonvolatile memorizer module with an erasing time also to determine A fixed positive integer n,
Wherein, the memory management circuitry is also used to writing first data into those realities into the 3rd entity erasing unit During n entity program unit of body programmed cell, check whether in need in first scratching area or second scratching area The entity erasing unit being wiped free of,
If the entity in need being wiped free of wipes unit in first scratching area or second scratching area, memory management electricity Road to perform those second instances of erasing erasing unit this one of them operation or the erasing those first The operation of one of them of entity erasing unit.
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