CN104238956A

CN104238956A - Method for writing data, controller of storage, and storage device of storage

Info

Publication number: CN104238956A
Application number: CN201310253210.7A
Authority: CN
Inventors: 叶志刚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2013-06-24
Filing date: 2013-06-24
Publication date: 2014-12-24

Abstract

The invention relates to a method for writing data, a controller of a storage and a storage device of the storage. The method is applicable to rewritable nonvolatile storage modules, and includes extracting physical erasing units to be used as global chaos regions; creating search tables of the global chaos regions to record a plurality of pieces of update information of updated logic pages in the global chaos regions; receiving update data required to be stored in a logic page; judging whether data scattering degrees corresponding to the global chaos regions are smaller than data scattering degree threshold values or not; writing the update data into the global chaos regions if the data scattering degrees corresponding to the global chaos regions are smaller than the data scattering degree threshold values, and recording the update information corresponding to the logic page in the search tables of the global chaos regions. The update data which are correspondingly temporarily stored in the global chaos regions belong to the updated logic pages.

Description

Method for writing data, Memory Controller and memory storage apparatus

Technical field

The present invention relates to Memory Controller and the memory storage apparatus of a kind of method for writing data for type nonvolatile and use the method.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, and the demand of consumer to storage medium is also increased rapidly.Because type nonvolatile (rewritable non-volatile memory) has the characteristics such as data are non-volatile, power saving, volume is little, mechanical structure, read or write speed are fast, be most suitable for portable electronic product, such as mobile computer.Solid state hard disc is exactly a kind of memory storage apparatus using flash memory as storage medium.Therefore, flash memory industry becomes a ring quite popular in electronic industry in recent years.

Flash memory module has multiple physics erased cell (physical erasing unit) and each physics erased cell has multiple physics programming unit (physical page), must be sequentially written in data when wherein writing data in physics erased cell according to physics programming unit.In addition, the physics programming unit needing being written into data could again for writing data after first being erased.Particularly, physics erased cell is the least unit of erasing, and physics programming unit is the minimum unit of programming (also known as write).Therefore, in the management of flash memory module, physics erased cell can be divided into data field and idle district.

The physics erased cell of data field is the data stored in order to host system.Specifically, the logic access address that host computer system can access by the memory management circuitry in memory storage apparatus is converted to the logical page (LPAGE) of logical blocks and the logical page (LPAGE) of logical blocks is mapped to the physics programming unit of the physics erased cell of data field.That is, in the management of flash memory module, the physics erased cell of data field is regarded as by the physics erased cell (such as, the data that write of host system) used.Such as, memory management circuitry can use logic to turn physical address mapping table to record the mapping relations of the physics erased cell of logical blocks and data field, and the logical page (LPAGE) wherein in logical blocks is the physics programming unit of the corresponding physics erased cell mapped.

The physics erased cell in idle district is the physics erased cell of rotating in data field.Specifically, as mentioned above, the physics erased cell of written data just can again for writing data after must being erased, therefore, the physics erased cell in idle district be designed to write more new data to replace the physics erased cell of mapping logic block.Base this, the physics erased cell in idle district is empty or spendable physics erased cell, i.e. no record data or be labeled as invalid data useless.

That is, the physics programming unit of the physics erased cell in data field and idle district is the logical page (LPAGE) that the mode of rotating carrys out mapping logic block, the data write with host system.Such as, the memory management circuitry of memory storage apparatus can extract one or more physics erased cell as the chaotic physics erased cell of universe from idle district, and when host computer system is a certain logical page (LPAGE) of a certain logical blocks of correspond to memories memory storage for writing the logic access address of more new data, the memory management circuitry of memory storage apparatus can by this more new data write in the physics programming unit of the chaotic physics erased cell of universe.

Particularly, during memory storage apparatus running, when universe chaotic physics erased cell fast depleted time, the memory management circuitry of memory storage apparatus can by the data preparation that is stored in the chaotic physics erased cell of universe to (hereinafter referred to as " valid data merge running ") in corresponding physics erased cell, to vacate the storage space of the chaotic physics erased cell of universe, the write instruction that executed is follow-up.After the data preparation that will be stored in the chaotic physics erased cell of universe is to corresponding physics erased cell, the memory management circuitry of memory storage apparatus needs more new logic to turn physical address mapping table, can normally be performed to make follow-up access running.Because the capacity of memory storage apparatus is increasing, therefore, multiple logic generally can be used to turn physical address mapping table to record the mapping between all logical blocks and physics erased cell.Therefore, when " valid data merging running " first need be carried out can complete the write instruction coming from host computer system, logic that may be different from restoring because of the carrying out loading needed repeatedly turns physical address mapping table and turns physical address mapping table so that the information in chaotic for universe district's search table is recorded to logic, and cause the time having postponed this write instruction, cause the usefulness of memory storage apparatus low.

Summary of the invention

The invention provides a kind of method for writing data, Memory Controller, Memory Controller and memory storage apparatus, it can be reduced in the delay caused because carrying out universe chaotic physics erased cell valid data to merge running when performing write instruction effectively.

The present invention one exemplary embodiment proposes a kind of for writing the method for writing data of data to reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple physics erased cell, each physics erased cell has multiple physics programming unit, this a little physics erased cell is at least grouped into data field and idle district, the physics erased cell in this idle district in order to the physics erased cell in replacement data district to write data, multiple logical block is configured to the physics erased cell mapping this data field, and each logical block has multiple logical page (LPAGE).Notebook data wiring method comprises: from the physics erased cell in idle district, extract at least one physics erased cell as the chaotic district of universe, wherein the chaotic district of this universe is in order to the temporary data belonging to multiple more new logical page, and this little more new logical page to belong among this little logical block multiple upgrades logical block.Notebook data wiring method also comprises sets up the chaotic district's search table of universe to be recorded in multiple lastest imformations of this little more new logical page corresponding in the chaotic district of universe.Notebook data wiring method also comprises and receives write instruction and write the more new data of instruction with corresponding this, wherein this more new data be belong to the first logical page (LPAGE) and first logical block of the first logical page (LPAGE) genus among this little logical block.Notebook data wiring method also comprises the scattered degree of data in the chaotic district of record this universe corresponding; Judge whether the scattered degree of data in the chaotic district of this universe corresponding is less than the scattered degree threshold value of data; And when if the scattered degree of data in the chaotic district of this universe corresponding is less than data scattered degree threshold value, by this more new data to write in the chaotic district of this universe and in the chaotic district's search table of universe, record the lastest imformation of corresponding first logical page (LPAGE).

In one example of the present invention embodiment, above-mentioned method for writing data also comprises: if the scattered degree of these data in the chaotic district of this universe corresponding is non-when being less than the scattered degree threshold value of data, the muon physics erased cell of the first physics erased cell as corresponding first logical block is extracted from idle district, to more write in this muon physics erased cell by new data, and the logic upgrading corresponding first logical block turns physical address mapping table, wherein this muon physics erased cell is only in order to store the data belonging to the first logical block.

In one example of the present invention embodiment, above-mentioned method for writing data also comprises: this little logical block is grouped into multiple logic region; And configure multiple logic and turn physical address mapping table to be assigned to this little logic region respectively, wherein this little logic turns physical address mapping table in order to record multiple mapping relations between the logical block of this little logic region and the physics erased cell of above-mentioned data field and each logic turns physical address mapping table is configured independently to one of them of this little logic region.

In one example of the present invention embodiment, this has upgraded logical block a bit and has belonged to multiple among this little logic region and upgrade logic region.Further, the step of the scattered degree of data in the chaotic district of record this universe corresponding comprises: calculate the number that this has upgraded logic region a bit; And record the data scattered degree of this number having upgraded logic region a bit as the chaotic district of corresponding universe.

In one example of the present invention embodiment, the step of the scattered degree of data in the chaotic district of above-mentioned record this universe corresponding comprises: calculate the above-mentioned number having upgraded logical block; And record the data scattered degree of this number having upgraded logical block a bit as the chaotic district of corresponding universe.

In one example of the present invention embodiment, the step of the scattered degree of data in the chaotic district of above-mentioned record this universe corresponding comprises: calculate multiple logic to be updated and turn the number of physical address mapping table and record the data scattered degree of number as the chaotic district of corresponding universe that this little logic to be updated turns physical address mapping table, wherein this little logic to be updated turns physical address mapping table in order to record the mapping between the above-mentioned physics erased cell having upgraded logical block and above-mentioned data field.

In one example of the present invention embodiment, above-mentioned method for writing data, also comprises: judge whether there are the valid data belonging to above-mentioned first logical block in the chaotic district of universe; And when having the valid data belonging to above-mentioned first logical block in the chaotic district of similar regions, above-mentioned more new data is write in the chaotic district of universe, be performed when wherein the above-mentioned step judging whether the scattered degree of data in the chaotic district of corresponding universe is less than data scattered degree threshold value is and does not have the valid data belonging to above-mentioned first logical block in the chaotic district of universe.

The present invention one exemplary embodiment proposes a kind of Memory Controller for controlling reproducible nonvolatile memorizer module, wherein reproducible nonvolatile memorizer module has multiple physics erased cell, each physics erased cell has multiple physics programming unit, this a little physics erased cell is at least grouped into data field and idle district, the physics erased cell in idle district in order to the physics erased cell in replacement data district to write data.Memory Controller comprises host interface, memory interface and memory management circuitry.Host interface is in order to be electrically connected to host computer system.Memory interface is in order to be electrically connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to host interface and memory interface, and in order to configure multiple logical block with these physics erased cell in mapping (enum) data district, wherein each logical block has multiple logical page (LPAGE).In addition, memory management circuitry also in order to extract at least one physics erased cell as the chaotic district of universe from the physics erased cell in idle district, wherein the chaotic district of this universe is in order to the temporary data belonging to multiple more new logical page, and this little more new logical page to belong among above-mentioned logical block multiple upgrades logical block.In addition, memory management circuitry is also in order to set up the chaotic district's search table of universe to be recorded in multiple lastest imformations of this little more new logical page corresponding in the chaotic district of this universe.At this, memory management circuitry also writes the more new data of instruction in order to receive write instruction with corresponding this, this more new data be belong to the first logical page (LPAGE) and the first logical page (LPAGE) belongs to the first logical block.Moreover memory management circuitry is also in order to record the scattered degree of data in the chaotic district of corresponding universe and to judge whether the scattered degree of data in the chaotic district of corresponding universe is less than the scattered degree threshold value of data.If when the scattered degree of data in the chaotic district of corresponding universe is less than data scattered degree threshold value, more new data to write in the chaotic district of universe and in the chaotic district's search table of universe, records the lastest imformation of corresponding first logical page (LPAGE) by memory management circuitry.

In one example of the present invention embodiment, if the scattered degree of these data in the chaotic district of this universe corresponding is non-when being less than the scattered degree threshold value of data, above-mentioned memory management circuitry extracts the muon physics erased cell of the first physics erased cell as corresponding first logical block from idle district, to more write in this muon physics erased cell by new data, and the logic upgrading corresponding first logical block turns physical address mapping table, wherein this muon physics erased cell is only in order to store the data belonging to the first logical block.

In one example of the present invention embodiment, above-mentioned memory management circuitry also turns physical address mapping table to be assigned to this little logic region respectively in order to this little logical block is grouped into multiple logic region and configures multiple logic, and wherein this little logic turns physical address mapping table in order to record multiple mapping between the logical block of this little logic region and the physics erased cell of above-mentioned data field and each logic turns physical address mapping table is configured independently to one of them of this little logic region.

In one example of the present invention embodiment, this has upgraded logical block a bit and has belonged to multiple among this little logic region and upgrade logic region.And, in the running of the scattered degree of data in the chaotic district of above-mentioned record this universe corresponding, above-mentioned memory management circuitry calculates this number having upgraded logic region a bit and records the data scattered degree of this number having upgraded logic region a bit as the chaotic district of corresponding universe.

In one example of the present invention embodiment, in the running of the scattered degree of data in the chaotic district of above-mentioned record this universe corresponding, above-mentioned memory management circuitry calculating is above-mentioned have been upgraded the number of logical block and has recorded the data scattered degree of this number having upgraded logical block a bit as the chaotic district of corresponding universe.

In one example of the present invention embodiment, in the running of the scattered degree of data in the chaotic district of above-mentioned record this universe corresponding, above-mentioned memory management circuitry calculates multiple logic to be updated and turns the number of physical address mapping table and record the data scattered degree of number as the chaotic district of corresponding universe that this little logic to be updated turns physical address mapping table, and wherein this little logic to be updated turns physical address mapping table in order to record the mapping between the above-mentioned physics erased cell having upgraded logical block and above-mentioned data field.

In one example of the present invention embodiment, memory management circuitry is also in order to judge whether there are the valid data belonging to above-mentioned first logical block in the chaotic district of universe, when wherein having the valid data belonging to above-mentioned first logical block in the chaotic district of similar regions, above-mentioned more new data writes in the chaotic district of universe by memory management circuitry, performs the above-mentioned the running whether scattered degree of data in the chaotic district of corresponding universe is less than the scattered degree threshold value of data that judges when wherein memory management circuitry is and does not have the valid data belonging to the first logical block in the chaotic district of universe.

The present invention one exemplary embodiment proposes a kind of memory storage apparatus, and it comprises connector, reproducible nonvolatile memorizer module and Memory Controller.Connector is in order to be electrically connected to host computer system.Reproducible nonvolatile memorizer module has multiple physics erased cell, each physics erased cell has multiple physics programming unit, this a little physics erased cell is at least grouped into data field and idle district, and the physics erased cell in idle district in order to the physics erased cell in replacement data district to write data.Memory Controller is electrically connected to connector and reproducible nonvolatile memorizer module, and in order to configure multiple logical block with these physics erased cell in mapping (enum) data district, wherein each logical block has multiple logical page (LPAGE).In addition, Memory Controller also in order to extract at least one physics erased cell as the chaotic district of universe from the physics erased cell in idle district, wherein the chaotic district of this universe is in order to the temporary data belonging to multiple more new logical page, and this little more new logical page to belong among above-mentioned logical block multiple upgrades logical block.In addition, Memory Controller is also in order to set up the chaotic district's search table of universe to be recorded in multiple lastest imformations of this little more new logical page corresponding in the chaotic district of this universe.At this, Memory Controller also writes the more new data of instruction in order to receive write instruction with corresponding this, this more new data be belong to the first logical page (LPAGE) and the first logical page (LPAGE) belongs to the first logical block.Moreover Memory Controller is also in order to record the scattered degree of data in the chaotic district of corresponding universe and to judge whether the scattered degree of data in the chaotic district of corresponding universe is less than the scattered degree threshold value of data.If when the scattered degree of data in the chaotic district of corresponding universe is less than data scattered degree threshold value, more new data to write in the chaotic district of universe and in the chaotic district's search table of universe, records the lastest imformation of corresponding first logical page (LPAGE) by Memory Controller.

In one of the present invention exemplary embodiment, if the scattered degree of these data in the chaotic district of this universe corresponding is non-when being less than the scattered degree threshold value of data, above-mentioned Memory Controller extracts the muon physics erased cell of the first physics erased cell as corresponding first logical block from idle district, more new data is write in the muon physics erased cell of corresponding first logical block, and the logic upgrading corresponding first logical block turns physical address mapping table, wherein this muon physics erased cell is only in order to store the data belonging to the first logical block.

In one example of the present invention embodiment, above-mentioned Memory Controller also turns physical address mapping table to be assigned to this little logic region respectively in order to this little logical block is grouped into multiple logic region and configures multiple logic, and wherein this little logic turns physical address mapping table in order to record multiple mapping relations between the logical block of this little logic region and the physics erased cell of above-mentioned data field and each logic turns physical address mapping table is configured independently to one of them of this little logic region.

In one example of the present invention embodiment, this has upgraded logical block a bit and has belonged to multiple among this little logic region and upgrade logic region.And, in the running of the scattered degree of data in the chaotic district of above-mentioned record this universe corresponding, above-mentioned Memory Controller calculates this number having upgraded logic region a bit and records the data scattered degree of this number having upgraded logic region a bit as the chaotic district of corresponding universe.

In one example of the present invention embodiment, in the running of the scattered degree of data in the chaotic district of above-mentioned record this universe corresponding, above-mentioned Memory Controller calculating is above-mentioned have been upgraded the number of logical block and has recorded the data scattered degree of this number having upgraded logical block a bit as the chaotic district of corresponding universe.

In one example of the present invention embodiment, in the running of the scattered degree of data in the chaotic district of above-mentioned record this universe corresponding, above-mentioned Memory Controller calculates multiple logic to be updated and turns the number of physical address mapping table and record the data scattered degree of number as the chaotic district of corresponding universe that this little logic to be updated turns physical address mapping table, and wherein this little logic to be updated turns physical address mapping table in order to record the mapping between the above-mentioned physics erased cell having upgraded logical block and above-mentioned data field.

In one example of the present invention embodiment, Memory Controller is also in order to judge whether there are the valid data belonging to above-mentioned first logical block in the chaotic district of universe, when wherein having the valid data belonging to above-mentioned first logical block in the chaotic district of similar regions, above-mentioned more new data writes in the chaotic district of universe by Memory Controller, performs the above-mentioned the running whether scattered degree of data in the chaotic district of corresponding universe is less than the scattered degree threshold value of data that judges when wherein Memory Controller is and does not have the valid data belonging to the first logical block in the chaotic district of universe.

Based on above-mentioned, the method for writing data of exemplary embodiment of the present invention, Memory Controller and memory storage apparatus can be avoided expending when performing universe chaotic physics erased cell valid data and merging and operate the too much time and turn physical address mapping table in more new logic, promote the speed that execution writes instruction thus.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Fig. 1 is the host computer system and memory storage apparatus that illustrate according to an exemplary embodiment.

Fig. 2 is the schematic diagram of computing machine, input/output device and the memory storage apparatus illustrated according to exemplary embodiment of the present invention.

Fig. 3 is the schematic diagram of host computer system and the memory storage apparatus illustrated according to exemplary embodiment of the present invention.

Fig. 4 is the schematic block diagram illustrating the memory storage apparatus shown in Fig. 1.

Fig. 5 is the schematic block diagram of the Memory Controller illustrated according to an exemplary embodiment.

Fig. 6 and Fig. 7 is the example schematic of the managing physical block illustrated according to the first exemplary embodiment.

Fig. 8 ~ 14 illustrate the simplification example using universe chaotic district's write data.

Figure 15 is the simplification example of the chaotic district's search table of universe illustrated according to Figure 14.

Figure 16 ~ 21 illustrate to perform universe chaotic district valid data consolidation procedure to complete the simplification example of follow-up write instruction.

Figure 22 ~ Figure 24 is the example that the use muon physics unit illustrated writes more new data.

Figure 25 is the process flow diagram of the method for writing data illustrated according to an exemplary embodiment.

[symbol description]

1000: host computer system

1100: computing machine

1102: microprocessor

1104: random access memory

1106: input/output device

1108: system bus

1110: data transmission interface

1202: mouse

1204: keyboard

1206: display

1208: printer

1212: Portable disk

1214: storage card

1216: solid state hard disc

1310: digital camera

1312:SD card

1314:MMC card

1316: memory stick

1318:CF card

1320: embedded memory storage

100: memory storage apparatus

102: connector

104: Memory Controller

106: reproducible nonvolatile memorizer module

202: memory management circuitry

204: host interface

206: memory interface

208: memory buffer

210: electric power management circuit

212: bug check and correcting circuit

410 (0) ~ 410 (N): physics erased cell

502: system region

504: data field

506: idle district

508: replace district

550: the chaotic district of universe

LBA (0) ~ LBA (H): logical block

LZ (0) ~ LZ (M): logic region

800: table is searched in the chaotic district of universe

810 (0) ~ 810 (4): root unit

902: the first fields

904: the second fields

906: third column position

S2501, S2503, S2505, S2507, S2509, S2511: the step of method for writing data

Embodiment

Generally speaking, memory storage apparatus (also known as, storage system) comprises reproducible nonvolatile memorizer module and controller (also known as, control circuit).Usual memory storage apparatus uses together with host computer system, data can be write to memory storage apparatus or read data from memory storage apparatus to make host computer system.

Please refer to Fig. 1, host computer system 1000 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises as the mouse 1202 of Fig. 2, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2, input/output device 1106 can also comprise other devices.

In embodiments of the present invention, memory storage apparatus 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memory storage apparatus 100.Such as, memory storage apparatus 100 can be the type nonvolatile memory storage of Portable disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 etc. as shown in Figure 2.

Generally speaking, host computer system 1000 is any system that can coordinate to store data substantially with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile memory storage is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (as shown in Figure 3).Embedded memory storage 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.

Please refer to Fig. 4, memory storage apparatus 100 comprises connector 102, Memory Controller 104 and reproducible nonvolatile memorizer module 106.

In this exemplary embodiment, connector 102 is compatible to advanced annex (Serial Advanced Technology Attachment, the SATA) standard of serial.But, it must be appreciated, the present invention is not limited thereto, connector 102 also can be meet parallel advanced annex (Parellel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, USB (universal serial bus) (Universal Serial Bus, USB) standard, a hypervelocity generation (Ultra High Speed-I, UHS-I) interface standard, hypervelocity two generation (Ultra High Speed-II, UHS-II) interface standard, secure digital (Secure Digital, SD) interface standard, memory stick (Memory Stick, MS) interface standard, multimedia storage card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated Device Electronics, IDE) standard or other standards be applicable to.

Memory Controller 104 in order to perform in the form of hardware or multiple logic gate of form of firmware implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the running such as to erase.

Reproducible nonvolatile memorizer module 106 is electrically connected to Memory Controller 104, and in order to data that host system 1000 writes.Reproducible nonvolatile memorizer module 106 has physics erased cell 410 (0) ~ 410 (N).Such as, physics erased cell 410 (0) ~ 410 (N) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each physics erased cell has multiple physics programming unit respectively, and the physics programming unit wherein belonging to same physics erased cell can be written independently and side by side be erased.But it must be appreciated, the present invention is not limited thereto, each physics erased cell can be made up of 64 physics programming units, 256 physics programming units or other any physics programming units.

In more detail, physics erased cell is the least unit of erasing.That is, each physics erased cell contain minimal amount in the lump by the memory cell of erasing.Physics programming unit is the minimum unit of programming.That is, physics programming unit is the minimum unit of write data.Each physics programming unit generally includes data bit district and redundant digit district.Data bit district comprises multiple physics access address in order to store the data of user, and redundant digit district is in order to the data (such as, control information and error correcting code) of storage system.In this exemplary embodiment, 4 physics access addresses in the data bit district of each physics programming unit, can be comprised, and the size of a physics access address is 512 bytes (byte).But in other exemplary embodiment, can comprise the more or less physics access address of number in data bit district, the present invention does not limit size and the number of physics access address yet.Such as, in an exemplary embodiment, physics erased cell is physical blocks, and physics programming unit is physical page or physical sector, but the present invention is not as limit.

In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is multistage memory cell (Multi Level Cell, MLC) NAND type flash memory module (that is, can store the flash memory module of 2 bit data in a memory cell).But, the present invention is not limited thereto, reproducible nonvolatile memorizer module 106 may also be single-order memory cell (Single Level Cell, SLC) NAND type flash memory module (namely, the flash memory module of 1 bit data can be stored in a memory cell), multistage memory cell (Trinary Level Cell, TLC) NAND type flash memory module (that is, the flash memory module of 3 bit data can be stored in a memory cell), other flash memory module or other there is the memory module of identical characteristics.

Please refer to Fig. 5, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.

Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has multiple steering order, and when memory storage apparatus 100 operates, this little steering order can be performed to carry out data write, read and the running such as to erase.

In this exemplary embodiment, the steering order of memory management circuitry 202 carrys out implementation with form of firmware.Such as, memory management circuitry 202 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and this little steering order is burned onto in this ROM (read-only memory).When memory storage apparatus 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the running such as to erase.

In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can form of program code be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of reproducible nonvolatile memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has driving code, and when Memory Controller 104 is enabled, microprocessor unit first can perform this and drive code section the steering order be stored in reproducible nonvolatile memorizer module 106 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order with carry out data write, read and the running such as to erase.

In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also an example, in hardware can carry out implementation.Such as, memory management circuitry 202 comprises microcontroller, memory cell management circuit, storer write circuit, memory reading circuitry, storer erase circuit and data processing circuit.Erase circuit and data processing circuit of memory cell management circuit, storer write circuit, memory reading circuitry, storer is electrically connected to microcontroller.Wherein, memory cell management circuit is in order to manage the physics erased cell of reproducible nonvolatile memorizer module 106; Storer write circuit is in order to assign write instruction data to be write in reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Memory reading circuitry is in order to assign reading command to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer erases circuit in order to assign instruction of erasing to reproducible nonvolatile memorizer module 106 data to be erased from reproducible nonvolatile memorizer module 106; And data processing circuit is in order to the data processed for writing to reproducible nonvolatile memorizer module 106 and the data read from reproducible nonvolatile memorizer module 106.

Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is compatible to SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 also can be compatible to PATA standard, IEEE1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards be applicable to.

Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.

In the present invention one exemplary embodiment, Memory Controller 104 also comprises memory buffer 208, electric power management circuit 210 and bug check and correcting circuit 212.

Memory buffer 208 is electrically connected to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.

Electric power management circuit 210 is electrically connected to memory management circuitry 202 and in order to the power supply of control store memory storage 100.

Bug check and correcting circuit 212 are electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 212 can be that the corresponding data that this writes instruction produce corresponding bug check and correcting code (Error Checking and Correcting Code, ECC Code), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding bug check and correcting code by memory management circuitry 202.Afterwards, can read bug check corresponding to these data and correcting code when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 212 can according to this bug check and correcting code to read data execution error inspection and correction programs simultaneously.

Fig. 6 and Fig. 7 is the example schematic of the managing physical erased cell illustrated according to the first exemplary embodiment.

Please refer to Fig. 6, physics erased cell 410 (0) ~ 410-(N) logically can be grouped into data field 502, idle district 504, system region 506 and replace district 508 by Memory Controller 104 (or memory management circuitry 202).

Belonging to data field 502 in logic with the physics erased cell in idle district 504 is in order to store the data coming from host computer system 1000.Specifically, the physics erased cell of data field 502 is the physics erased cell being regarded as storing data, and the physics erased cell in idle district 504 is the physics erased cell in order to replacement data district 502.That is, when receiving the data that write instruction writes with wish from host computer system 1000, memory management circuitry 202 meeting extracts physical erased cell from idle district 504, and data are write in extracted physics erased cell, with the physics erased cell in replacement data district 502.

The physics erased cell belonging to system region 506 is in logic in order to register system data.Such as, system data comprises manufacturer about reproducible nonvolatile memorizer module and model, the physics erased cell number of reproducible nonvolatile memorizer module, the physics programming unit number etc. of each physics erased cell.

Belonging to the physics erased cell replaced in district 508 is in logic replace program, with replacing damaged physics erased cell for bad physics erased cell.Specifically, if replace in district 508 still have normal physics erased cell and the physics erased cell of data field 502 damages time, memory management circuitry 202 can extract normal physics erased cell to change the physics erased cell of damage from replacement district 508.

Particularly, data field 502, idle district 504, system region 506 can be different according to different storer specifications with the quantity of the physics erased cell in replacement district 508.In addition, it must be appreciated, in the running of memory storage apparatus 100, physics erased cell is associated to data field 502, idle district 504, system region 506 can dynamically change with the grouping relation replacing district 508.Such as, when the physics erased cell in idle district 504 damages and is substituted the physics erased cell replacement in district 508, then the physics erased cell originally replacing district 508 can be associated to idle district 504.

Please refer to Fig. 7, Memory Controller 104 (or memory management circuitry 202) meeting configuration logic unit LBA (0) ~ LBA (H) is with the physics erased cell in mapping (enum) data district 502, and wherein each logical block has the physics programming unit of the physics erased cell that multiple logical page (LPAGE) is answered with mapping pair.And, when host computer system 100 to be stored in the data in logical block for write data to logical block or renewal, Memory Controller 104 (or memory management circuitry 202) can extract a physics erased cell and write data, with the physics erased cell of data field 502 of rotating from idle district 504.

Data in order to each logical block of identification data are stored in that physics erased cell, in this exemplary embodiment, Memory Controller 104(or memory management circuitry 202) mapping between logical block and physics erased cell can be recorded.And, when host computer system 1000 is in logical page (LPAGE) during access data, Memory Controller 104 (or memory management circuitry 202) can confirm the logical block belonging to this logical page (LPAGE), and carrys out access data in the physics erased cell mapped in this logical block.Such as, in this exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) stored logic can turn the physics erased cell that physical address mapping table maps to record each logical block in reproducible nonvolatile memorizer module 106, and logic is turned physical address mapping table and be loaded into memory buffer 208 when for Memory Controller 104 (or memory management circuitry 202) during access data and safeguard.

It is worth mentioning that, because the finite capacity of memory buffer 208 cannot the mapping table of mapping relations of all logical blocks of stored record, therefore, in this exemplary embodiment, Memory Controller 104(or memory management circuitry 202) logical block LBA (0) ~ LBA (H) can be grouped into multiple logic region LZ (0) ~ LZ (M), and turn physical address mapping table for each logic region configures a logic.Particularly, when Memory Controller 104 (or memory management circuitry 202) is for upgrading the mapping of certain logical block, the logic of corresponding logic region belonging to this logical block turns physical address mapping table and can be loaded on memory buffer 208 and be updated.

In this exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) as the chaotic district of universe, and to write to being contained in the physics erased cell (being also called the chaotic physics erased cell of universe) in the chaotic district of universe from the data (be also called and upgrade data) in the write instruction of host computer system 1000 by extracts physical erased cell from idle district 504.In this exemplary embodiment, the chaotic physics erased cell of universe is that design stores the data corresponding respectively to Different Logic unit.

Specifically, when memory storage apparatus 100 receives write instruction from host computer system 1000, the data come from the write instruction of host computer system 1000 can be written in the physics erased cell in the chaotic district of universe.And, when the chaotic physics erased cell of this universe is fully written, Memory Controller 104 (or memory management circuitry 202) can extract empty physics erased cell again as the chaotic physics erased cell of another universe from idle district 504, to continue to write the corresponding more new data coming from the write instruction of host computer system 1000.Until when having arrived a higher limit as the number of the physics erased cell in the chaotic district of universe, Memory Controller 104 (or memory management circuitry 202) can perform data consolidation procedure, to make the data be stored in the chaotic physics erased cell of universe become invalid data, and the chaotic physics erased cell of the universe afterwards stored data being all invalid data associates go back to idle district 504.

For convenience of description, in this tentation data district 502, there are 5 physics erased cell, idle district 504 has 4 physics erased cell, each physics erased cell has 3 physics programming units, data for writing to each physics erased cell must be written into according to the order of physics programming unit, and are 2 as the higher limit of the physics erased cell number of the chaotic physics erased cell of universe.

Please refer to Fig. 8, in the original state of memory storage apparatus 100, the physics programming unit of the physics erased cell 410 (0) ~ 410 (4) in the logical page (LPAGE) mapping (enum) data district 502 of logical block LBA (0) ~ LBA (4), and idle district 504 has physics erased cell 410 (5) ~ 410 (8).That is, Memory Controller 104 (or memory management circuitry 202) can turn in physical address mapping table in logic the mapping relations recording logical block LBA (0) ~ between LBA (4) and physics erased cell 410 (0) ~ 410 (4), and be considered as the physics programming unit of physics erased cell 410 (0) ~ 410 (4) to store the data (that is, primary data ID1 ~ ID15) of the logical page (LPAGE) belonging to logical block LBA (0) ~ LBA (4).It must be appreciated, when memory storage apparatus 100 just dispatches from the factory, primary data ID1 ~ ID15 may be empty data.In addition, Memory Controller 104 (or memory management circuitry 202) can record physics erased cell 410 (5) ~ 410 (8) available in idle district 504.

Please refer to Fig. 9, suppose for programme more new data UD1 and more new data UD1 is the 1st logical page (LPAGE) belonging to logical block LBA (0) time, Memory Controller 104 (or memory management circuitry 202) can from idle district 504 extracts physical erased cell 410 (5) as the chaotic district 550 of universe physics erased cell and assign programming instruction with by this more new data UD1 write to the 0th physics programming unit of physics erased cell 410 (5).

Please refer to Figure 10, hookup 9, suppose for programme again more new data UD2 and more new data UD2 is the 0th logical page (LPAGE) belonging to logical block LBA (1) time, Memory Controller 104 (or memory management circuitry 202) can assign programming instruction with by this more new data UD2 write to the 1st physics programming unit of physics erased cell 410 (5).

Please refer to Figure 11, continue Figure 10, suppose for programme again more new data UD3 and more new data UD3 is the 1st logical page (LPAGE) belonging to logical block LBA (2) time, Memory Controller 104 (or memory management circuitry 202) can assign programming instruction with by this more new data UD3 write to the 2nd physics programming unit of physics erased cell 410 (5).

Please refer to Figure 12, continue Figure 11, suppose for programme again more new data UD4 and more new data UD4 is the 0th logical page (LPAGE) belonging to logical block LBA (3) time, because the chaotic physics erased cell 410 (5) of universe is without storage space, therefore, Memory Controller 104 (or memory management circuitry 202) can from idle district 504 extracts physical erased cell 410 (6) as the chaotic district 550 of universe physics erased cell and assign programming instruction with by this more new data UD4 write to the 0th physics programming unit of physics erased cell 410 (6).

Please refer to Figure 13, continue Figure 12, suppose for programme again more new data UD5 and more new data UD5 is the 1st logical page (LPAGE) belonging to logical block LBA (3) time, Memory Controller 104 (or memory management circuitry 202) can assign programming instruction with by this more new data UD5 write to the 1st physics programming unit of physics erased cell 410 (6).

Please refer to Figure 14, continue Figure 13, suppose for programme again more new data UD6 and more new data UD6 is the 2nd logical page (LPAGE) belonging to logical block LBA (0) time, Memory Controller 104 (or memory management circuitry 202) can assign programming instruction with by this more new data UD6 write to the 2nd physics programming unit of physics erased cell 410 (6).

In order to identify that the data in the physics erased cell being stored in the chaotic district of universe are those logical page (LPAGE)s (being also called more new logical page) belonging to that logical block (be also called and upgraded logical block), in this exemplary embodiment, memory management circuitry 202 can set up the chaotic district's search table of universe, in order to the search of valid data.At this, the logical page (LPAGE) more belonging to new data be temporary in the chaotic district of universe is called more new logical page and logical block block more belonging to new logical page is called and upgrades logical block.In universe, chaotic district searches in table, and Memory Controller 104 (or memory management circuitry 202) can be set up multiple root unit and be each root unit configuration one login link.Particularly, the grouping of the logical page (LPAGE) of logical block can be corresponded to one of them root unit by Memory Controller 104 (or memory management circuitry 202) respectively, and the Login chain lastest imformation of more new logical page being recorded in corresponding root unit is tied.Base this, when for searching the more new data of specific logical unit in the chaotic physics erased cell of universe, only need the login link searching corresponding root unit.

Such as, in this exemplary embodiment, the logical page (LPAGE) of each logical block can be corresponded to same root unit by Memory Controller 104 (or memory management circuitry 202) respectively.Namely, the logical page (LPAGE) of same logical block is corresponding same root unit.It must be appreciated, the present invention is not limited thereto, such as, in another example of the present invention is implemented, also can by a part of logical page (LPAGE) grouping of a logical block to a root unit and by the grouping of another part logical page (LPAGE) of this logical block to another root unit.

In addition, when configuring one for each root unit respectively and log in link and whenever execution write instruction, Memory Controller 104 (or memory management circuitry 202) can tie at the Login chain of correspondence the lastest imformation set up and log in record about this write instruction.Such as, each login comprises the first field (such as, the field 902 of Figure 15), the second field (such as, the field 904 of Figure 15) and third column position is (such as, the field 906 of Fig. 6), the wherein address of the first field record more new logical page, the second field stores the physical address of this more more new data of new logical page in order to record, and whether third column position is effective in order to mark this login.At this, if this logs on as effectively, then third column position such as can be marked as ' 1 '; And if this logs on as invalid, then third column position such as can be marked as ' 0 '.It must be appreciated, effectively log in the mode with bad login at this mark, be not limited thereto.Such as, also can ' 1 ' represent bad login and with ' 0 ' representative effectively log in.

Please refer to Figure 15, the chaotic district's search table 800 of universe comprises root unit 810 (0) ~ 810 (4), wherein the logical page (LPAGE) of logical block LBA (0) is corresponding root unit 810 (0), the logical page (LPAGE) of logical block LBA (1) is corresponding root unit 810 (1), the logical page (LPAGE) of logical block LBA (2) is corresponding root unit 810 (2), the logical page (LPAGE) of logical block LBA (3) is corresponding root unit 810 (3), and the logical page (LPAGE) of logical block LBA (4) is corresponding root unit 810 (4).

In the login link of root unit 810 (0), comprise 2 effectively log in, to record the 1st logical page (LPAGE) of logical block LBA (0) (namely, information " LBA (0)-1 ") and the 2nd logical page (LPAGE) is (namely, information " LBA (0)-2 ") be updated, wherein the more new data of the 1st logical page (LPAGE) of logical block LBA (0) is written into the 0th physics programming unit of physics erased cell 410 (5) (namely, information " 410 (5)-0 ") in and the more new data of the 2nd logical page (LPAGE) of logical block LBA (0) is written into the 2nd physics programming unit of physics erased cell 410 (6) (namely, information " 410 (6)-2 ") in.

In the login link of root unit 810 (1), comprise 1 effectively log in, to record the 0th logical page (LPAGE) of logical block LBA (1) (namely, information " LBA (1)-0 ") be updated, wherein the more new data of the 0th logical page (LPAGE) of logical block LBA (1) is written in the 1st the physics programming unit (that is, information " 410 (5)-1 ") of physics erased cell 410 (5).

In the login link of root unit 810 (2), comprise 1 effectively log in, to record the 1st logical page (LPAGE) of logical block LBA (2) (namely, information " LBA (2)-1 ") be updated, wherein the more new data of the 1st logical page (LPAGE) of logical block LBA (2) is written in the 2nd the physics programming unit (that is, information " 410 (5)-2 ") of physics erased cell 410 (5).

In the login link of root unit 810 (3), comprise 2 effectively log in, to record the 0th logical page (LPAGE) of logical block LBA (3) (namely, information " LBA (3)-0 ") and the 1st logical page (LPAGE) is (namely, information " LBA (3)-1 ") be updated, wherein the more new data of the 0th logical page (LPAGE) of logical block LBA (3) is written into the 0th physics programming unit of physics erased cell 410 (6) (namely, information " 410 (6)-0 ") in and the more new data of the 1st logical page (LPAGE) of logical block LBA (3) is written into the 1st physics programming unit of physics erased cell 410 (6) (namely, information " 410 (6)-1 ") in.

In addition, in the login link of root unit 810 (0) ~ 810 (4), 1 empty login can be comprised respectively, to represent the end logging in link.Such as, if when belonging to the data of logical block LBA (4) for searching in the chaotic physics erased cell of universe, the login that Memory Controller 104 (or memory management circuitry 202) only can be had time according to the login link of root unit 810 (4), and identify in the chaotic physics erased cell of universe and do not store the data belonging to logical block LBA (4), the direct basis logic information that turns physical address mapping table can read data from the physics programming unit of the physics erased cell of correspondence thus.

By that analogy, host computer system 1000 can write to as in the physics erased cell in the chaotic district of universe for the data stored by Memory Controller 104 (or memory management circuitry 202) in order.Particularly, when the number of the physics erased cell in the chaotic district of universe reaches 3, Memory Controller 104 (or memory management circuitry 202) can perform data consolidation procedure in the lump when performing write instruction, is exhausted to prevent the physics erased cell in idle district.

Please refer to Figure 16, continue Figure 14, suppose for programme again more new data UD7 and more new data UD7 is the 0th logical page (LPAGE) belonging to logical block LBA (2) time, because the chaotic physics erased cell 410 (6) of universe is without storage space, and reach 2 as the number of the physics erased cell in the chaotic district 550 of universe, therefore, memory management circuitry 202 can perform data consolidation procedure before execution write running.That is, in this example, in execution this time between write order period, memory management circuitry 202 can perform data consolidation procedure in the lump.

Such as, first, Memory Controller 104 (or memory management circuitry 202) can be selected logical block LBA (0) to carry out data merging.Now, memory management circuitry 202 can recognition logic unit LBA (0) be mapping physical erased cell 410 (0), from idle district 504 extracts physical erased cell 410 (7), and the valid data belonging to logical block LBA (0) in physics erased cell 410 (0) and the chaotic district 550 of universe are copied in physics erased cell 410 (7).Specifically, UD1 in data ID 1 in physics erased cell 410 (0), physics erased cell 410 (5) and the data UD6 in physics erased cell 410 (6) can write in 0th ~ 2 physics programming units of physics erased cell 410 (7) by Memory Controller 104 (or memory management circuitry 202) in order, and is denoted as invalid (as shown in oblique line) by the 2nd physics programming unit of the 0th of physics erased cell 410 (5) the physics programming unit and physics erased cell 410 (6).Afterwards, Memory Controller 104 (or memory management circuitry 202) can perform to physics erased cell 410 (0) running of erasing, turn in physical address mapping table in logic and logical block LBA (0) is remapped to physics erased cell 410 (7), and physics erased cell 410 (0) is associated to idle district 504.

Please refer to Figure 17, then, Memory Controller 104 (or memory management circuitry 202) can be selected logical block LBA (1) to carry out data merging.Now, memory management circuitry 202 can recognition logic unit LBA (1) be mapping physical erased cell 410 (1), from idle district 504 extracts physical erased cell 410 (8), and the valid data belonging to logical block LBA (1) in physics erased cell 410 (1) and the chaotic district 550 of universe are copied in physics erased cell 410 (8).Afterwards, Memory Controller 104 (or memory management circuitry 202) can perform to physics erased cell 410 (1) running of erasing, turn in physical address mapping table in logic and logical block LBA (1) is remapped to physics erased cell 410 (8), and physics erased cell 410 (1) is associated to idle district 504.

Please refer to Figure 18, then, Memory Controller 104 (or memory management circuitry 202) can be selected logical block LBA (2) to carry out data merging.Now, memory management circuitry 202 can recognition logic unit LBA (2) be mapping physical erased cell 410 (2), from idle district 504 extracts physical erased cell 410 (0), and the valid data belonging to logical block LBA (2) in physics erased cell 410 (2) and the chaotic district 550 of universe are copied in physics erased cell 410 (0).Afterwards, Memory Controller 104 (or memory management circuitry 202) can perform to physics erased cell 410 (2) running of erasing, turn in physical address mapping table in logic and logical block LBA (2) is remapped to physics erased cell 410 (0), and physics erased cell 410 (2) is associated to idle district 504.

Please refer to Figure 19, then, when Memory Controller 104 (or memory management circuitry 202) can select logical block LBA (3) to carry out data to merge, memory management circuitry 202 can recognition logic unit LBA (3) be mapping physical erased cell 410 (3), from idle district 504 extracts physical erased cell 410 (1), and the valid data belonging to logical block LBA (3) in physics erased cell 410 (3) and the chaotic district 550 of universe are copied in physics erased cell 410 (1).Afterwards, Memory Controller 104 (or memory management circuitry 202) can perform to physics erased cell 410 (3) running of erasing, turn in physical address mapping table in logic and logical block LBA (3) is remapped to physics erased cell 410 (1), and physics erased cell 410 (3) is associated to idle district 504.

Particularly, now, the data that the physics erased cell in the chaotic district 550 of universe stores are all invalid data, therefore, Memory Controller 104 (or memory management circuitry 202) can perform to erase to physics erased cell 410 (5) and 410 (6) and operate, and the physics erased cell 410 (5) after erasing is associated to idle district 504 (as shown in figure 20) with 410 (6), and the valid data completing the chaotic district 550 of universe thus merge running.

Please refer to Figure 21, after the valid data completing the chaotic district 550 of universe merge running, Memory Controller 104 (or memory management circuitry 202) can from idle district 504 extracts physical unit 410 (2) as the chaotic district 550 of universe physics erased cell and assign programming instruction with by this more new data UD7 write to the 0th physical page of physical location 410 (2).

Base this, according to above-mentioned running, the upper valid data of the physics erased cell in chaotic for universe district 550 can restore in the physics erased cell that logical block maps by Memory Controller 104 (or memory management circuitry 202), chaotic for the universe storing invalid data physics erased cell is associated go back to idle district 504, and from idle district 504, extract empty physics erased cell as the chaotic physics erased cell of universe, be less than higher limit with the number of the physics erased cell maintaining the chaotic district 550 of universe.

It is worth mentioning that, as mentioned above, when the data performing the chaotic district 550 of universe merge running, Memory Controller 104 (or memory management circuitry 202) need merge the valid data belonging to Different Logic unit, and more new logic turns physical address mapping table.Particularly, as mentioned above, due to the finite capacity of memory buffer 208, limited logic can only be loaded into and turn physical address mapping table, therefore, if when this little logical block belongs to different logic regions, Memory Controller 104 (or memory management circuitry 202) repeatedly need be loaded into and restore different logics and turn physical address mapping table, the data that can complete the chaotic district 550 of universe merge running, cause the execution postponing write instruction.Base this, in this exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) can record the scattered degree of data in the chaotic district 550 of current universe, and judges whether the scattered degree of data in the chaotic district 550 of current universe is less than the scattered degree threshold value of data.Particularly, only when the scattered degree of data in the chaotic district 550 of the current universe of correspondence is less than the scattered degree threshold value of these data, Memory Controller 104 (or memory management circuitry 202) just can use the chaotic district 550 of universe to store the data coming from host computer system 1000.

Such as, in the present invention one exemplary embodiment, the data that Memory Controller 104 (or memory management circuitry 202) can note down how many logic regions are stored in the chaotic district 550 of universe.Specifically, when the more new data of a logical page (LPAGE) being stored to universe confusion district 550, Memory Controller 104 (or memory management circuitry 202) can know that this logical page (LPAGE) belongs to that logical block (namely, upgrade logical block) and this logical block be belong to that logic region (namely, upgrade logic region), therefore, Memory Controller 104 (or memory management circuitry 202) can record the number (that is, having the data of how many logic regions to be stored in the chaotic district 550 of universe) having upgraded logic region at present.Particularly, if when the number having upgraded logic region is at present greater than preset value, Memory Controller 104 (or memory management circuitry 202) can identify that the scattered degree of data in the chaotic district 550 of current universe is non-and be less than the scattered degree threshold value of data.

It is worth mentioning that, to upgrade the number of logic region to judge that the scattered degree of data in the chaotic district 550 of universe is only an example, the present invention is not limited thereto.Such as, in another exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) also can upgrade the number of logical block to identify the scattered degree of data in the chaotic district 550 of universe.Such as, if when the number having upgraded logical block is at present greater than preset value, Memory Controller 104 (or memory management circuitry 202) can identify that the scattered degree of data in the chaotic district 550 of current universe is non-and be less than the scattered degree threshold value of data.

Moreover, during owing to merging running in the data performing the chaotic district 550 of universe, the corresponding logic having upgraded logical block need be upgraded and turn physical address mapping table (turning physical address mapping table hereinafter referred to as logic to be updated).Therefore, in another exemplary embodiment, Memory Controller 104 (or memory management circuitry 202) also logic to be updated can turn the number of physical address mapping table to identify the scattered degree of data in the chaotic district 550 of universe.Such as, if when the number that logic to be updated turns physical address mapping table is greater than preset value, Memory Controller 104 (or memory management circuitry 202) can identify that the scattered degree of data in the chaotic district 550 of current universe is non-and be less than the scattered degree threshold value of data.

In this exemplary embodiment, if the scattered degree of data in the corresponding chaotic district 550 of universe is at present non-when being less than the scattered degree threshold value of these data, Memory Controller 104 (or memory management circuitry 202) can use muon physics erased cell to write the data that come from host computer system 1000 and upgrade corresponding logic and turn physical address mapping table.

Figure 22 ~ Figure 24 illustrates the example using muon physics erased cell to write more new data.

Referring to Figure 22 ~ Figure 24, such as, under the mapping status mapping to physics erased cell 410 (0) at logical block LBA (0), when Memory Controller 104 (or memory management circuitry 202) receives write instruction and for write data to when belonging to the logical page (LPAGE) of logical block LBA (0) from host computer system 1000, it is map to physics erased cell 410 (0) and extracts physical erased cell 410 (H+1) is rotated physics erased cell 410 (0) from idle district 504 at present that Memory Controller 104 (or memory management circuitry 202) turns physical address mapping table recognition logic unit LBA (0) according to logic.But, while new data writes to physics erased cell 410 (H+1), all valid data in physics erased cell 410 (0) can be moved the physics erased cell 410 (0) of erasing to physics erased cell 410 (H+1) by Memory Controller 104 (or memory management circuitry 202) at once.Specifically, Memory Controller 104 (or memory management circuitry 202) can read for writing valid data before physics programming unit (that is, the data in the 0th physics programming unit of physics erased cell 410 (0) and the 1st physics programming unit) from physics erased cell 410 (0).Afterwards, Memory Controller 104 (or memory management circuitry 202) is understood in the 0th physics programming unit and the 1st physics programming unit that the wish valid data write before physics programming unit in physics erased cell 410 (0) are write to physics erased cell 410 (H+1) (as shown in figure 22), and is write to by new data in 2nd ~ 4 physics programming units of physics erased cell 410 (H+1) (as shown in figure 23).Now, Memory Controller 104 (or memory management circuitry 202) namely completes the running of write.Because the valid data in physics erased cell 410 (0) likely in next operation (such as, write instruction) in become invalid, therefore at once the valid data in physics erased cell 410 (0) are moved to physics erased cell 410 (H+1) and meaningless moving may be caused.In addition, data must write to the physics programming unit in physics erased cell in order, therefore, Memory Controller 104 (or memory management circuitry 202) can first move for write physics programming unit before valid data (namely, be stored in data in the 0th physics programming unit of physics erased cell 410 (0) and the 0th physics programming unit), and all the other valid data (that is, being stored in data in 5th ~ K physics programming unit of physics erased cell 410 (0)) wouldn't be moved.

In this exemplary embodiment, the running temporarily maintaining these transient state relations is called unlatching (open) mothers and sons physics erased cell, and original physical erased cell (such as, above-mentioned physics erased cell 410 (0)) be called parent substance reason erased cell and physics erased cell (such as, above-mentioned with physics erased cell 410 (H+1)) in order to replace parent substance reason erased cell is called muon physics erased cell.

Afterwards, when needing physics erased cell 410 (0) to merge (merge) with the data of physics erased cell 410 (H+1), Memory Controller 104 (or memory management circuitry 202) can by whole to physics erased cell 410 (0) and the data of physics erased cell 410 (H+1) and to a physics erased cell, promote the service efficiency of physics erased cell thus.At this, the running merging mother and sons' physics erased cell is called data consolidation procedure or closedown (close) mothers and sons physics erased cell.Such as, as shown in figure 24, when carrying out closedown mother and child blocks, (namely Memory Controller 104 (or memory management circuitry 202) can read remaining valid data from physics erased cell 410 (0), data in 5th ~ K physics programming unit of physics erased cell 410 (0)), remaining valid data in physics erased cell 410 (0) are write in the 5th physics programming unit ~ the K physics programming unit of physics erased cell 410 (H+1), erase operation for use is performed to physics erased cell 410 (0), physics erased cell 410 (0) after erasing is associated to idle district 504 and physics erased cell 410 (H+1) is associated to data field 502.That is, Memory Controller 104 (or memory management circuitry 202) to turn in physical address mapping table in logic and remaps logical block LBA (0) to physics erased cell 410 (H+1).It is worth mentioning that, in idle district 504, the number of physics erased cell is limited, base this, during memory storage apparatus 100 operates, the number of mother and sons' physics erased cell group of having opened also can be restricted.Therefore, when memory storage apparatus 100 receives the write instruction coming from host computer system 1000, if the number having opened mother and sons' physics erased cell group reaches in limited time, Memory Controller 104 just can perform this write instruction after need closing at least one group of mother and sons' physics erased cell group of having opened at present.

Figure 25 is the process flow diagram of the method for writing data illustrated according to the present invention one exemplary embodiment.

Please refer to Figure 25, in step S2501, at least one physics erased cell can be extracted the physics erased cell as the chaotic district 550 of universe from idle district 504.

In step S2503, the chaotic district's search table of universe can be established and be stored in memory buffer 208 to be recorded in the lastest imformation of corresponding multiple more new logical page in the chaotic district 550 of universe.

In step S2505, the write instruction of a logical page (LPAGE) (hereinafter referred to as the first logical page (LPAGE)) of instruction write data to logical block (hereinafter referred to as the first logical block) can be received with the corresponding more new data that this writes instruction.

In step S2507, the scattered degree of data in the chaotic district 550 of current universe can be recorded and be judged whether be less than the scattered degree threshold value of data.

If when at present the scattered degree of data in the chaotic district 550 of universe is less than data scattered degree threshold value, then in step S2509, this more new data to be written in the chaotic district 550 of universe and the lastest imformation of this first logical page (LPAGE) corresponding can be recorded in the chaotic district's search table of universe.Writing more new data has coordinated Fig. 8 ~ 15 to describe in detail as above to the chaotic district 550 of universe and the mode that records lastest imformation in the chaotic district's search table of universe, does not repeat them here.

If at present the scattered degree of data in the chaotic district 550 of universe is non-when being less than the scattered degree threshold value of data, then in step S2511, the muon physics erased cell that physics erased cell (hereinafter referred to as the first physics erased cell) can be extracted as corresponding first logical block from idle district 504 and more new data can be written in the muon physics erased cell of corresponding first logical block.The mode writing more new data with muon physics erased cell has coordinated Figure 22 ~ 24 to describe in detail as above, does not repeat them here.

It is worth mentioning that, if the chaotic district of universe has had when belonging at present for writing the logical block of more new data, more new data is write to the scattered degree of data that can't increase the chaotic district 550 of universe in the chaotic district 550 of universe, therefore, can directly will more new data stored in universe confusion district 550.Such as, in another exemplary embodiment of the present invention, before above-mentioned steps S2507, more can judge whether the chaotic district 550 of universe has the valid data belonging to the first logical block.Further, if when there are the valid data belonging to the first logical block in the chaotic district 550 of universe, step S2509 can be performed.If when there are not the valid data belonging to the first logical block in the chaotic district 550 of universe, just perform step S2507.

In sum, more new data can calculated the scattered degree of data in the chaotic district of universe by the method for writing data of exemplary embodiment of the present invention, Memory Controller and memory storage apparatus before writing to the chaotic district of universe, and and if only if the scattered degree of data in the chaotic district of universe is less than the scattered degree threshold value of data just will upgrade data temporary storage in the chaotic district of universe, can avoid expending when performing universe chaotic physics erased cell valid data and merging running the too much time thus turns physical address table in more new logic, and postpones the execution of write instruction.Therefore, the method for writing data of exemplary embodiment of the present invention, Memory Controller and memory storage apparatus can promote the usefulness that data write effectively.

Claims

1. a method for writing data, for writing data to reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple physics erased cell, each these physics erased cell has multiple physics programming unit, these physics erased cell are at least grouped into a data field and an idle district, the physics erased cell in this idle district is in order to replace the physics erased cell of this data field to write data, multiple logical block is configured to these physics erased cell mapping this data field, and each these logical block has multiple logical page (LPAGE), this method for writing data comprises:

At least one physics erased cell is extracted as the chaotic district of a universe from these physics erased cell in this idle district, wherein the chaotic district of this universe is in order to the temporary data belonging to multiple more new logical page, and these more new logical page to belong among these logical blocks multiple upgrades logical block;

Set up the chaotic district's search table of a universe to be recorded in multiple lastest imformations of these more new logical page corresponding in the chaotic district of this universe;

Receive a write instruction with to a more new data that should write instruction, wherein this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block among these logical blocks;

Record should the scattered degree of data in the chaotic district of universe;

Judge the scattered degree of these data in the chaotic district of universe whether being less than the scattered degree threshold value of data; And

If to should the scattered degree of these data in the chaotic district of universe be less than these data scattered degree threshold value time, by this more new data to write in the chaotic district of this universe and record should a lastest imformation of the first logical page (LPAGE) in the chaotic district's search table of this universe.

2. method for writing data as claimed in claim 1, also comprises:

If to should the scattered degree of these data in the chaotic district of universe is non-be less than these data scattered degree threshold value time, one first physics erased cell is extracted as to should a muon physics erased cell of the first logical block among these physics erased cell in this idle district, by this more new data write in this muon physics erased cell, and upgrade a logic of the first logical block turning physical address mapping table, wherein this muon physics erased cell is only in order to store the data belonging to this first logical block.

3. method for writing data as claimed in claim 1, also comprises:

These logical blocks are grouped into multiple logic region; And

Configure multiple logic and turn physical address mapping table to be assigned to these logic regions respectively, wherein these logics turn physical address mapping table in order to record multiple mapping relations between the logical block of these logic regions and the physics erased cell of this data field and each these logic turns physical address mapping table is configured independently to one of them of these logic regions.

4. method for writing data as claimed in claim 3, wherein these have upgraded multiple that logical block belongs among these logic regions and have upgraded logic region,

Wherein record should the step of the scattered degree of these data in the chaotic district of universe comprise:

Calculate the number that these have upgraded logic region; And

Record these numbers having upgraded logic region as to should the scattered degree of these data in the chaotic district of universe.

5. method for writing data as claimed in claim 1, wherein records should the step of the scattered degree of these data in the chaotic district of universe comprise:

Calculate the number that these have upgraded logical block; And

Record these numbers having upgraded logical block as to should the scattered degree of these data in the chaotic district of universe.

6. method for writing data as claimed in claim 1, wherein records should the step of the scattered degree of these data in the chaotic district of universe comprise:

Calculate the number that multiple logic to be updated turns physical address mapping table, wherein these logics to be updated turn physical address mapping table in order to the mapping between the physics erased cell that records these and upgraded logical block and this data field; And

Record number that these logics to be updated turn physical address mapping table as to should the scattered degree of these data in the chaotic district of universe.

7. method for writing data as claimed in claim 1, also comprises:

Judge whether there are the valid data belonging to this first logical block in the chaotic district of this universe; And

If when having the valid data belonging to this first logical block in the chaotic district of this universe, by this more new data write in the chaotic district of this universe,

Wherein above-mentioned judgement to should the scattered degree of these data in the chaotic district of the universe step that whether is less than the scattered degree threshold value of these data be and do not have the valid data belonging to this first logical block in the chaotic district of this universe time be performed.

8. a Memory Controller, for controlling a reproducible nonvolatile memorizer module, this Memory Controller comprises:

One host interface, in order to be electrically connected to a host computer system;

One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple physics erased cell, each these physics erased cell has multiple physics programming unit, these physics erased cell are at least grouped into a data field and an idle district, and the physics erased cell in this idle district is in order to replace the physics erased cell of this data field to write data; And

One memory management circuitry, is electrically connected to this host interface and this memory interface, and in order to configure multiple logical block to map these physics erased cell of this data field, wherein each these logical block has multiple logical page (LPAGE),

Wherein this memory management circuitry also in order to extract at least one physics erased cell as the chaotic district of a universe from these physics erased cell in this idle district, wherein the chaotic district of this universe is in order to the temporary data belonging to multiple more new logical page, and these more new logical page to belong among these logical blocks multiple upgrades logical block

Wherein this memory management circuitry is also in order to set up the chaotic district's search table of a universe to be recorded in multiple lastest imformations of these more new logical page corresponding in the chaotic district of this universe,

Wherein this memory management circuitry also in order to receive a write instruction with to a more new data that should write instruction, this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block among these logical blocks,

Wherein this memory management circuitry also in order to record to should the chaotic district of universe the scattered degree of data and judge the scattered degree of these data in universe confusion district whether being less than the scattered degree threshold value of data,

If wherein to should the scattered degree of these data in the chaotic district of universe be less than these data scattered degree threshold value time, this memory management circuitry by this more new data to write in the chaotic district of this universe and record should a lastest imformation of the first logical page (LPAGE) in the chaotic district's search table of this universe.

9. Memory Controller as claimed in claim 8, if wherein to should the scattered degree of these data in the chaotic district of universe is non-be less than these data scattered degree threshold value time, this memory management circuitry extracts one first physics erased cell as to should a muon physics erased cell of the first logical block among these physics erased cell in this idle district, by this more new data write in this muon physics erased cell, and upgrade a logic of the first logical block turning physical address mapping table

Wherein this muon physics erased cell is only in order to store the data belonging to this first logical block.

10. Memory Controller as claimed in claim 8, wherein this memory management circuitry also turns physical address mapping table to be assigned to these logic regions respectively in order to these logical blocks are grouped into multiple logic region and configure multiple logic,

Wherein these logics turn physical address mapping table in order to record multiple mapping relations between the logical block of these logic regions and the physics erased cell of this data field and each these logic turns physical address mapping table is configured independently to one of them of these logic regions.

11. Memory Controllers as claimed in claim 10, wherein these have upgraded multiple that logical block belongs among these logic regions and have upgraded logic region,

Wherein record to should the chaotic district of universe the scattered degree of these data running in, this memory management circuitry calculates these numbers having upgraded logic region and records these numbers having upgraded logic region as to should the scattered degree of these data in the chaotic district of universe.

12. Memory Controllers as claimed in claim 8, wherein record to should the chaotic district of universe the scattered degree of these data running in, this memory management circuitry calculates these numbers having upgraded logical block and records these numbers having upgraded logical block as to should the scattered degree of these data in the chaotic district of universe.

13. Memory Controllers as claimed in claim 8, wherein record to should the chaotic district of universe the scattered degree of these data running in, this memory management circuitry calculates multiple logic to be updated and turns the number of physical address mapping table and record number that these logics to be updated turn physical address mapping table as to should the scattered degree of these data in the chaotic district of universe

Wherein these logics to be updated turn physical address mapping table in order to the mapping between the physics erased cell that records these and upgraded logical block and this data field.

14. Memory Controllers as claimed in claim 8, wherein this memory management circuitry is also in order to judge whether there are the valid data belonging to this first logical block in the chaotic district of this universe,

If when wherein having the valid data belonging to this first logical block in the chaotic district of this universe, this memory management circuitry by this more new data write in the chaotic district of this universe,

Above-mentioned judgement is performed to the scattered degree of these data in the chaotic district of universe whether being less than the running of these data scattered degree threshold value when wherein this memory management circuitry is and does not have the valid data belonging to this first logical block in the chaotic district of this universe.

15. 1 kinds of memory storage apparatus, comprising:

A connector, in order to be electrically connected to a host computer system;

One reproducible nonvolatile memorizer module, there is multiple physics erased cell, each these physics erased cell has multiple physics programming unit, these physics erased cell are at least grouped into a data field and an idle district, and the physics erased cell in this idle district is in order to replace the physics erased cell of this data field to write data; And

One Memory Controller, is electrically connected to this connector and this reproducible nonvolatile memorizer module, and in order to configure multiple logical block to map these physics erased cell of this data field, wherein each these logical block has multiple logical page (LPAGE),

Wherein this Memory Controller also in order to extract at least one physics erased cell as the chaotic district of a universe from these physics erased cell in this idle district, wherein the chaotic district of this universe is in order to the temporary data belonging to multiple more new logical page, and these more new logical page to belong among these logical blocks multiple upgrades logical block

Wherein this Memory Controller is also in order to set up the chaotic district's search table of a universe to be recorded in multiple lastest imformations of these more new logical page corresponding in the chaotic district of this universe,

Wherein this Memory Controller also in order to receive a write instruction with to a more new data that should write instruction, this more new data be belong to one first logical page (LPAGE) and this first logical page (LPAGE) belongs to one first logical block among these logical blocks,

Wherein this Memory Controller also in order to record to should the chaotic district of universe the scattered degree of data and judge the scattered degree of these data in universe confusion district whether being less than the scattered degree threshold value of data,

If wherein to should the scattered degree of these data in the chaotic district of universe be less than these data scattered degree threshold value time, this Memory Controller by this more new data to write in the chaotic district of this universe and record should a lastest imformation of the first logical page (LPAGE) in the chaotic district's search table of this universe.

16. memory storage apparatus as claimed in claim 15, if wherein to should the scattered degree of these data in the chaotic district of universe is non-be less than these data scattered degree threshold value time, this Memory Controller extracts one first physics erased cell as to should a muon physics erased cell of the first logical block among these physics erased cell in this idle district, by this more new data write in this muon physics erased cell, and upgrade a logic of the first logical block turning physical address mapping table

17. memory storage apparatus as claimed in claim 15, wherein this Memory Controller also turns physical address mapping table to be assigned to these logic regions respectively in order to these logical blocks are grouped into multiple logic region and configure multiple logic,

18. memory storage apparatus as claimed in claim 17, wherein these have upgraded multiple that logical block belongs among these logic regions and have upgraded logic region,

Wherein record to should the chaotic district of universe the scattered degree of these data running in, this Memory Controller calculates these numbers having upgraded logic region and records these numbers having upgraded logic region as to should the scattered degree of these data in the chaotic district of universe.

19. memory storage apparatus as claimed in claim 15, wherein record to should the chaotic district of universe the scattered degree of these data running in, this Memory Controller calculates these numbers having upgraded logical block and records these numbers having upgraded logical block as to should the scattered degree of these data in the chaotic district of universe.

20. memory storage apparatus as claimed in claim 15, wherein record to should the chaotic district of universe the scattered degree of these data running in, this Memory Controller calculates multiple logic to be updated and turns the number of physical address mapping table and record number that these logics to be updated turn physical address mapping table as to should the scattered degree of these data in the chaotic district of universe

21. memory storage apparatus as claimed in claim 15, wherein this Memory Controller is also in order to judge whether there are the valid data belonging to this first logical block in the chaotic district of this universe,

If when wherein having the valid data belonging to this first logical block in the chaotic district of this universe, this Memory Controller by this more new data write in the chaotic district of this universe,

Above-mentioned judgement is performed to the scattered degree of these data in the chaotic district of universe whether being less than the running of these data scattered degree threshold value when wherein this Memory Controller is and does not have the valid data belonging to this first logical block in the chaotic district of this universe.