CN104636267A - Storage control method, storage storing device and storage control circuit unit - Google Patents
Storage control method, storage storing device and storage control circuit unit Download PDFInfo
- Publication number
- CN104636267A CN104636267A CN201310558040.3A CN201310558040A CN104636267A CN 104636267 A CN104636267 A CN 104636267A CN 201310558040 A CN201310558040 A CN 201310558040A CN 104636267 A CN104636267 A CN 104636267A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- data
- reproducible nonvolatile
- read
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a storage control method, a storage storing device and a storage control circuit unit. The storage control method comprises the steps that a first time pulse signal is provided for a copiable nonvolatile storage module, and first data in the copiable nonvolatile storage module are read according to the first time pulse signal; a second time pulse signal is provided for the copiable nonvolatile storage module, and second data are written into the copiable nonvolatile storage module according to the second time pulse signal, wherein the frequency of the second time pulse signal is different from that of the first time pulse signal. Accordingly, the operation speed of the copiable nonvolatile storage module can be increased, and the probability of operation errors can be lowered.
Description
Technical field
The invention relates to a kind of memory control methods, and relate to the memory control methods of reproducible nonvolatile memorizer module, memory storage apparatus and memorizer control circuit unit especially.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, and the demand of consumer to medium is also increased rapidly.Due to reproducible nonvolatile memorizer module (such as, flash memory) there is data non-volatile, power saving, volume are little, and the characteristic such as mechanical structure, so be built in above-mentioned illustrated various portable multimedia devices in being applicable to very much.
In general, reproducible nonvolatile memorizer module is controlled by a memorizer control circuit unit.This memorizer control circuit unit can provide clock signal to reproducible nonvolatile memorizer module, and reproducible nonvolatile memorizer module can operate according to this clock signal by this.If the frequency of clock signal is higher, then the speed of reproducible nonvolatile memorizer module running can be faster, but the probability made a mistake when carrying out certain operations (such as, write) also can promote, and thus may produce non-response mistake.But, if the frequency of clock signal is lower, then reproducible nonvolatile memorizer module perform these operation speed can reduce.Therefore, how when pulling speed, reduce again the probability that certain operations makes a mistake, for this reason the subject under discussion be concerned about of those skilled in the art.
Summary of the invention
The invention provides a kind of memory control methods, memory storage apparatus and memorizer control circuit unit, the operating speed of reproducible nonvolatile memorizer module can be promoted, and the probability that certain operations makes a mistake can be reduced.
The present invention one exemplary embodiment proposes a kind of memory control methods, for a reproducible nonvolatile memorizer module.The method comprises: provide the first clock signal to reproducible nonvolatile memorizer module, and reads the first data in reproducible nonvolatile memorizer module according to the first clock signal; There is provided the second clock signal to reproducible nonvolatile memorizer module, and according to the second clock signal, the second data are write in reproducible nonvolatile memorizer module.Wherein the frequency of the second clock signal is different from the frequency of the first clock signal.
In an exemplary embodiment, the frequency of above-mentioned second clock signal is less than the frequency of the first clock signal.
In an exemplary embodiment, above-mentioned memory control methods also comprises: receive the first instruction from host computer system; If the first instruction is reading command, described in execution, provide the step of the first clock signal; And if the first instruction is write instruction, provides the step of the second clock signal described in execution.
In an exemplary embodiment, above-mentioned reproducible nonvolatile memorizer module comprises multiple entity erased cell.These entity erased cell are at least divided into data field and system region, and the first above-mentioned data are stored in data field.This memory control methods also comprises: provide the second clock signal to reproducible nonvolatile memorizer module, and according to the 3rd data in the second clock signal reading system district.
In an exemplary embodiment, above-mentioned memory control methods also comprises: judge that whether the first data are wrong according to an error correcting code or a bug check code, and judges whether a read error number of times meets critical condition; If the first data are wrong and read error number of times does not meet critical condition, again read the first data according to the first clock signal and upgrade read error number of times; If the first data are wrong and read error number of times meets critical condition, provide the second clock signal to reproducible nonvolatile memorizer module, and read the first data according to the second clock signal.
In an exemplary embodiment, above-mentionedly judge that the whether vicious step of the first data comprises according to error correcting code or bug check code: judge that whether the first data are wrong according to error correcting code; And if judge that the first data do not have mistake according to error correcting code, judge that whether the first data wrong according to bug check code.
In an exemplary embodiment, above-mentioned reproducible nonvolatile memorizer module is electrically connected to multiple passage.Above-mentioned memory control methods also comprises: for each passage, the read error number of times that record is corresponding.
The present invention one exemplary embodiment proposes a kind of memory storage apparatus, comprise connecting interface unit, above-mentioned reproducible nonvolatile memorizer module, with memorizer control circuit unit.Connecting interface unit is electrically connected to host computer system.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, in order to provide the first clock signal to reproducible nonvolatile memorizer module, and read the first data in reproducible nonvolatile memorizer module according to the first clock signal.Second data also in order to provide the second clock signal to reproducible nonvolatile memorizer module, and write in reproducible nonvolatile memorizer module according to the second clock signal by memorizer control circuit unit.The frequency of the second clock signal is different from the frequency of the first clock signal.
In an exemplary embodiment, above-mentioned memorizer control circuit unit is also in order to receive the first instruction from host computer system.If the first instruction is reading command, memorizer control circuit unit is in order to provide the first clock signal.If the first instruction is write instruction, memorizer control circuit unit is in order to provide the second clock signal.
In an exemplary embodiment, above-mentioned entity erased cell is at least divided into data field and system region, and the first data are stored in data field.Memorizer control circuit unit also in order to provide the second clock signal to reproducible nonvolatile memorizer module, and according to the 3rd data in the second clock signal reading system district.
In an exemplary embodiment, above-mentioned memorizer control circuit unit also in order to judge that whether the first data are wrong according to error correcting code or bug check code, and judges whether a read error number of times meets critical condition.If the first data are wrong and read error number of times does not meet critical condition, memorizer control circuit unit is in order to again to read the first data according to the first clock signal and to upgrade read error number of times.If the first data are wrong and read error number of times meets critical condition, memorizer control circuit unit in order to provide the second clock signal to reproducible nonvolatile memorizer module, and reads the first data according to the second clock signal.
In an exemplary embodiment, according to error correcting code or bug check code, above-mentioned memorizer control circuit unit judges that the whether vicious operation of the first data comprises following operation.According to error correcting code, memorizer control circuit unit judges that whether the first data are wrong.If judge that the first data do not have mistake according to error correcting code, according to bug check code, memorizer control circuit unit judges that whether the first data are wrong.
In an exemplary embodiment, above-mentioned reproducible nonvolatile memorizer module is electrically connected to memorizer control circuit unit by multiple passage.Memorizer control circuit unit also in order to for each passage, records corresponding read error number of times.
The present invention one exemplary embodiment proposes a kind of memorizer control circuit unit, for controlling above-mentioned reproducible nonvolatile memorizer module.This memorizer control circuit unit comprises host interface, memory interface, memory management circuitry and clock generating circuit.Host interface is electrically connected to host computer system.Memory interface is electrically connected to reproducible nonvolatile memorizer module.Memory management circuitry is electrically connected to host interface and memory interface.Clock generating circuit provides the first clock signal or the second clock signal to reproducible nonvolatile memorizer module.Memory management circuitry is in order to read the first data in reproducible nonvolatile memorizer module according to the first clock signal.Memory management circuitry is also in order to write to the second data in reproducible nonvolatile memorizer module according to the second clock signal.Wherein the frequency of the second clock signal is different from the frequency of the first clock signal.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to receive the first instruction from host computer system.If the first instruction is reading command, clock generating circuit is in order to provide the first clock signal.If the first instruction is write instruction, clock generating circuit is in order to provide the second clock signal.
In an exemplary embodiment, above-mentioned entity erased cell is at least divided into data field and system region, and the first data are stored in data field.Memory management circuitry is also in order to according to the 3rd data in the second clock signal reading system district.
In an exemplary embodiment, above-mentioned memory management circuitry also in order to judge that whether the first data are wrong according to error correcting code or bug check code, and judges whether a read error number of times meets critical condition.If the first data are wrong and read error number of times does not meet critical condition, memory management circuitry is in order to again to read the first data according to the first clock signal and to upgrade read error number of times.If the first data are wrong and read error number of times meets critical condition, memory management circuitry is in order to read the first data according to the second clock signal.
In an exemplary embodiment, according to error correcting code or bug check code, above-mentioned memory management circuitry judges that the whether vicious operation of the first data comprises following operation.According to error correcting code, memory management circuitry judges that whether the first data are wrong.If judge that the first data do not have mistake according to error correcting code, according to bug check code, memory management circuitry judges that whether the first data are wrong.
In an exemplary embodiment, above-mentioned reproducible nonvolatile memorizer module is electrically connected to memorizer control circuit unit by multiple passage.Memory management circuitry also in order to for each passage, records corresponding read error number of times.
The present invention one exemplary embodiment proposes a kind of memory control methods, for reproducible nonvolatile memorizer module.Entity program unit in reproducible nonvolatile memorizer module is divided into data field, idle district and system region.This memory control methods comprises: provide the first clock signal to reproducible nonvolatile memorizer module, and applies the first clock signal to the data field of reproducible nonvolatile memorizer module or idle district execution first operation.There is provided the second clock signal to reproducible nonvolatile memorizer module, and apply the second clock signal to the data field of reproducible nonvolatile memorizer module or idle district execution second operation.Wherein the frequency of the first clock signal is different from the frequency of the second clock signal.
In an exemplary embodiment, the frequency of above-mentioned second clock signal is less than the frequency of the first clock signal, and first is operating as read operation, and second is operating as write operation.
In an exemplary embodiment, the frequency of above-mentioned second clock signal is less than the frequency of the first clock signal, and user's data are read in the first operation, and physical address mapping table is read in the second operation.
In an exemplary embodiment, the frequency of above-mentioned second clock signal is less than the frequency of the first clock signal, and the first data are read in the first operation, and the second operation is in order to read the first data again when the first data are wrong.
In an exemplary embodiment, the system data non-memory of reproducible nonvolatile memorizer module is in data field or idle district, and the entity program unit in system region is without the logical address mapped in the physical address mapping table of memory storage apparatus.
The present invention one exemplary embodiment proposes a kind of memory storage apparatus, comprises connecting interface unit, above-mentioned reproducible nonvolatile memorizer module and memorizer control circuit unit.Connecting interface unit is electrically connected to host computer system.Memorizer control circuit unit is electrically connected to connecting interface unit and reproducible nonvolatile memorizer module, in order to provide the first clock signal to reproducible nonvolatile memorizer module, and apply the first clock signal to the data field of reproducible nonvolatile memorizer module or idle district execution first operation.Memorizer control circuit unit also in order to provide the second clock signal to reproducible nonvolatile memorizer module, and applies the second clock signal to the data field of reproducible nonvolatile memorizer module or idle district execution second operation.Wherein the frequency of the first clock signal is different from the frequency of the second clock signal.
Based on above-mentioned, the memory control methods that exemplary embodiment of the present invention proposes, memory storage apparatus and memorizer control circuit unit, can provide the clock signal of different frequency to reproducible nonvolatile memorizer module.By this, the operating speed of reproducible nonvolatile memorizer module can be promoted in some cases, and the probability operating and make a mistake can be reduced in other cases.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and shown in coordinating, accompanying drawing is described in detail below.
Accompanying drawing explanation
Figure 1A is host computer system shown by an exemplary embodiment and memory storage apparatus;
Figure 1B is the schematic diagram of computer, input/output device and memory storage apparatus shown by an exemplary embodiment;
Fig. 1 C is the schematic diagram of host computer system shown by an exemplary embodiment and memory storage apparatus;
Fig. 2 illustrates the schematic diagram of the memory storage apparatus shown in Figure 1A;
Fig. 3 is the schematic diagram of memorizer control circuit unit shown by an exemplary embodiment;
Fig. 4 is the example schematic managing reproducible nonvolatile memorizer module shown by an exemplary embodiment;
Fig. 5 illustrates according to an exemplary embodiment process flow diagram judging use first clock signal or the second clock signal.
Description of reference numerals:
1000: host computer system;
1100: computer;
1102: microprocessor;
1104: random access memory;
1106: input/output device;
1108: system universal serial bus;
1110: data transmission interface;
1202: mouse;
1204: keyboard;
1206: display;
1208: printer;
1212: portable disk;
1214: storage card;
1216: solid state hard disc;
1310: digital camera;
1312:SD card;
1314:MMC card;
1316: memory stick;
1318:CF card;
1320: embedded memory storage;
100: memory storage apparatus;
102: connecting interface unit;
104: memorizer control circuit unit;
106: reproducible nonvolatile memorizer module;
304 (0) ~ 304 (R): entity erased cell;
202: memory management circuitry;
204: host interface;
206: memory interface;
252: memory buffer;
254: electric power management circuit;
256: bug check and correcting circuit;
258: clock generating circuit;
402: data field;
404: idle district;
406: system region;
410 (0) ~ 410 (D): logical address;
S501 ~ S505: step.
Embodiment
[the first exemplary embodiment]
Generally speaking, memory storage apparatus (also claiming, storage system) comprises reproducible nonvolatile memorizer module and controller (also claiming, control circuit).Usual memory storage apparatus uses together with host computer system, data can be write to memory storage apparatus or read data from memory storage apparatus to make host computer system.
Figure 1A is host computer system shown by an exemplary embodiment and memory storage apparatus.Figure 1B is the schematic diagram of computer, input/output device and memory storage apparatus shown by an exemplary embodiment.Fig. 1 C is the schematic diagram of host computer system shown by an exemplary embodiment and memory storage apparatus.
Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100, and (input/output is called for short: I/O) device 1106 with I/O.RAM) 1104, system universal serial bus 1108 and data transmission interface 1110 computer 1100 comprises microprocessor 1102, (random access memory is called for short: random access memory.Input/output device 1106 comprises as the mouse 1202 of Figure 1B, keyboard 1204, display 1206 and printer 1208.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.
In embodiments of the present invention, memory storage apparatus 100 is electrically connected by data transmission interface 1110 other elements with host computer system 1000.Data can be write to memory storage apparatus 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106 or read data from memory storage apparatus 100.Such as, memory storage apparatus 100 can be that (Solid State Drive is called for short: SSD) the type nonvolatile memory storage of 1216 grades for portable disk 1212 as shown in Figure 1B, storage card 1214 or solid state hard disc.
Generally speaking, host computer system 1000 is any system that can coordinate to store data substantially with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 explains with computer system, but host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile memory storage is then its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded memory storage 1320 (as shown in Figure 1 C).Embedded memory storage 1320 comprises embedded multi-media card, and (Embedded MMC is called for short: eMMC).It is worth mentioning that, embedded multi-media card is directly electrically connected on the substrate of host computer system.
Fig. 2 illustrates the schematic diagram of the memory storage apparatus shown in Figure 1A.
Please refer to Fig. 2, memory storage apparatus 100 comprises connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.
In this exemplary embodiment, connecting interface unit 102 is that (Serial Advanced Technology Attachment is called for short: SATA) standard Serial Advanced Technology Attachment.But, it must be appreciated, the present invention is not limited thereto, connecting interface unit 102 also can be meet parallel advanced technology annex (Parallel Advanced Technology Attachment, be called for short: PATA) standard, Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronic Engineers, be called for short: IEEE) 1394 standards, high-speed peripheral interconnecting interface (Peripheral Component Interconnect Express, be called for short: PCI Express) standard, USB (universal serial bus) (Universal Serial Bus, be called for short: USB) standard, safe digital (Secure Digital, be called for short: SD) interface standard, a hypervelocity generation (Ultra High Speed-I, be called for short: UHS-I) interface standard, hypervelocity two generation (Ultra High Speed-II, be called for short: UHS-II) interface standard, memory stick (Memory Stick, be called for short: MS) interface standard, multimedia storage card (Multi Media Card, be called for short: MMC) interface standard, down enters formula multimedia storage card (Embedded Multimedia Card, be called for short: eMMC) interface standard, general flash memory (Universal Flash Storage, be called for short: UFS) interface standard, compact flash (Compact Flash, be called for short: CF) interface standard, ide interface (Integrated Device Electronics, be called for short: IDE) standard or other standards be applicable to.Connecting interface unit 102 can be encapsulated in a chip with memorizer control circuit unit 104, or connecting interface unit 102 is laid in one to comprise outside memorizer control circuit unit 104 chip.
Memorizer control circuit unit 104 in order to perform in the form of hardware or multiple logic gate of form of firmware implementation or steering order, and according to the instruction of host computer system 1000 carry out in reproducible nonvolatile memorizer module 106 data write, read and the running such as to erase.
Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to data that host system 1000 writes.Reproducible nonvolatile memorizer module 106 has entity erased cell 304 (0) ~ 304 (R).Such as, entity erased cell 304 (0) ~ 304 (R) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each entity erased cell has a plurality of entity program unit respectively, and the entity program unit belonging to same entity erased cell can be written independently and side by side be erased.Such as, each entity erased cell is made up of 128 entity program unit.But it must be appreciated, the present invention is not limited thereto, each entity erased cell can be made up of 64 entity program unit, 256 entity program unit or other any entity program unit.
More particularly, each entity erased cell comprises many character lines and many bit lines, and each character line and each bit line infall are configured with a memory cell.Each memory cell can store one or more bit.In same entity erased cell, all memory cells can be erased together.In this exemplary embodiment, entity erased cell is the least unit of erasing.That is, each entity erased cell contain minimal amount in the lump by the memory cell of erasing.Such as, entity erased cell is physical blocks.On the other hand, the memory cell on same character line can form one or more entity program unit.If each memory cell can store the bit of more than 2, then the entity program unit on same character line can be classified as lower entity program unit and upper entity program unit.In general, the writing speed of lower entity program unit can be greater than the writing speed of entity program unit.In this exemplary embodiment, entity program unit is the minimum unit of sequencing.That is, entity program unit is the minimum unit of write data.Such as, entity program unit is physical page or entity fan (sector).If entity program unit is physical page, then each entity program unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises multiple entity fan, and in order to store the data of user, and redundancy ratio special zone is in order to the data (such as, error correcting code) of storage system.In this exemplary embodiment, each data bit district comprises 32 entity fans, and the size of an entity fan is 512 bytes (byte, B).But, in other exemplary embodiment, also can comprise in data bit district 8,16 or number more or less entity fan, the present invention do not limit entity fan size and number.
In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is that (Multi Level Cell is called for short: MLC) NAND type flash memory module, namely can store at least 2 bits in a memory cell multilayer memory cell.But, the present invention is not limited thereto, reproducible nonvolatile memorizer module 106 may also be individual layer memory cell (Single Level Cell, be called for short: SLC) NAND type flash memory module, plural layer memory cell (Trinary Level Cell, be called for short: TLC) NAND type flash memory module, other flash memory module or other there is the memory module of identical characteristics.
In this exemplary embodiment, memorizer control circuit unit 104 is electrically connected to reproducible nonvolatile memorizer module 106 by multiple passage (channel).Each passage is the entity erased cell 304 (0) ~ 304 (R) being electrically connected to part.Operation on these passages is independent of each other.For example, when memorizer control circuit unit 104 performs write operation on a passage, read operation can be performed on another passage simultaneously.But the number of the present invention's not limiting channel, also not limiting each passage is be electrically connected to which entity erased cell.In another exemplary embodiment, only have a passage between memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106, the present invention is also not subject to the limits.
Fig. 3 is the schematic diagram of memorizer control circuit unit shown by an exemplary embodiment.
Please refer to Fig. 3, memorizer control circuit unit 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.
Memory management circuitry 202 is in order to the overall operation of control store control circuit unit 104.Specifically, memory management circuitry 202 has multiple steering order, and when memory storage apparatus 100 operates, this little steering order can be performed to carry out data write, read and the running such as to erase.When the operation of memory management circuitry 202 is below described, be equal to the operation that memorizer control circuit unit 104 is described, below and repeat no more.
In this exemplary embodiment, the steering order of memory management circuitry 202 carrys out implementation with form of firmware.Such as, memory management circuitry 202 has microprocessor unit (not shown) and ROM (read-only memory) (not shown), and this little steering order is burned onto in this ROM (read-only memory).When memory storage apparatus 100 operates, this little steering order can by microprocessor unit perform to carry out data write, read and the running such as to erase.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also can procedure code form be stored in the specific region (such as, being exclusively used in the system region of storage system data in memory module) of reproducible nonvolatile memorizer module 106.In addition, memory management circuitry 202 has microprocessor unit (not shown), ROM (read-only memory) (not shown) and random access memory (not shown).Particularly, this ROM (read-only memory) has boot code (boot code), and when memorizer control circuit unit 104 is enabled, microprocessor unit first can perform this boot code and the steering order be stored in reproducible nonvolatile memorizer module 106 is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate this little steering order with carry out data write, read and the running such as to erase.
In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 also an example, in hardware can carry out implementation.Such as, memory management circuitry 202 comprises microcontroller, Memory Management Unit, storer writing unit, storer reading unit, storer erased cell and data processing unit.Memory Management Unit, storer writing unit, storer reading unit, storer erased cell and data processing unit are electrically connected to microcontroller.Wherein, Memory Management Unit is in order to manage the entity erased cell of reproducible nonvolatile memorizer module 106; Storer writing unit is in order to assign write instruction data to be write in reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer reading unit is in order to assign reading command to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; Storer erased cell is in order to assign instruction of erasing data to be erased from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106; And data processing unit is in order to the data processed for writing to reproducible nonvolatile memorizer module 106 and the data read from reproducible nonvolatile memorizer module 106.
Host interface 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify the instruction that transmits of host computer system 1000 and data.That is, the instruction that transmits of host computer system 1000 and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is compatible with SATA standard.But, it must be appreciated and the present invention is not limited thereto, host interface 204 also can be compatible with PATA standard, IEEE1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards be applicable to.
Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.That is, the data for writing to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 via memory interface 206.
In the present invention one exemplary embodiment, memorizer control circuit unit 104 also comprises memory buffer 252, electric power management circuit 254, bug check and correcting circuit 256 and clock generating circuit 258.
Memory buffer 252 is electrically connected to memory management circuitry 202 and comes from the data and instruction of host computer system 1000 in order to temporary or come from the data of reproducible nonvolatile memorizer module 106.
Electric power management circuit 254 is electrically connected to memory management circuitry 202 and in order to the power supply of control store memory storage 100.
Bug check and correcting circuit 256 are electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, bug check and correcting circuit 256 can be that the corresponding data that this writes instruction produce corresponding error correcting code (error correcting code, be called for short: ECC), and the data of this write instruction corresponding can write in reproducible nonvolatile memorizer module 106 with corresponding error correcting code by memory management circuitry 202.Afterwards, can read error correcting code corresponding to these data when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, and bug check and correcting circuit 256 can according to this error correcting code to read data execution error inspection and correction programs simultaneously.
Clock generating circuit 258 produces clock signal to allow memory management circuitry 202 to access reproducible nonvolatile memorizer module 106.Specifically, the clock signal that clock generating circuit 258 produces can be supplied to reproducible nonvolatile memorizer module 106, and reproducible nonvolatile memorizer module 106 can perform reading, write or other operations according to this clock signal.When the frequency of provided clock signal is larger, the running speed of reproducible nonvolatile memorizer module 106 also can be faster.In an exemplary embodiment, the clock signal that clock generating circuit 258 produces also can be supplied to other circuit in memorizer control circuit unit 104, and these circuit are also operate according to provided clock signal by this.In this exemplary embodiment, clock generating circuit 258 can provide the clock signal of two or more different frequency.Such as, one or more oscillator is included in clock generating circuit 258, and these oscillators can be the oscillators of hartley (Hartley) oscillator, Ke Bizi (Colpitts) oscillator, carat general (Clapp) oscillator, phase shift (phase-shift) oscillator, RC oscillator, LC oscillator or other kinds, the present invention is also not subject to the limits.
Fig. 4 is the example schematic managing reproducible nonvolatile memorizer module shown by an exemplary embodiment.
It must be appreciated, when this describes the running of entity erased cell of reproducible nonvolatile memorizer module 106, carrying out application entity erased cell with the word such as " extraction ", " division ", " association " is concept in logic.That is, the physical location of the entity erased cell of reproducible nonvolatile memorizer module is not changed, but operates the entity erased cell of reproducible nonvolatile memorizer module in logic.
Please refer to Fig. 4, the entity erased cell 304 (0) ~ 304 (R) of reproducible nonvolatile memorizer module can be logically divided into multiple region by memory management circuitry 202, such as, be data field 402, idle district 404 and system region 406.That is the entity program unit in entity erased cell 304 (0) ~ 304 (R) is also divided into data field 402, idle district 404 and system region 406.
The entity erased cell of data field 402 is the data in order to store from host computer system 1000.The entity erased cell in idle district 404 is in order to the working area as data field 402.For example, if host computer system 1000 will upgrade the data in data field 402, then these data can first be written in idle district 404, and these data can be moved and merge to data field 402 or with the data in data field 402 afterwards.Or the entity erased cell in idle district 404 also can be used to the entity erased cell of replacement data district 402 and system region 406.That is, when (namely the entity erased cell in data field 402 with system region 406 is damaged, become bad entity erased cell (bad physical erasing unit)) time, the entity erased cell in idle district 404 can be used to replace this bad entity erased cell.If in idle district 404 without normal entity erased cell and when having entity erased cell to damage; then whole memory storage apparatus 100 can be declared as write protection (write protect) state by Memory Controller 104, and cannot write data again.In another exemplary embodiment, memory management circuitry 202 can mark off one again and replace district, and deposit the entity erased cell for replacing bad entity erased cell specially, the present invention is also not subject to the limits.
The entity erased cell of system region 406 is in order to register system data, wherein this system data comprises the identification code of reproducible nonvolatile memorizer module 106, provides the identity of host computer system 1000 in order to identification memory storage apparatus 100 and the relevant information etc. of specification about manufacturer and the model of memory chip, the capacity (entity erased cell number) of memory chip, the entity program unit number of manufacturer's information, each entity erased cell or memory storage apparatus 100 on being connected during host computer system 1000.It should be noted that these system datas can not be stored in data field 402 or idle district 404.
Data field 402, idle district 404 can be different according to different storer specifications from the quantity of the entity erased cell of system region 406.In addition, it must be appreciated, in the running of memory storage apparatus 100, entity erased cell is associated to data field 402, idle district 404 and can dynamically changes with the grouping relation of system region 406.Such as, when when the entity erased cell in data field 402 damages, the entity erased cell in idle district 404 replaces, then the entity erased cell in original idle district 404 can be associated to data field 402.
Memory management circuitry 202 meeting configuration logic address 410 (0) ~ 410 (D) is to map to the entity erased cell 304 (0) ~ 304 (A) in data field 402.Host computer system 1000 is the data come by logical address 410 (0) ~ 410 (D) in access data district 402.In this exemplary embodiment, logical address maps to an entity storage unit (an entity storage unit represents a physical address, such as entity fan), multiple logical address can form a logical program unit, and multiple logical program unit can form a logic erased cell.A logical program unit maps to one or more entity program unit, and a logic erased cell maps to one or more entity erased cell.
In this exemplary embodiment, memory management circuitry 202 is with logic erased cell to manage reproducible nonvolatile memorizer module 106, and therefore memory management circuitry 202 can set up a physical address mapping table to record the mapping relations between logic erased cell and entity erased cell.In another exemplary embodiment, memory management circuitry 202 is with logical program unit to manage reproducible nonvolatile memorizer module 106, and therefore memory management circuitry 202 can set up a physical address mapping table to record the mapping relations between logical program unit and entity program unit.Above-mentioned physical address mapping table can be stored among system region 406 or outside, the present invention is also not subject to the limits.
Logical address 410 (0) ~ 410 (D) may map to the entity storage unit in data field 402 or idle district 404, but can not map to the entity storage unit in system region 406.With another one angle, in this exemplary embodiment, logical address in the write instruction that the host computer system 1000 that can not map to entity program unit in system region 406 transmits, that is the entity program unit in system region 406 can not map to memory storage apparatus 100 be supplied to host computer system 1000 use logical address 410 (0) ~ 410 (D), logical address 410 (0) ~ 410 (D) can be the logical address in the physical address mapping table in memory storage apparatus 100.
When host computer system 1000 will access the data in reproducible nonvolatile memorizer module 106, host computer system 1000 can be assigned reading command or write instruction to memorizer control circuit unit 104.Memorizer control circuit unit 104 can read data according to this reading command or data be write in reproducible nonvolatile memorizer module 106 from reproducible nonvolatile memorizer module 106.In addition, when host computer system 1000 does not assign instruction, memorizer control circuit unit 104 also can access reproducible nonvolatile memorizer module 106, such as, perform the data in refuse collection (garbage collection) or access system district 406.Specifically, in different situations, memorizer control circuit unit 104 can provide the clock signal of different frequency to reproducible nonvolatile memorizer module 106.
For example, when memory management circuitry 202 will read reproducible nonvolatile memorizer module 106, clock generating circuit 258 can provide the first clock signal to reproducible nonvolatile memorizer module 106 and memory management circuitry 202, and memory management circuitry 202 can read the first data in reproducible nonvolatile memorizer module 106 according to the first clock signal.When memory management circuitry 202 will write reproducible nonvolatile memorizer module 106 one second data, clock generating circuit 258 can provide the second clock signal to reproducible nonvolatile memorizer module 106 and memory management circuitry 202, and the second data can write in reproducible nonvolatile memorizer module 106 according to the second clock signal by memory management circuitry 202.Wherein the frequency of the second clock signal is different from the frequency of the first clock signal.Such as, the frequency of the second clock signal is the frequency being less than the first clock signal.Therefore, when reading the first data, reproducible nonvolatile memorizer module 106 operates in higher frequency, can increase reading speed by this.On the other hand, when write the second data, reproducible nonvolatile memorizer module 106 operates in lower frequency, can be reduced in the probability that in the process of write, the second data make a mistake by this.But in another exemplary embodiment, the frequency of the second clock signal may also be the frequency being greater than the first clock signal, the present invention is also not subject to the limits.
In an exemplary embodiment, above-mentioned read or write operation is indicated by host computer system 1000.Specifically, memory management circuitry 202 can receive one first instruction from host computer system 1000.Memory management circuitry 202 can judge the classification of this first instruction.If the first instruction is reading command, then clock generating circuit 258 can provide the first clock signal, and memory management circuitry 202 can read the first data according to the first clock signal.If the first instruction is write instruction, then clock generating circuit 258 can provide the second clock signal, and the second data can be write to reproducible nonvolatile memorizer module 106 according to the second clock signal by memory management circuitry 202.But in another exemplary embodiment, above-mentioned read or write operation is not indicated by host computer system 1000.Such as, when performing refuse collection (being not indicated by host computer system 1000), memory management circuitry 202 also can read or write some data.The present invention does not limit above-mentioned read or write operation whether indicated by host computer system 1000, does not limit source and the content of the first data and the second data yet.
In an exemplary embodiment, when read important data, the second clock signal that meeting frequency of utilization is lower; And read relatively unessential data time, can higher the first clock signal of frequency of utilization.For example, the data being stored in system region 406 are relatively important than the data be stored in data field 402.In an exemplary embodiment, the first above-mentioned data can be stored in data field 402, and when memory management circuitry 202 will read the first data in data field 402, the first clock signal that memory management circuitry 202 meeting frequency of utilization is higher reads data.But, in a system region 406 the 3rd data are stored in (such as when memory management circuitry 202 will read, physical address mapping table) time, clock generating circuit 258 can provide the second clock signal to reproducible nonvolatile memorizer module 106, and memory management circuitry 202 can according to the 3rd data in the second clock signal reading system district 406.By this, the probability made a mistake when reading significant data can be reduced.
In an exemplary embodiment, when there is read error, memory management circuitry 202 can repeat the operation of reading.When the first clock signal that frequency of utilization is higher reads the first data, memory management circuitry 202 also can calculate a read error number of times, and judges whether that the second clock signal will using frequency instead lower reads the first data according to this read error number of times.Specifically, when the first data are written into reproducible nonvolatile memorizer module 106, bug check and correcting circuit 256 can produce corresponding error correcting code or bug check code (error detection code, abbreviation: EDC).These error correcting codes or bug check code can be Hamming code (hamming code), low-density parity check code (low density parity check code, LDPC code), turbine code (turbo code) or Reed Solomon code (Reed-solomon code be called for short:, RS code), BCH code or use the code of other algorithms be called for short:, the present invention is also not subject to the limits.The error correcting code of correspondence or bug check code can write in reproducible nonvolatile memorizer module 106 by memory management circuitry 202.When reading the first data, memory management circuitry 202 also can read corresponding error correcting code or bug check code in the lump.According to this error correcting code or bug check code, bug check and correcting circuit 256 can judge that whether the first data are wrong.Such as, according to error correcting code, bug check and correcting circuit 256 first can judge that whether the first data are wrong.If judge that the first data do not have mistake according to error correcting code, according to bug check code, bug check and correcting circuit 256 also can judge that whether the first data are wrong.If the first data are wrong, memory management circuitry 202 can judge whether read error number of times meets a critical condition (such as, being greater than a critical value).If the first data are wrong and read error number of times does not meet this critical condition (such as, be less than critical value), memory management circuitry 202 can again read the first data according to the first clock signal and upgrade read error number of times (such as, adding 1).That is read error number of times also can represent the number of times repeating reading first data.If the first data are wrong and read error number of times meets critical condition, the second clock signal that clock generating circuit 258 can provide frequency lower is to reproducible nonvolatile memorizer module 106, and memory management circuitry 202 can read the first data according to the second clock signal, reduces the probability of read error by this.
In an exemplary embodiment, be electrically connected at the passage between reproducible nonvolatile memorizer module 106 and memorizer control circuit unit 104 for each, memory management circuitry all can record corresponding read error number of times.Therefore, read error number of times also can represent whether corresponding passage easily read error occurs.Easily occurring on the passage of read error, memorizer control circuit unit 104 can read data by lower the second clock signal of frequency of utilization, may read data by higher the first clock signal of frequency of utilization on other passages simultaneously.
Above-mentioned judgement uses the step of the first clock signal or the second clock signal also can at random combine.Such as, Fig. 5 illustrates according to an exemplary embodiment process flow diagram judging use first clock signal or the second clock signal.Please refer to Fig. 5, in step S501, judge whether read error number of times meets critical condition.If read error number of times meets critical condition, carry out step S505.If read error number of times does not meet critical condition, in step S502, judge that whether the data that will access are in system region 406.Data to access are in system region 406, carry out step S505.To the data of access not in system region 406, in step S503, whether what judge to perform is write operation.If what perform is write operation, carry out step S505.If what perform is not write operation, carry out step S504, the clock signal providing frequency lower is to reproducible nonvolatile memorizer module 106.In step S505, the clock signal providing frequency higher is to reproducible nonvolatile memorizer module 106.But the present invention does not limit how integrating step S501 ~ 503.
[the second exemplary embodiment]
At this, the second exemplary embodiment and the first exemplary embodiment difference are only described.Please refer to Fig. 4, in the second exemplary embodiment, clock generating circuit 258 can provide the first clock signal or the second clock signal to reproducible nonvolatile memorizer module 106.But memory management circuitry 202 can be applied the first clock signal and perform the first operation to data field 402 or idle district 404, and the second clock signal can be applied the second operation is performed to data field 402 or idle district 404.First operation and second operates can be identical or not identical.In addition, it can be performed by the instruction assigned according to host computer system 1000 that the first operation and second operate, also can be memory management circuitry 202 own performed by, the present invention is also not subject to the limits.But the frequency of the first clock signal is different from the frequency of the second clock signal.For example, the frequency of the second clock signal is less than the frequency of this first clock signal.
In an exemplary embodiment, first is operating as read operation, and second is operating as write operation.In another exemplary embodiment, above-mentioned physical address mapping table is stored in the entity erased cell in idle district 404, the user's data in data field 402 or idle district 404 are read in first operation, and the physical address mapping table in idle district 404 is read in the second operation.
In an exemplary embodiment, the first data in data field 402 or idle district 404 are read in the first operation, and the second operation is in order to read the first data again when the first data are wrong.Specifically, after application first clock signal reads the first data, according to error correcting code or bug check code, memory management circuitry 202 can judge that whether the first data are wrong.If judge that the first data are wrong according to error correcting code or bug check code, then memory management circuitry can perform the second operation, again reads the first data to apply the second clock signal.
In sum, the memory control methods that exemplary embodiment of the present invention proposes, memory storage apparatus and memorizer control circuit unit, can provide the clock signal of different frequency to reproducible nonvolatile memorizer module according to different situations.By this, the speed of reproducible nonvolatile memorizer module running can be promoted, or the probability that reduction certain operations makes a mistake.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (31)
1. a memory control methods, for a reproducible nonvolatile memorizer module, is characterized in that, comprising:
There is provided one first clock signal to this reproducible nonvolatile memorizer module, and read one first data in this reproducible nonvolatile memorizer module according to this first clock signal; And
There is provided one second clock signal to this reproducible nonvolatile memorizer module, and according to this second clock signal, one second data are write in this reproducible nonvolatile memorizer module, wherein a frequency of this second clock signal is different from a frequency of this first clock signal.
2. memory control methods according to claim 1, is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal.
3. memory control methods according to claim 1, is characterized in that, also comprises:
Receive one first instruction from a host computer system;
If this first instruction is a reading command, described in execution, provide the step of this first clock signal; And
If this first instruction is a write instruction, described in execution, provide the step of this second clock signal.
4. memory control methods according to claim 1, it is characterized in that, this reproducible nonvolatile memorizer module comprises multiple entity erased cell, those entity erased cell are at least divided into a data field and a system region, these first data are stored in this data field, and this memory control methods also comprises:
There is provided this second clock signal to this reproducible nonvolatile memorizer module, and read 1 in this system region the 3rd data according to this second clock signal.
5. memory control methods according to claim 1, is characterized in that, also comprises:
Judge that whether these first data are wrong according to an error correcting code or a bug check code, and judge whether a read error number of times meets a critical condition;
If these first data are wrong and this read error number of times does not meet this critical condition, again read these first data according to this first clock signal and upgrade this read error number of times;
If these first data are wrong and this read error number of times meets this critical condition, provide this second clock signal to this reproducible nonvolatile memorizer module, and read this first data according to this second clock signal.
6. memory control methods according to claim 5, is characterized in that, judges that the whether vicious step of these first data comprises according to this error correcting code or this bug check code:
Judge that whether these first data are wrong according to this error correcting code; And
If judge that these first data do not have mistake according to this error correcting code, judge that whether these first data are wrong according to this bug check code.
7. memory control methods according to claim 5, is characterized in that, this reproducible nonvolatile memorizer module is electrically connected to multiple passage, and this memory control methods also comprises:
For each those passage, this read error number of times that record is corresponding.
8. a memory storage apparatus, is characterized in that, comprising:
One connecting interface unit, in order to be electrically connected to a host computer system;
One reproducible nonvolatile memorizer module, comprises multiple entity erased cell; And
One memorizer control circuit unit, be electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, in order to provide one first clock signal to this reproducible nonvolatile memorizer module, and one first data read according to this first clock signal in this reproducible nonvolatile memorizer module
Wherein, this memorizer control circuit unit is in order to provide one second clock signal to this reproducible nonvolatile memorizer module, and according to this second clock signal, one second data are write in this reproducible nonvolatile memorizer module, wherein a frequency of this second clock signal is different from a frequency of this first clock signal.
9. memory storage apparatus according to claim 8, is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal.
10. memory storage apparatus according to claim 8, is characterized in that, this memorizer control circuit unit also in order to receive from one first instruction of this host computer system,
Wherein, if this first instruction is a reading command, this memorizer control circuit unit is in order to provide this first clock signal; And
Wherein, if this first instruction is a write instruction, this memorizer control circuit unit is in order to provide this second clock signal.
11. memory storage apparatus according to claim 8, it is characterized in that, those entity erased cell are at least divided into a data field and a system region, these first data are stored in this data field, and this memorizer control circuit unit is also in order to provide this second clock signal to this reproducible nonvolatile memorizer module, and reads 1 in this system region the 3rd data according to this second clock signal.
12. memory storage apparatus according to claim 8, it is characterized in that, this memorizer control circuit unit also in order to judge that whether these first data are wrong according to an error correcting code or a bug check code, and judges whether a read error number of times meets a critical condition
Wherein, if these first data are wrong and this read error number of times does not meet this critical condition, this memorizer control circuit unit in order to again to read these first data according to this first clock signal and to upgrade this read error number of times,
Wherein, if these first data are wrong and this read error number of times meets this critical condition, this memorizer control circuit unit in order to provide this second clock signal to this reproducible nonvolatile memorizer module, and reads this first data according to this second clock signal.
13. memory storage apparatus according to claim 12, is characterized in that, according to this error correcting code or this bug check code, this memorizer control circuit unit judges that the whether vicious operation of these first data comprises:
According to this error correcting code, this memorizer control circuit unit judges that whether these first data are wrong,
If judge that these first data do not have mistake according to this error correcting code, according to this bug check code, this memorizer control circuit unit judges that whether these first data are wrong.
14. memory storage apparatus according to claim 12, it is characterized in that this reproducible nonvolatile memorizer module is electrically connected to this memorizer control circuit unit by multiple passage, and this memorizer control circuit unit also in order to for each those passage, records this corresponding read error number of times.
15. 1 kinds of memorizer control circuit unit, for controlling a reproducible nonvolatile memorizer module, is characterized in that, this reproducible nonvolatile memorizer module comprises multiple entity erased cell, and this memorizer control circuit unit comprises:
One host interface, in order to be electrically connected to a host computer system;
One memory interface, in order to be electrically connected to this reproducible nonvolatile memorizer module;
One memory management circuitry, is electrically connected to this host interface and this memory interface; And
One clock generating circuit, in order to provide one first clock signal or one second clock signal to this reproducible nonvolatile memorizer module,
Wherein, this memory management circuitry in order to read one first data in this reproducible nonvolatile memorizer module according to this first clock signal,
Wherein, this memory management circuitry is in order to write in this reproducible nonvolatile memorizer module according to this second clock signal by one second data, and wherein a frequency of this second clock signal is different from a frequency of this first clock signal.
16. memorizer control circuit unit according to claim 15, is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal.
17. memorizer control circuit unit according to claim 15, is characterized in that, this memory management circuitry also in order to receive from one first instruction of this host computer system,
Wherein, if this first instruction is a reading command, this clock generating circuit is in order to provide this first clock signal; And
Wherein, if this first instruction is a write instruction, this clock generating circuit is in order to provide this second clock signal.
18. memorizer control circuit unit according to claim 15, it is characterized in that, those entity erased cell are at least divided into a data field and a system region, these first data are stored in this data field, and this memory management circuitry is also in order to read 1 in this system region the 3rd data according to this second clock signal.
19. memorizer control circuit unit according to claim 15, it is characterized in that, this memory management circuitry also in order to judge that whether these first data are wrong according to an error correcting code or a bug check code, and judges whether a read error number of times meets a critical condition
Wherein, if these first data are wrong and this read error number of times does not meet this critical condition, this memory management circuitry in order to again to read these first data according to this first clock signal and to upgrade this read error number of times,
Wherein, if these first data are wrong and this read error number of times meets this critical condition, this memory management circuitry is in order to read this first data according to this second clock signal.
20. memorizer control circuit unit according to claim 19, is characterized in that, according to this error correcting code or this bug check code, this memory management circuitry judges that the whether vicious operation of these first data comprises:
According to this error correcting code, this memory management circuitry judges that whether these first data are wrong,
If judge that these first data do not have mistake according to this error correcting code, according to this bug check code, this memory management circuitry judges that whether these first data are wrong.
21. memorizer control circuit unit according to claim 19, it is characterized in that, this reproducible nonvolatile memorizer module is electrically connected to this memorizer control circuit unit by multiple passage, and this memory management circuitry also in order to for each those passage, records this corresponding read error number of times.
22. 1 kinds of memory control methods, for a reproducible nonvolatile memorizer module, it is characterized in that, this reproducible nonvolatile memorizer module comprises multiple entity program unit, and those entity program unit are divided into a system region, a data field and an idle district, this memory control methods comprises:
There is provided one first clock signal to this reproducible nonvolatile memorizer module, and apply this first clock signal to this data field of this reproducible nonvolatile memorizer module maybe this idle district execution one first operation; And
There is provided one second clock signal to this reproducible nonvolatile memorizer module, and apply this second clock signal to this data field of this reproducible nonvolatile memorizer module maybe this idle district execution one second operation,
Wherein the frequency of this first clock signal is different from the frequency of this second clock signal.
23. memory control methods according to claim 22, is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal, and this first is operating as a read operation, and this second is operating as a write operation.
24. memory control methods according to claim 22, it is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal, and user's data are read in this first operation, and a physical address mapping table is read in this second operation.
25. memory control methods according to claim 22, it is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal, one first data are read in this first operation, and this second operation is in order to read this first data again when these first data are wrong.
26. memory control methods according to claim 22, it is characterized in that, the system data non-memory of this reproducible nonvolatile memorizer module is maybe this idle district in this data field, and those entity program unit in this system region are without the logical address in the physical address mapping table mapped in this reproducible nonvolatile memorizer module.
27. 1 kinds of memory storage apparatus, is characterized in that, comprising:
One connecting interface unit, in order to be electrically connected to a host computer system;
One reproducible nonvolatile memorizer module, comprises multiple entity program unit; And
One memorizer control circuit unit, is electrically connected to this connecting interface unit and this reproducible nonvolatile memorizer module, those entity program unit is divided into a data field, idle district and a system region,
Wherein, this memorizer control circuit unit is in order to provide one first clock signal to this reproducible nonvolatile memorizer module, and apply this first clock signal to maybe this idle district execution one first operation of this data field of this reproducible nonvolatile memorizer module
Wherein, this memorizer control circuit unit is in order to provide one second clock signal to this reproducible nonvolatile memorizer module, and apply this second clock signal to maybe this idle district execution one second operation of this data field of this reproducible nonvolatile memorizer module
Wherein the frequency of this first clock signal is different from the frequency of this second clock signal.
28. memory storage apparatus according to claim 27, is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal, and this first is operating as a read operation, and this second is operating as a write operation.
29. memory storage apparatus according to claim 27, it is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal, and user's data are read in this first operation, and a physical address mapping table is read in this second operation.
30. memory storage apparatus according to claim 27, it is characterized in that, this frequency of this second clock signal is less than this frequency of this first clock signal, one first data are read in this first operation, and this second operation is in order to read this first data again when these first data are wrong.
31. memory storage apparatus according to claim 27, it is characterized in that, the system data non-memory of this reproducible nonvolatile memorizer module is maybe this idle district in this data field, and those entity program unit in this system region are without the logical address mapped in a physical address mapping table of this memory storage apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310558040.3A CN104636267B (en) | 2013-11-11 | 2013-11-11 | Memory control methods, memory storage apparatus and memorizer control circuit unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310558040.3A CN104636267B (en) | 2013-11-11 | 2013-11-11 | Memory control methods, memory storage apparatus and memorizer control circuit unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104636267A true CN104636267A (en) | 2015-05-20 |
| CN104636267B CN104636267B (en) | 2018-01-12 |
Family
ID=53215047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310558040.3A Active CN104636267B (en) | 2013-11-11 | 2013-11-11 | Memory control methods, memory storage apparatus and memorizer control circuit unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104636267B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107590080A (en) * | 2016-07-07 | 2018-01-16 | 合肥兆芯电子有限公司 | Map table updating method, memorizer control circuit unit and memory storage apparatus |
| CN107807903A (en) * | 2017-11-07 | 2018-03-16 | 晶晨半导体(上海)股份有限公司 | A kind of DDR system frequencies dynamic regulating method and device |
| CN108363453A (en) * | 2017-01-26 | 2018-08-03 | 群联电子股份有限公司 | With reference to time pulse signal forming method, memory storage apparatus and connecting interface unit |
| WO2019136981A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Data reliability enhancement system and method |
| CN111610937A (en) * | 2020-05-26 | 2020-09-01 | 群联电子股份有限公司 | Data writing method, memory storage device and memory control circuit unit |
| CN113096713A (en) * | 2021-04-12 | 2021-07-09 | 合肥兆芯电子有限公司 | Memory management method, memory control circuit unit and memory storage device |
| CN113450843A (en) * | 2020-03-27 | 2021-09-28 | 群联电子股份有限公司 | Circuit layout structure and memory storage device |
| CN112309445B (en) * | 2019-08-01 | 2023-10-13 | 群联电子股份有限公司 | Memory interface circuit, memory storage device and signal generation method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1395153A (en) * | 2001-07-11 | 2003-02-05 | 仁宝电脑工业股份有限公司 | Portable computer peripheral equipment |
| CN1627427A (en) * | 2003-08-18 | 2005-06-15 | 索尼株式会社 | Data recording/reproducing device, data recording/reproducing method, program, and recording medium |
| CN1801343A (en) * | 2005-01-06 | 2006-07-12 | 建兴电子科技股份有限公司 | Optical disk reading method |
| CN101814007A (en) * | 2009-02-19 | 2010-08-25 | 威盛电子股份有限公司 | Hard disk access method and system supporting highest hard disk transmission rate |
| CN101930404A (en) * | 2010-08-27 | 2010-12-29 | 威盛电子股份有限公司 | Memory device and operation method thereof |
| WO2013016723A2 (en) * | 2011-07-28 | 2013-01-31 | Netlist, Inc. | Flash-dram hybrid memory module |
-
2013
- 2013-11-11 CN CN201310558040.3A patent/CN104636267B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1395153A (en) * | 2001-07-11 | 2003-02-05 | 仁宝电脑工业股份有限公司 | Portable computer peripheral equipment |
| CN1627427A (en) * | 2003-08-18 | 2005-06-15 | 索尼株式会社 | Data recording/reproducing device, data recording/reproducing method, program, and recording medium |
| CN1801343A (en) * | 2005-01-06 | 2006-07-12 | 建兴电子科技股份有限公司 | Optical disk reading method |
| CN101814007A (en) * | 2009-02-19 | 2010-08-25 | 威盛电子股份有限公司 | Hard disk access method and system supporting highest hard disk transmission rate |
| CN101930404A (en) * | 2010-08-27 | 2010-12-29 | 威盛电子股份有限公司 | Memory device and operation method thereof |
| WO2013016723A2 (en) * | 2011-07-28 | 2013-01-31 | Netlist, Inc. | Flash-dram hybrid memory module |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107590080A (en) * | 2016-07-07 | 2018-01-16 | 合肥兆芯电子有限公司 | Map table updating method, memorizer control circuit unit and memory storage apparatus |
| CN107590080B (en) * | 2016-07-07 | 2020-10-09 | 合肥兆芯电子有限公司 | Mapping table updating method, memory control circuit unit and memory storage device |
| CN108363453A (en) * | 2017-01-26 | 2018-08-03 | 群联电子股份有限公司 | With reference to time pulse signal forming method, memory storage apparatus and connecting interface unit |
| CN107807903A (en) * | 2017-11-07 | 2018-03-16 | 晶晨半导体(上海)股份有限公司 | A kind of DDR system frequencies dynamic regulating method and device |
| WO2019136981A1 (en) * | 2018-01-12 | 2019-07-18 | 江苏华存电子科技有限公司 | Data reliability enhancement system and method |
| CN112309445B (en) * | 2019-08-01 | 2023-10-13 | 群联电子股份有限公司 | Memory interface circuit, memory storage device and signal generation method |
| CN113450843A (en) * | 2020-03-27 | 2021-09-28 | 群联电子股份有限公司 | Circuit layout structure and memory storage device |
| CN113450843B (en) * | 2020-03-27 | 2024-01-23 | 群联电子股份有限公司 | Circuit layout structure and memory storage device |
| CN111610937A (en) * | 2020-05-26 | 2020-09-01 | 群联电子股份有限公司 | Data writing method, memory storage device and memory control circuit unit |
| CN113096713A (en) * | 2021-04-12 | 2021-07-09 | 合肥兆芯电子有限公司 | Memory management method, memory control circuit unit and memory storage device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104636267B (en) | 2018-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI527037B (en) | Data storing method, memory control circuit unit and memory storage apparatus | |
| TWI516927B (en) | Data writing method, memory controller and memory storage apparatus | |
| CN104636267A (en) | Storage control method, storage storing device and storage control circuit unit | |
| TWI470431B (en) | Data writing method, memory controller and memory storage apparatus | |
| TWI476590B (en) | Memory management method, and memory controller and memory storage device using the same | |
| CN104423888A (en) | Data writing method, memory control circuit unit and memory storage device | |
| TWI479314B (en) | Method of storing system data, and memory controller and memory storage apparatus using the same | |
| TWI479505B (en) | Data management method, memory controller and memory storage apparatus | |
| CN104765568A (en) | Data storing method, storage control circuit unit and a storage storing device | |
| CN104765569A (en) | Data write-in method, memory control circuit unit and memory storing device | |
| TWI486765B (en) | Memory management method, memory controller and memory storage device using the same | |
| US8966344B2 (en) | Data protecting method, memory controller and memory storage device | |
| TWI509615B (en) | Data storing method, and memory controller and memory storage apparatus using the same | |
| CN103678162B (en) | System data storage method, memory controller and memory storage device | |
| TW201606503A (en) | Data management method, memory control circuit unit and memory storage apparatus | |
| TWI517165B (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| TWI548991B (en) | Memory management method, memory control circuit unit and memory storage apparatus | |
| TWI501244B (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| CN104252317A (en) | Data writing method, memory controller and memory storage device | |
| US9367390B2 (en) | Memory controlling method, memory storage device and memory controlling circuit unit | |
| CN105224238A (en) | Storage management method, memory storage apparatus and memorizer control circuit unit | |
| CN109273033B (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN104252600B (en) | Data guard method, Memory Controller and memorizer memory devices | |
| TWI553477B (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN104731710A (en) | Memory management method, memory control circuit unit and memory storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |