CN103488579A

CN103488579A - Memory management method, memory controller and memory storage device

Info

Publication number: CN103488579A
Application number: CN201210191603.5A
Authority: CN
Inventors: 黄金汉; 林盈志
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2012-06-11
Filing date: 2012-06-11
Publication date: 2014-01-01
Anticipated expiration: 2032-06-11
Also published as: CN103488579B

Abstract

A memory management method is used by a rewritable nonvolatile memory module with a plurality of physical unit sets, and each physical unit assembly at least comprises a first physical unit. The method includes the following steps: the physical unit sets are grouped into a first area and a second area, the physical unit sets of the first area are set to belong to a first programming mode which represents that all the physical units can be programmed, and the physical unit sets of the second area are set to belong to a second programming mode which represents that only the first physical units can be programmed. The method also includes the following step: when one physical unit set in the first area or the second area is damaged, one physical unit set is converted from the first programming mode into the second programming mode, and cannot be set into the first programming mode again. Consequently, the service life of the rewritable nonvolatile memory can be prolonged.

Description

Storage management method, Memory Controller and memorizer memory devices

Technical field

The invention relates to a kind of storage management method, and particularly relevant for a kind of storage management method for the duplicative non-volatile memory module, Memory Controller and memorizer memory devices.

Background technology

Digital camera, mobile phone and MP3 player are very rapid in growth over the years, make the consumer also increase rapidly the demand of Storage Media.For example, because duplicative non-volatile memory module (, flash memory) has that data are non-volatile, power saving, volume be little, and the characteristic such as machinery-free structure, so be built in above-mentioned given an example various portable multimedia devices in being applicable to very much.

According to the storable figure place of each storage unit, can divide into single-order storage element (Single Level Cell with non-(NAND) type flash memory, SLC) NAND type flash memory, multistage storage element (Multi Level Cell, MLC) NAND type flash memory and multistage storage element (Trinary Level Cell, TLC) NAND type flash memory, the data that wherein each storage unit of SLC NAND type flash memory can store 1 position (, " 1 " and " 0 "), each storage unit that each storage unit of MLC NAND type flash memory can store the data of 2 positions and TLC NAND type flash memory can store the data of 3 positions.

With TLC NAND type flash memory, each physical blocks can comprise a plurality of physical page groups, and each physical page group can comprise lower physical page, middle physical page and upper physical page.In general, the physical blocks in flash memory can be divided into a plurality of uses zone, replaces in district and also can comprise a plurality of physical blocks.When using regional physical blocks to damage, the physical blocks that replaces district can be used to replace the physical blocks of damaging.Yet, when wherein replacing in district while there is no physical blocks, represent that finish the serviceable life of flash memory.Therefore, how effectively the managing physical block, make the life-span of flash memory to extend, the subject under discussion of being concerned about for those skilled in the art.

Summary of the invention

The present invention's one exemplary embodiment proposes a kind of storage management method, Memory Controller and memorizer memory devices, can extend the serviceable life of duplicative non-volatile memory module.

The present invention's one exemplary embodiment proposes a kind of storage management method, for controlling a duplicative non-volatile memory module.This duplicative non-volatile memory module comprises a plurality of physical location set, each physical location set comprises a plurality of physical location groups, each physical location group comprises a plurality of physical locations, and the physical location of each physical location group at least comprises first physical location.This storage management method comprises: the physical location set at least is divided into to the firstth district and Second Region, and the physical location set of setting the firstth district belongs to the first programming mode, and the physical location set of setting Second Region belongs to the second programming mode.Wherein the first programming mode means that all physical locations can be programmed, and the second programming mode means that only the first physical location can be programmed.This method also comprises: when the first physical location set of Second Region meets the second damage condition, replace the first physical location set with the second physical location set in the firstth district, set that the second physical location set belongs to the second programming mode and the second physical location set can't be set to the first programming mode again.

In an example is implemented, the second above-mentioned damage condition comprises: the number of times of erasing of the first physical location set reaches the upper limit that position number that the second critical value, the first physical location set generation misprogrammed or the first physical location set make a mistake can be corrected over bug check and correcting code.

In an example is implemented, when above-mentioned the first physical location set when Second Region meets the second damage condition, the step of replacing the first physical location set with the second physical location set in the firstth district comprises: from the physical location set in the firstth district, obtain the second physical location set of the first damage condition that meets and replace the first physical location set.The first damage condition comprises: the number of times of erasing of the second physical location set reaches the first critical value, the second physical location set and position number that one misprogrammed or the second physical location set make a mistake occurs surpasses the upper limit that bug check and correcting code can be corrected.

In an example is implemented, when above-mentioned the first physical location set when Second Region meets the second damage condition, the step of replacing the first physical location set with the second physical location set in the firstth district comprises: from the physical location set in the firstth district, obtain the number of times of erasing and replace the first physical location set between the second physical location set of 0 to first critical value.

In an example is implemented, above-mentioned storage management method also comprises: when the 3rd physical location set in the firstth district meets the first damage condition, the 3rd physical location set is divided into to Second Region; And set that the 3rd physical location set belongs to the second programming mode and the 3rd physical location set can't be set to the first programming mode again.The first damage condition comprises: the number of times of erasing of the 3rd physical location set reaches position number that the first critical value, the 3rd physical location set generation misprogrammed or the 3rd physical location set make a mistake and surpasses the upper limit that bug check and correcting code can be corrected.

In an example is implemented, above-mentioned storage management method also comprises: when the 3rd physical location set in the firstth district meets the first damage condition, obtain a plurality of the 4th physical location set that meet the first damage condition in the firstth district; Set these the 4th physical location set and belong to the second programming mode; And replace the 3rd physical location set with the 4th physical location set.The first damage condition comprises: the number of times of erasing of the 4th physical location set reaches the first critical value, the 4th physical location set and position number that one misprogrammed or the 4th physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

In an example is implemented, when above-mentioned the 3rd physical location set when the firstth district meets the first damage condition, the step that obtains in the firstth district the 4th physical location set that belongs to the first damage condition comprises; Judge in the firstth district whether have the physical location set can be under the first programming mode storage data, if not, obtain the 4th physical location set and replace the 3rd physical location set.

With the another one angle, the present invention's one exemplary embodiment proposes a kind of memorizer memory devices, comprises connector, duplicative non-volatile memory module and Memory Controller.Wherein connector is to be electrically connected to host computer system.The duplicative non-volatile memory module comprises a plurality of physical location set, and each physical location set comprises a plurality of physical location groups.And each physical location group comprises a plurality of physical locations, the physical location of each physical location group at least comprises the first physical location.Memory Controller is to be electrically connected to connector and duplicative non-volatile memory module.Memory Controller can at least be divided into the firstth district and Second Region by the physical location set.And the physical location set that Memory Controller can be set the firstth district belongs to the first programming mode, and the physical location set of setting Second Region belongs to the second programming mode.Wherein the first programming mode means that all physical locations can be programmed, and the second programming mode means that only the first physical location can be programmed.When the first physical location set of Second Region meets the second damage condition, Memory Controller is replaced the first physical location set in order to the second physical location set with the firstth district, and sets that the second physical location set belongs to the second programming mode and the second physical location set can't be divided into the first programming mode again.

In an example is implemented, above-mentioned Memory Controller, also in order to the physical location set from the firstth district, is obtained the second physical location set of the first damage condition that meets and is replaced the first physical location set.The first damage condition comprises: the number of times of erasing of the second physical location set reaches position number that the first critical value, the second physical location set generation misprogrammed or the second physical location set make a mistake and surpasses the upper limit that bug check and correcting code can be corrected.

In an example is implemented, above-mentioned Memory Controller, also in order to the physical location set from the firstth district, is obtained the number of times of erasing and is replaced the first physical location set between the second physical location set of 0 to first critical value.

In an example is implemented, when the 3rd physical location set in the firstth district meets the first damage condition, Memory Controller is also in order to the 3rd physical location set is divided into to Second Region, and sets the 3rd physical location set and belong to the second programming mode and can't be set to the first programming mode again.The first damage condition comprises: the number of times of erasing of the 3rd physical location set reaches the first critical value, the 3rd physical location set and position number that one misprogrammed or the 3rd physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

In an example is implemented, when above-mentioned Memory Controller also damages in order to the 3rd physical location set in the firstth district, obtain a plurality of the 4th physical location set that meet the first damage condition in the firstth district, set the 4th physical location set and belong to the second programming mode, and replace the 3rd physical location set with the 4th physical location set.The first damage condition comprises: the number of times of erasing of the 4th physical location set reaches position number that the first critical value, the 4th physical location set generation misprogrammed or the 4th physical location set make a mistake and surpasses the upper limit that bug check and correcting code can be corrected.

In an example is implemented, above-mentioned Memory Controller also in order to judge in the firstth district whether have the physical location set can be under the first programming mode storage data, if not, obtain the 4th physical location set and replace the 3rd physical location set.

With the another one angle, the present invention's one exemplary embodiment proposes a kind of Memory Controller, comprises host interface, memory interface and memory management circuitry.Host interface is to be electrically connected to host computer system.Memory interface is to be electrically connected to above-mentioned duplicative non-volatile memory module.Memory management circuitry is to be electrically connected to host interface and memory interface.Memory management circuitry can at least be divided into the firstth district and Second Region by the physical location set.And memory management circuitry belongs to the first programming mode in order to the physical location set of setting the firstth district, the physical location set of setting Second Region belongs to the second programming mode.Wherein, the first programming mode means that all physical locations can be programmed, and the second programming mode means that only the first physical location can be programmed.When the first physical location set of Second Region meets the second damage condition, memory management circuitry can be replaced the first physical location set with the second physical location set in the firstth district, and to set the second physical location set be that the second programming mode and the second physical location set can't be divided into the first programming mode again.

In an example is implemented, above-mentioned memory management circuitry, also in order to the physical location set from the firstth district, obtains the second physical location set of the first damage condition that meets and replaces the first physical location set.The first damage condition comprises: the number of times of erasing of the second physical location set reaches the first critical value, the second physical location set and position number that one misprogrammed or the second physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

In an example is implemented, above-mentioned memory management circuitry, also in order to the physical location set from the firstth district, obtains the number of times of erasing and replaces the first physical location set between the second physical location set of 0 to first critical value.

In an example is implemented, when the 3rd physical location set in the firstth district meets the first damage condition, memory management circuitry is also in order to be divided into Second Region by the 3rd physical location set, sets that the 3rd physical location set belongs to the second programming mode and the 3rd physical location set can not be set to the first programming mode again.The first damage condition comprises: the number of times of erasing of the 3rd physical location set reaches position number that the first critical value, the 3rd physical location set generation misprogrammed or the 3rd physical location set make a mistake and surpasses the upper limit that bug check and correcting code can be corrected.

In an example is implemented, when above-mentioned memory management circuitry is also damaged in order to the 3rd physical location set in the firstth district, obtain a plurality of the 4th physical location set that meet the first damage condition in the firstth district, set these the 4th physical location set and belong to the second programming mode, and replace the 3rd physical location set with the 4th physical location set.The first damage condition comprises: the number of times of erasing of the 4th physical location set reaches position number that the first critical value, the 4th physical location set generation misprogrammed or the 4th physical location set make a mistake and surpasses the upper limit that bug check and correcting code can be corrected.

In an example is implemented, above-mentioned memory management circuitry also in order to judge in the firstth district whether have the physical location set can be under the first programming mode storage data, if not, obtain the 4th physical location set and replace the 3rd physical location set.

With the another one angle, the present invention's one exemplary embodiment proposes a kind of storage management method, for controlling above-mentioned duplicative non-volatile memory module.This storage management method comprises: the physical location set at least is divided into to the firstth district and Second Region, the physical location set of setting the firstth district belongs to the first programming mode, the physical location set of setting Second Region belongs to the second programming mode, wherein the first programming mode means that physical location can be programmed, and the second programming mode means that only the first physical location can be programmed.The method also comprises: when at least one first physical location set in the firstth district meets the first damage condition, the first physical location set is divided to Second Region, set the first physical location set and belong to the second programming mode, and the first physical location set can't be set to the first programming mode again.

In an example is implemented, the first above-mentioned damage condition comprises: the number of times of erasing of the first physical location set reaches the upper limit that position number that the first critical value, the first physical location set generation misprogrammed or the first physical location set make a mistake can be corrected over a bug check and correcting code.

In an example is implemented, above-mentioned storage management method also comprises: the first zoning is divided into to a data field and Ge 3rd district, configures the physical location set of a plurality of logical block compound mappings to data field; When at least the first physical location set meets the first damage condition, judge the 3rd district whether have the physical location set can be under the first programming mode storage data, if not, obtain a plurality of the second physical location set from Second Region; And the second physical location set is divided into to the 3rd district.

Based on above-mentioned, exemplary embodiment of the present invention proposes a kind of storage management method, Memory Controller and memorizer memory devices, can increase the serviceable life of duplicative nonvolatile memory.

For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.

The accompanying drawing explanation

Figure 1A is host computer system and the memorizer memory devices illustrated according to an exemplary embodiment.

Figure 1B is the schematic diagram of the computing machine, input/output device and the memorizer memory devices that illustrate according to an exemplary embodiment.

Fig. 1 C is the host computer system that illustrates according to an exemplary embodiment and the schematic diagram of memorizer memory devices.

Fig. 2 is the summary calcspar that illustrates the memorizer memory devices shown in Figure 1A.

Fig. 3 A and Fig. 3 B are the example schematic that the storage unit that illustrates according to an exemplary embodiment stores framework and physical blocks.

Fig. 3 C is the example schematic according to the write sequence of an exemplary embodiment explanation physical page.

Fig. 4 is the summary calcspar of the Memory Controller that illustrates according to an exemplary embodiment.

Fig. 5 is the example schematic of the management duplicative non-volatile memory module that illustrates according to an exemplary embodiment.

Fig. 6 writes to data the example schematic of the physical blocks of Second Region according to another exemplary embodiment explanation.

Fig. 7 replaces the example schematic of the physical blocks in the firstth district according to the physical blocks in exemplary embodiment explanation Yong 3rd district.

Fig. 8 is the process flow diagram according to an exemplary embodiment explanation storage management method.

Fig. 9 take physical page according to an exemplary embodiment explanation physical blocks to be divided into during as unit to the example schematic of the firstth district and Second Region.

Figure 10 be take physical page during as unit according to an exemplary embodiment explanation, the example schematic that data are write.

Figure 11 copies to three example schematic that are set as the physical blocks of the second programming mode according to an exemplary embodiment explanation by the valid data of a physical blocks.

Figure 12 is the process flow diagram of the storage management method that illustrates according to an exemplary embodiment.

[main element label declaration]

Embodiment

[the first exemplary embodiment]

In this manual, the physical location of indication also is called as physical page, and the physical location set also is called as physical blocks, and the physical location group also is called as the physical page group.Wherein, the least unit that the physical location set is erased.And, by a plurality of physical location set of a clusters of logic cells mapping, can be called as a physical location group.In addition, upper physical location also is called as physical page, and middle physical location also is called as middle physical page, and lower physical location also is called as lower physical page.Yet, in other exemplary embodiment, physical location can have one or more electronic component that can make carbon copies with non-volatile characteristic for other, for example entity is fanned, and the present invention is also not subject to the limits.In addition, logical blocks also is called as the logical block set, and the logical page (LPAGE) group also is called as the logical block group, and logical page (LPAGE) also is called as logical block.And a plurality of logical block set also can be described as a clusters of logic cells.

Generally speaking, memorizer memory devices (also claiming memory storage system) comprises duplicative non-volatile memory module and controller (also claiming control circuit).Usually memorizer memory devices is to use together with host computer system, so that host computer system can write to data memorizer memory devices or reading out data from memorizer memory devices.

Please refer to Figure 1A, host computer system 1000 generally comprises computing machine 1100 and installs 1106 with I/O (input/output, I/O).Computing machine 1100 comprises microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other device.

In embodiments of the present invention, memorizer memory devices 100 is to be electrically connected by data transmission interface 1110 and other element of host computer system 1000.Data can be write to memorizer memory devices 100 or reading out data from memorizer memory devices 100 by microprocessor 1102, random access memory 1104 with the running of input/output device 1106.For example, memorizer memory devices 100 can be the duplicative non-volatile memory storage device of portable disk 1212, storage card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 as shown in Figure 1B etc.

Generally speaking, host computer system 1000 is to coordinate substantially any system with storage data with memorizer memory devices 100.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example, in host computer system, be digital camera (video camera) 1310 o'clock, duplicative non-volatile memory storage device is its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is directly to be electrically connected on the substrate of host computer system.

Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104 and duplicative non-volatile memory module 106.

In this exemplary embodiment, connector 102 is to be compatible with secure digital (Secure Digital, SD) interface standard.Yet, it must be appreciated, the invention is not restricted to this, connector 102 can also be to meet advanced annex arranged side by side (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal serial bus (Universal Serial Bus, USB) standard, advanced annex (the Serial Advanced Technology Attachment of sequence, SATA) standard, memory stick (Memory Stick, MS) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, compact flash (Compact Flash, CF) interface standard, integrated form drives electrical interface (Integrated Device Electronics, IDE) standard or other applicable standard.

Memory Controller 104 is a plurality of logic gates or the steering order with hardware pattern or firmware pattern implementation in order to execution, and carries out the runnings such as writing, read and erase of data in duplicative non-volatile memory module 106 according to the instruction of host computer system 1000.

Duplicative non-volatile memory module 106 is to be electrically connected to Memory Controller 104, and the data that write in order to store host computer system 1000.Duplicative non-volatile memory module 106 has physical blocks 304 (0)～304 (R).For example, physical blocks 304 (0)～304 (R) can belong to same memory crystal grain (die) or belong to different memory crystal grain.In this exemplary embodiment, each physical blocks has respectively a plurality of physical page groups and each physical page group comprises at least one physical page consisted of the storage unit that is positioned at same word line, and the physical page that wherein belongs to same physical blocks must side by side be erased.In more detail, physical blocks is the least unit of erasing.That is, the storage unit of being erased in the lump that each physical blocks contains minimal amount.

Fig. 3 A and Fig. 3 B are the example schematic that the storage unit that illustrates according to the first exemplary embodiment stores framework and physical blocks.

Please refer to Fig. 3 A, the storing state of each storage unit of duplicative non-volatile memory module 106 can be identified as " 111 ", " 110 ", " 101 ", " 100 ", " 011 ", " 010 ", " 001 " or " 000 " (as shown in Figure 3A), and wherein the 1st position counting, left side is LSB (Least significant bit), the 2nd position counting from left side be that CSB (center significant bit) and the 3rd position counting from left side are MSB (most significant bit).In addition, the several storage unit that are arranged on same word line can form 3 physical pages, the physical page that wherein LSB of a little storage unit forms thus is called lower physical page, the physical page that the CSB of a little storage unit forms thus is called middle physical page, and the physical page that the MSB of a little storage unit forms thus is called physical page.

Please refer to Fig. 3 B, a physical blocks is comprised of a plurality of physical page groups, wherein each physical page group comprise the lower physical page that formed by the several storage unit on being arranged in same word line, in physical page and upper physical page.For example, putting in order of numeral physical page in Fig. 3 B, in physical blocks, belong to the 0th physical page of lower physical page, the 2nd physical page that belongs to the 1st physical page of middle physical page and belong to physical page can be regarded as a physical page group.Similarly, the 3rd, 4,5 physical pages can be regarded as a physical page group, and other physical page is also to be divided into a plurality of physical page groups according to this mode by that analogy.Physical page is the minimum unit of programming.That is the minimum unit that, physical page is data writing.Specifically, while being programmed to being arranged in several storage unit on same word line, only can under programming, after physical page or under programming, after physical page, middle physical page and upper physical page, just can be read, otherwise stored data may be lost.For example, after the 0th physical page and the 1st physical page are programmed, the 2nd physical page of must first programming just can read 0th～2 physical pages later.

Please refer to Fig. 3 C, physical blocks also can be by the jagged order physical page of programming.The numbering of each word line of each digitized representation in word line field 322.And each numeral in lower physical page field 324, middle physical page field 326 and upper physical page field 328 is the write sequence of physical page.For example, when will be data programing during to physical blocks, Memory Controller 104 can first be programmed to the lower physical page of the 0th word line.Then, the lower physical page of the 1st word line of Memory Controller 104 meeting programmings and the middle physical page of the 0th the word line of programming.Then, lower physical page, the middle physical page of the 1st word line and the upper physical page of the 0th word line of the 2nd word line of Memory Controller 104 meeting programmings, by that analogy.By this, the physical page of different word lines can side by side be programmed.Yet, in other exemplary embodiment, Memory Controller 104 physical blocks of also can programming in differing order, the present invention is also not subject to the limits.

In addition, when a physical blocks meets one of them of a plurality of damage conditions, this physical blocks just can be called as the physical blocks of damage.For example, the number of times of erasing of physical blocks has a upper limit, if the number of times of erasing of physical blocks arrives this upper limit, can meet the damage condition.When if this hypothesis is selected physical page under programming, middle physical page with upper physical page, the number of times of erasing of physical blocks on be limited to the first critical value.If only select the lower physical page of programming, the number of times of erasing of physical blocks on be limited to the second critical value.Specifically, the first critical value can be less than the second critical value.For example, the first critical value is 3000, and the second critical value is 20000.The writing speed of lower physical page can be faster than the writing speed of middle physical page and upper physical page.That is to say, when data are programmed to a physical blocks, data are write to the required time of lower physical page can be shorter than data being write to the required time of middle physical page or upper physical page.In addition, if misprogrammed has occurred when data are write to physical blocks, the physical blocks that misprogrammed occurs also can meet the damage condition.Perhaps, if the position number made a mistake during from the physical blocks reading out data surpasses the upper limit that bug check and correcting code (error detection and correction code) can be corrected, this physical blocks also meets the damage condition.In sum, when a physical blocks meets one of them of above-mentioned damage condition, this physical blocks just can be called as the physical blocks of damage.Yet the present invention is the condition of damage-limiting not.

On the other hand, must be according to the data writing that puts in order of physical page during data writing in physical blocks 304 (0)～304 (R).In addition, the physical page that has been written into data could be again for data writing after must first being erased.Therefore, in general, physical blocks is the least unit of management duplicative non-volatile memory module 106.For example, if, when in physical blocks, only the data of partial page are updated, the valid data in this physical blocks must be moved to another empty physical blocks, this physical blocks just can be performed erase operation for use.At this, the operation of moving valid data is called data and merges running.Yet, in another exemplary embodiment, also can be used as the least unit of management duplicative non-volatile memory module 106 with physical page, the present invention is also not subject to the limits.

Each physical page generally includes data bit district and redundant digit district.The data bit district is in order to store user's data, and the redundant digit district for example, in order to the data (, bug check and correcting code) of stocking system.In this exemplary embodiment, each physical blocks is comprised of 258 physical pages, and the capacity of each physical page is 8 kilobyte (Kilobyte, KB).Yet, it must be appreciated, the invention is not restricted to this.

In this exemplary embodiment, duplicative non-volatile memory module 106 is a multistage storage element (Trinary Level Cell, TLC) NAND type flash memory module, that is each physical page group has comprised time physical page, middle physical page and upper physical page.Yet, it must be appreciated, duplicative non-volatile memory module 106 is not limited to TLC NAND type flash memory module.In another exemplary embodiment of the present invention, duplicative non-volatile memory module 106 is also more than quadravalence, or other has the memory module of identical characteristics.

Please refer to Fig. 4, Memory Controller 104 comprises memory management circuitry 202, host interface 204 and memory interface 206.

Memory management circuitry 202 is in order to the overall operation of control store controller 104.Specifically, memory management circuitry 202 has a plurality of steering orders, and, when memorizer memory devices 100 running, these a little steering orders can be performed to carry out the runnings such as writing, read and erase of data.

In this exemplary embodiment, the steering order of memory management circuitry 202 is to carry out implementation with the firmware pattern.For example, memory management circuitry 202 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and these a little steering orders are to be burned onto in this ROM (read-only memory).When memorizer memory devices 100 running, these a little steering orders can be carried out to carry out by microprocessor unit the runnings such as writing, read and erase of data.

In another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also the procedure code pattern for example be stored in, in the specific region (, in memory module, being exclusively used in the system region of storage system data) of duplicative non-volatile memory module 106.In addition, memory management circuitry 202 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Particularly, this ROM (read-only memory) has the code of driving, and, when Memory Controller 104 is enabled, microprocessor unit can first be carried out this steering order that drives the code section will be stored in duplicative non-volatile memory module 106 and be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can turn round these a little steering orders to carry out the runnings such as writing, read and erase of data.

In addition, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 202 can also a hardware pattern be carried out implementation.For example, memory management circuitry 202 comprises that microcontroller, Memory Management Unit, storer write unit, storer reading unit, storer erase unit and data processing unit.It is to be electrically connected to microcontroller that Memory Management Unit, storer write erase unit and data processing unit of unit, storer reading unit, storer.Wherein, Memory Management Unit is in order to manage the physical blocks of duplicative non-volatile memory module 106; Storer writes unit and writes instruction data are write in duplicative non-volatile memory module 106 in order to duplicative non-volatile memory module 106 is assigned; The storer reading unit is in order to assign reading command with reading out data from duplicative non-volatile memory module 106 to duplicative non-volatile memory module 106; Storer is erased unit in order to duplicative non-volatile memory module 106 is assigned to the instruction of erasing so that data are erased from duplicative non-volatile memory module 106; And data processing unit wants to write to the data of duplicative non-volatile memory module 106 and the data that read from duplicative non-volatile memory module 106 in order to processing.

Host interface 204 is instruction and the data that are electrically connected to memory management circuitry 202 and transmit in order to reception and identification host computer system 1000.That is to say, the instruction that host computer system 1000 transmits and data can be sent to memory management circuitry 202 by host interface 204.In this exemplary embodiment, host interface 204 is to be compatible with the SD standard.Yet, it must be appreciated and the invention is not restricted to this, host interface 204 can also be to be compatible with PATA standard, IEEE 1394 standards, PCI Express standard, USB standard, SATA standard, MS standard, MMC standard, CF standard, IDE standard or other applicable data transmission standard.

Memory interface 206 is to be electrically connected to memory management circuitry 202 and in order to access duplicative non-volatile memory module 106.That is to say, the data of wanting to write to duplicative non-volatile memory module 106 can be converted to 106 receptible forms of duplicative non-volatile memory module via memory interface 206.

In the present invention's one exemplary embodiment, Memory Controller 104 also comprises memory buffer 252, electric power management circuit 254 and bug check and correcting circuit 256.

Memory buffer 252 is to be electrically connected to memory management circuitry 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from duplicative non-volatile memory module 106.

Electric power management circuit 254 is to be electrically connected to memory management circuitry 202 and in order to the power supply of control store storage device 100.

Bug check and correcting circuit 256 be electrically connected to memory management circuitry 202 and in order to execution error inspection and correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202, from host computer system 1000, receive while writing instruction, bug check can produce corresponding bug check and correcting code (Error Checking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 256, ECC Code), and memory management circuitry 202 corresponding these data that write instruction can be write in duplicative non-volatile memory module 106 with corresponding bug check and correcting code.Afterwards, when memory management circuitry 202 can read bug check corresponding to these data and correcting code during reading out data from duplicative non-volatile memory module 106 simultaneously, and bug check and correcting circuit 256 can be according to this bug check and correcting code to read data execution error inspection and correction programs.

In general, memory management circuitry 202 can be divided into system region, data field, replacement district and idle district by physical blocks 304 (0)～304 (R).

The physical blocks in data field and idle district is to come from the data of host computer system 1000 in order to storage.Data field is the physical blocks of storage data, and the physical blocks in idle district is the physical blocks in order to the replacement data district.Therefore, the physical blocks in idle district be sky or spendable physical blocks, i.e. no record data or be labeled as invalid data useless.That is to say, the physical blocks in idle district has been performed the running of erasing, or the physical blocks that the physical blocks in idle district is extracted for extracting before storage data can first be performed the running of erasing.

The physical blocks that belongs in logic system region is in order to the register system data, and wherein this system data comprises about the manufacturer of memory chip and model, the physical blocks number of memory chip, physical page number of each physical blocks etc.

Belonging in logic the physical blocks replaced in district is the alternate physical block.For example, the duplicative non-volatile memory module can be reserved 4% physical blocks and uses as changing when dispatching from the factory.That is to say, when the physical blocks in data field, idle district and system region is damaged, the physical blocks of reserving in replacing district is in order to replacing damaged physical blocks (that is, bad physical blocks (bad block)).

Yet, in this exemplary embodiment, memory management circuitry 202 can be merged into a zone (also Cheng 3rd district) by traditional replacement district and idle district and use.That is to say, when having physical blocks to damage, can come the extracts physical block to replace in Cong 3rd district.When having data to keep in, also can Cong 3rd district in the extracts physical block use.

Please refer to Fig. 5, memory management circuitry 202 can at least be divided into physical blocks 304 (0)～304 (R) the first district 580 and Second Region 560.Specifically, the physical blocks that memory management circuitry 202 can be set the first district 580 belongs to the first programming mode, and the physical blocks of setting Second Region 560 belongs to the second programming mode.Wherein, the first programming mode means that all lower physical pages, middle physical page and upper physical page all can be programmed.The second programming mode means to only have lower physical page (also being called the first physical page) to be programmed.In other words, memory management circuitry 202 can be carried out storage data with lower physical page, middle physical page and the upper physical page of each physical blocks in the first district 580.And, in Second Region 560, memory management circuitry 202 is only carried out storage data with the lower physical page of each physical blocks.The physical blocks in the first district 580 is the storage areas that provide a large amount of, but the upper limit of the number of times of relatively erasing (that is, the first critical value) is less.And relative less in the storage area of the physical blocks of Second Region 560, the upper limit of number of times but it is erased (that is, the second critical value) is larger.

When a physical blocks in the first district 580 meets one first damage condition, this physical blocks can be called as the physical blocks of damage.For example, the first damage condition comprises: the number of times of erasing reaches the first critical value, the upper limit that the position number that makes a mistake in misprogrammed or physical blocks can be corrected over bug check and correcting code occurs.When a physical blocks of Second Region 580 meets one second damage condition, this physical blocks can be called as the physical blocks of damage.For example, the second damage condition comprises: the number of times of erasing reaches the second critical value, the upper limit that the position number that makes a mistake in misprogrammed or physical blocks can be corrected over bug check and correcting code occurs.

For example, memory management circuitry 202 can be further subdivided into the 3rd 520Yu data field, district 540 by the first district 580.The 3rd district 520 has comprised physical blocks 304 (0)～304 (A), and data field 540 has comprised physical blocks 304 (A+1)～304 (B), and Second Region has comprised physical blocks 304 (B+1)～304 (P).Yet, in other exemplary embodiment, memory management circuitry 202 also can mark off a system region again by physical blocks 304 (0)～304 (R), the present invention does not limit the number in marked off zone.

In this exemplary embodiment, memory management circuitry 202 can the physical blocks 304 (A+1)～304 (B) of assignment logic block address LBA (A+1)～LBA (B) to map to data field 540.And memory management circuitry 202 can be set up a logical block addresses-physical blocks mapping table, to record the mapping relations between logical block addresses LBA (A+1)～LBA (B) and physical blocks 304 (A+1)～304 (B).Memory management circuitry 202 also can offer host computer system 1000 by logical block addresses LBA (A+1)～LBA (B).Thus, host computer system 1000 just can access logical block addresses LBA (A+1)～LBA (B).

The physical blocks in the 3rd district 520 can be in order to the physical blocks of damaging in replacement data district 540 or Second Region 560.In this exemplary embodiment, while in Ruo tri-districts 520, there is no available physical blocks, memory management circuitry 202 can be declared as write protection (write protect) state by whole memorizer memory devices 100, and data writing again.

Please refer to Fig. 6, when a physical blocks is set while from the first programming mode, being converted to the second programming mode, memory management circuitry 202 can be assigned an instruction to duplicative non-volatile memory module 106, makes the physical blocks that is set to the second programming mode only can provide lower physical page to carry out data writing.That is to say, memory management circuitry 202 can only obtain the physical address of the lower physical page of this physical blocks.For example, after physical blocks 304 (B+1)～304 (B+3) is converted to the second programming mode, physical blocks 304 (B+1)～304 (B+3) only can provide the physical address 0-85 of lower physical page to memory management circuitry 202.After receiving from host computer system 1000 and writing instruction, memory management circuitry 202 can first write to data the lower physical page of physical blocks 304 (B+1)～304 (B+3).Next, memory management circuitry 202 can copy to physical blocks 304 (A+1) to data physical page from physical blocks 304 (B+1)～304 (B+3).

When a physical blocks in the first district 580 meets the first damage condition, memory management circuitry 202 can be set these physical blocks and belong to the second programming mode and be divided into Second Region 560.And memory management circuitry 202 can be set this physical blocks can't be changed into the first programming mode again.

Fig. 7 is the example schematic according to the physical blocks in the physical blocks replacement data district in exemplary embodiment explanation Yong 3rd district.

Please refer to Fig. 7, when the physical blocks 304 (A+1) (also claiming the first physical blocks) of data field 540 meets the first damage condition, mean that the unrenewable lower physical page of physical blocks 304 (A+1), middle physical page and upper physical page carry out data writing.Memory management circuitry 202 can judgement physical blocks 304 (A+1) be the physical blocks of damaging, and the physical blocks in Yong tri-districts 520 is replaced physical blocks 304 (A+1).For example, the physical blocks 304 (0) that memory management circuitry 202 can obtain the 3rd district 520 is replaced physical blocks 304 (A+1).In this hypothesis physical blocks 304 (A+1), be to map to logical block addresses LBA (A+1) originally, therefore when memory management circuitry 202 use physical blocks 304 (0) are replaced physical blocks 304 (A+1), logical block addresses LBA (A+1) can be remapped to physical blocks 304 (0).And memory management circuitry 202 can copy to physical blocks 304 (0) to the valid data in physical blocks 304 (A+1).In addition, memory management circuitry 202 can be divided into Second Region 560 to physical blocks 304 (A+1), and setting physical blocks 304 (A+1) changes the second programming mode into from the first programming mode.Specifically, physical blocks 304 (A+1) is converted into the second programming mode and just can't be transformed back into the first programming mode later again.Due to when only with lower physical page, carrying out data writing, the upper limit of the number of times of erasing of a physical blocks can increase (from the first critical value, becoming the second critical value).Therefore, physical blocks 304 (A+1) can also continue to be used after being set to the second programming mode.

In an exemplary embodiment, memory management circuitry 202 also can first be collected the physical blocks of three damages in the first district 580, and these three physical blocks are divided into to Second Region 560 simultaneously.Yet memory management circuitry 202 also can be divided the more or less physical blocks of number to Second Region 560 simultaneously, the present invention is also not subject to the limits.

Yet, when Dang tri-districts 520 have not had available physical blocks, memory management circuitry 202 also can obtain three and belong to the physical blocks of the second programming mode and be divided to the 3rd district 520 from Second Region 560.These three physical blocks can be in order to replace a physical blocks in the 3rd district 520.Specifically, memory management circuitry 202 can lower physical page, middle physical page and the upper physical page as a physical blocks be used the lower physical page of these three physical blocks.In other words, when Dang tri-districts 520 have not had operable physical blocks, memory management circuitry 202 can be extracted the physical blocks of Second Region 560 and avoid whole memorizer memory devices 100 is declared as to write protection, and then extends its serviceable life.

Please refer to Fig. 8, in step S802, memory management circuitry 202 can at least be divided into the firstth district and Second Region by physical blocks, and the physical blocks of setting the firstth district belongs to the first programming mode, and the physical blocks of setting Second Region belongs to the second programming mode.Wherein the first programming mode means that all physical pages all can be programmed, and the second programming mode means that only the first physical page can be programmed.

In step S804, when the firstth district has physical blocks to meet the first damage condition, memory management circuitry 202 can be divided to Second Region by this physical blocks, sets this physical blocks and belongs to the second programming mode and can't be set back the first programming mode again.Wherein the first damage condition comprises: the number of times of erasing of this physical blocks reaches the first critical value, misprogrammed occurs or the upper limit that the position number that makes a mistake can be corrected over bug check and correcting code.

Yet in Fig. 8, each step has described in detail as above, just repeats no more at this.

[the second exemplary embodiment]

In the first exemplary embodiment, when the firstth district has physical blocks to damage, memory management circuitry 202 just can change the physical blocks of damage into the second programming mode and be divided into Second Region.Yet, in the second exemplary embodiment, memory management circuitry 202 is when Second Region has physical blocks to damage, and just selects a physical blocks from the firstth district, and the physical blocks of selecting is divided into to Second Region and is set as the second programming mode.In addition, in the first exemplary embodiment, memory management circuitry 202 is to take physical blocks to manage duplicative non-volatile memory module 106 as unit, but, in the second exemplary embodiment, memory management circuitry 202 is to take physical page to manage duplicative non-volatile memory module 106 as unit.Yet, in the second exemplary embodiment, memory management circuitry 202 also can be take physical blocks and managed duplicative non-volatile memory module 106 as unit, the present invention is also not subject to the limits.

Fig. 9 is divided into physical blocks the example schematic of the firstth district and Second Region according to an exemplary embodiment explanation.

Please refer to Fig. 9, memory management circuitry 202 can mark off physical blocks 304 (0)～304 (R) the first district 920 and Second Region 940.The first district 920 comprises physical blocks 304 (0)～304 (D), and Second Region 940 comprises physical blocks 304 (D+1)～304 (E).Physical blocks 304 (0)～304 (D) can be set to the first programming mode, and physical blocks 304 (D+1)～304 (E) can be set to the second programming mode.

When memory management circuitry 202, from host computer system 1000, receive one write instruction and data writing after, can first write to the physical blocks in Second Region 940 to data writing.Then, memory management circuitry 202 can copy to the first district 920 to these data writings from Second Region 940.That is to say, the physical blocks of Second Region 940 is as temporary physical blocks, and the physical blocks in the first district 920 can provide large storage area.

Figure 10 take according to an exemplary embodiment explanation example schematic that physical page writes data as unit.

Please refer to Figure 10, logical block addresses LBA (A+1) has comprised logical page address 702 (0)～702 (F), and logical page address 702 (0) is the lower physical page 902 mapped in physical blocks 304 (0).When host computer system 1000 will be changed the data in physical page 902, that can assign access logical page address 702 (0) writes instruction and data writing to memory management circuitry 202.Memory management circuitry 202 can first write to data writing the lower physical page 904 of physical blocks 304 (D+1).Then, it is invalid that memory management circuitry 202 can be labeled as physical page 902, and logical page address 702 (0) is remapped to physical page 904.If what host computer system 1000 had been assigned again an access logical page address 702 (0) writes instruction and data writing, memory management circuitry 202 can write to physical page 906 by data writing, it is invalid that physical page 904 is labeled as, and logical page address 702 (0) is remapped to physical page 906.After aforesaid operations, stored in physical page 902 and 904 is invalid data, and what in physical page 906, store is valid data.There is no available physical page in physical blocks 304 (D+1) after, memory management circuitry 202 also can be used the physical page in physical blocks 304 (D+2) to carry out storage data.The physical blocks that the size of the valid data in physical blocks 304 (D+1), 304 (D+2) and other physical blocks meets the firstth district (for example, during physical blocks 304 (0)) big or small, memory management circuitry 202 can copy back the physical blocks in the firstth district to these valid data.And memory management circuitry 202 can assign with 304 (D+2) instruction of erasing to physical blocks 304 (D+1), for storing other, come from the data writing of host computer system 1000.

In the second exemplary embodiment, after a physical blocks in the first district 920 meets the first damage condition, memory management circuitry 202 can copy to the valid data in this physical blocks in the first district 920 other physical blocks, and can be labeled as this physical blocks the physical blocks of damage.In other words, the first district 920 can comprise a plurality of physical blocks that meet the first damage condition, and these physical blocks can't be under the first programming mode storage data.Specifically, these physical blocks can be set to the second programming mode, in order to the lower physical page of replacing a physical blocks in the first district 920, middle physical page and upper physical page.For instance, when memory management circuitry 202 will copy to the firstth district 920 to valid data from Second Region 940, if the first district 920 has not had the physical blocks can be under the first programming mode during storage data, memory management circuitry 202 can be set as the second programming mode to three physical blocks that meet the first damage condition, and stores valid data with the lower physical page of these three physical blocks.Perhaps, when a physical blocks in the firstth district is damaged, memory management circuitry 202 can be set as the second programming mode to three physical blocks, and replaces a physical blocks by these physical blocks.

Please refer to Figure 11, when physical blocks 304 (0) (also claiming the 3rd physical blocks), while meeting the damage condition, memory management circuitry 202 can obtain and meet the first damage condition physical blocks 304 (1)～304 (3) (also claiming the 4th physical blocks).Memory management circuitry 202 can be set as the second programming mode to physical blocks 304 (1)～304 (3), and uses physical blocks 304 (1)～304 (3) to replace physical blocks 304 (0).Specifically, each logical block addresses LBA (A+1)～LBA (B) can comprise a plurality of logical page address.Wherein at least one logical page address (also claiming the 3rd logical page address) can map to the physical page (also claiming the 3rd physical page) that stores valid data in physical blocks 304 (0).Next, memory management circuitry 202 can copy at least one physical page (also claiming the 4th physical page) in physical blocks 304 (1)～304 (3) to the valid data in the 3rd physical page.And, the 4th physical page that memory management circuitry 202 can remap the 3rd logical page address that maps to physical blocks 304 (0) originally to physical blocks 304 (1)～304 (3).

In the exemplary embodiment shown in Figure 11, memory management circuitry 202 is in the first district 920, not had the physical blocks can be under the first programming mode during storage data, just the physical blocks 304 (1)～304 (3) that meets the first damage condition is set as to the second programming mode.Yet, in other exemplary embodiment, memory management circuitry 202 also can three physical blocks that meet the first damage condition be set as the second programming mode and continue using in first district 920 that names a person for a particular job At All Other Times, the present invention is also not subject to the limits.In addition, in another exemplary embodiment, when a physical page group comprises four physical pages, memory management circuitry 202 also can be replaced a physical blocks by four physical blocks that are set as the second programming mode, and when the physical blocks that is set as the second programming mode 2 physical pages able to programme, memory management circuitry 202 can be replaced a physical blocks by two physical blocks that are set as the second programming mode, and the present invention is also not subject to the limits.

On the other hand, after the physical blocks (also claiming the first physical blocks) of Second Region 940 meets the second damage condition, memory management circuitry 202 can be chosen a physical blocks (also claiming the second physical blocks) and replace the first physical blocks from the first district 920.For example, memory management circuitry 202 can preferentially be selected from the first district 920 the physical blocks physical blocks of use as an alternative that meets the first damage condition.Yet memory management circuitry 202 also can be selected the number of times of erasing between the physical blocks of 0 to the first critical value physical blocks of use as an alternative from the first district 920, the present invention is also not subject to the limits.It should be noted that after the second physical blocks is divided into to Second Region 940, it is that the second programming mode also can't be set back the first programming mode again that memory management circuitry 202 can be set the second physical blocks.

Please refer to Figure 12, in step S1202, memory management circuitry 202 can at least be cut apart the firstth district and Second Region by physical blocks.And the physical blocks that memory management circuitry 202 can be set the firstth district belongs to the first programming mode, and the physical blocks of setting Second Region belongs to the second programming mode.Wherein the first programming mode means that all physical pages all can be programmed, and the second programming mode means that only the first physical page can be programmed.

In step S1204, when the first physical blocks of Second Region meets the second damage condition, memory management circuitry 202 can be replaced the first physical blocks by second physical blocks in the firstth district.It is the second programming mode that memory management circuitry 202 can be set the second physical blocks, and the second physical blocks can't be set to the first programming mode again, wherein the second damage condition comprises: the number of times of erasing of the first physical blocks reaches the second critical value, the first physical blocks and position number that one misprogrammed or the first physical blocks make a mistake occurs surpasses the upper limit that bug check and correcting code can be corrected.

Yet each step in Figure 12 has described in detail as above, just repeats no more at this.

In sum, exemplary embodiment of the present invention has proposed a kind of storage management method, Memory Controller and memorizer memory devices.Wherein when the physical blocks of Second Region is damaged, can with in the firstth district used physical blocks replace.Perhaps, when the physical blocks in the firstth district is damaged, the physical blocks of damage can be set to the second programming mode and continue to use.Thus, can increase the serviceable life of duplicative nonvolatile memory.

Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; have and usually know the knowledgeable in technical field under any; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.

Claims

1. a storage management method, for controlling a duplicative non-volatile memory module, this duplicative non-volatile memory module comprises a plurality of physical location set, each the plurality of physical location set comprises a plurality of physical location groups, each the plurality of physical location group comprises a plurality of physical locations, the plurality of physical location of each the plurality of physical location group at least comprises one first physical location, and wherein this storage management method comprises:

The plurality of physical location set at least is divided into to one first district and a Second Region, those physical location set of setting this firstth district belong to one first programming mode, those physical location set of setting this Second Region belong to one second programming mode, wherein this first programming mode means that those physical locations can be programmed, and this second programming mode means that only this first physical location can be programmed; And

When one first physical location set symbol unification second of this Second Region damages condition, replace this first physical location set with the one second physical location set in this firstth district, wherein set that this second physical location set belongs to this second programming mode and this second physical location set can't be set to this first programming mode again.

2. storage management method according to claim 1, wherein this second damage condition comprises: the number of times of erasing of this first physical location set reaches one second critical value, this first physical location set and position number that one misprogrammed or this first physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

3. storage management method according to claim 1, wherein when this first physical location set symbol of this Second Region should second while damaging condition, the step of with this second physical location set in this firstth district, replacing this first physical location set comprises:

From those physical location set in this firstth district, obtain and meet one first this second physical location set that damages condition and replace this first physical location set, wherein this first damage condition comprises: the number of times of erasing of this second physical location set reaches one first critical value, this second physical location set the upper limit that position number that one misprogrammed or this second physical location set make a mistake can be corrected over a bug check and correcting code occurs.

4. storage management method according to claim 1, wherein when this first physical location set symbol of this Second Region should second while damaging condition, the step of with this second physical location set in this firstth district, replacing this first physical location set comprises:

From those physical location set in this firstth district, obtain the number of times of erasing and replace this first physical location set between this second physical location set of 0 to 1 first critical value.

5. storage management method according to claim 1 also comprises:

When one the 3rd physical location set symbol unification first in this firstth district damages condition, the 3rd physical location set is divided into to this Second Region; And

Set that the 3rd physical location set belongs to this second programming mode and the 3rd physical location set can't be set to this first programming mode again, wherein this first damage condition comprises: the number of times of erasing of the 3rd physical location set reaches one first critical value, the 3rd physical location set and position number that one misprogrammed or the 3rd physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

6. storage management method according to claim 1 also comprises:

When one the 3rd physical location set symbol unification first in this firstth district damages condition, obtain a plurality of the 4th physical location set that meet this first damage condition in this firstth district;

Set those the 4th physical location set and belong to this second programming mode; And

Replace the 3rd physical location set with those the 4th physical location set, wherein this first damage condition comprises: the number of times of erasing of those the 4th physical location set reaches one first critical value, those the 4th physical location set and position number that one misprogrammed or those the 4th physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

7. storage management method according to claim 6, wherein when the 3rd physical location set symbol in this firstth district should first while damaging condition, obtain in this firstth district and belong to this first step of damaging those the 4th physical location set of condition and comprise;

Judge in this firstth district whether have the physical location set can be under this first programming mode storage data, if not, obtain those the 4th physical location set and replace the 3rd physical location set.

8. a memorizer memory devices comprises:

A connector, in order to be electrically connected to a host computer system;

One duplicative non-volatile memory module, comprise a plurality of physical location set, each those physical location set comprises a plurality of physical location groups, each those physical location group comprises a plurality of physical locations, and those physical locations of each those physical location group at least comprise one first physical location; And

One Memory Controller, be electrically connected to this connector and this duplicative non-volatile memory module,

Wherein, this Memory Controller is in order at least to be divided into one first district and a Second Region by those physical location set, those physical location set of setting this firstth district belong to one first programming mode, those physical location set of setting this Second Region belong to one second programming mode, wherein this first programming mode means that those physical locations can be programmed, this second programming mode means that only those first physical locations can be programmed

Wherein, when one first physical location set symbol unification second of this Second Region damages condition, this Memory Controller is replaced this first physical location set in order to the one second physical location set with this firstth district, and sets that this second physical location set belongs to this second programming mode and this second physical location set can't be set to this first programming mode again.

9. memorizer memory devices according to claim 8, wherein this second damage condition comprises: the number of times of erasing of this first physical location set reaches one second critical value, this first physical location set and position number that one misprogrammed or this first physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

10. memorizer memory devices according to claim 9, wherein this Memory Controller is also in order to those physical location set from this firstth district, obtain and meet one first this second physical location set that damages condition and replace this first physical location set, wherein this first damage condition comprises: the number of times of erasing of this second physical location set reaches one first critical value, this second physical location set the upper limit that position number that one misprogrammed or this second physical location set make a mistake can be corrected over a bug check and correcting code occurs.

11. memorizer memory devices according to claim 8, wherein this Memory Controller, also in order to those physical location set from this firstth district, is obtained the number of times of erasing and is replaced this first physical location set between this second physical location set of 0 to 1 first critical value.

12. memorizer memory devices according to claim 8, wherein when one the 3rd physical location set symbol unification first in this firstth district damages condition, this Memory Controller is also in order to be divided into this Second Region by the 3rd physical location set, and set the 3rd physical location set and belong to this second programming mode and can't be set to again this first programming mode, wherein this first damage condition comprises: the number of times of erasing of the 3rd physical location set reaches one first critical value, position number that one misprogrammed or the 3rd physical location set make a mistake occurs and surpasses the upper limit that a bug check and correcting code can be corrected in the 3rd physical location set.

13. memorizer memory devices according to claim 8, when wherein this Memory Controller also damages in order to one the 3rd physical location set in this firstth district, obtain a plurality of the 4th physical location set that meet one first damage condition in the firstth district, set those the 4th physical location set and belong to this second programming mode, and replace the 3rd physical location set with those the 4th physical location set, wherein this first damage condition comprises: the number of times of erasing of those the 4th physical location set reaches one first critical value, position number that one misprogrammed or those the 4th physical location set make a mistake occurs and surpasses the upper limit that a bug check and correcting code can be corrected in those the 4th physical location set.

14. memorizer memory devices according to claim 13, wherein this Memory Controller also in order to judge in this firstth district whether have the physical location set can be under this first programming mode storage data, if not, obtain those the 4th physical location set and replace the 3rd physical location set.

15. a Memory Controller comprises:

One host interface, in order to be electrically connected to a host computer system;

One memory interface, in order to be electrically connected to a duplicative non-volatile memory module, this duplicative non-volatile memory module comprises a plurality of physical location set, each those physical location set comprises a plurality of physical location groups, each those physical location group comprises a plurality of physical locations, and those physical locations of each those physical location group at least comprise one first physical location; And

One memory management circuitry, be electrically connected to this host interface and this memory interface,

Wherein, this memory management circuitry is in order at least to be divided into one first district and a Second Region by those physical location set, those physical location set of setting this firstth district belong to one first programming mode, those physical location set of setting this Second Region belong to one second programming mode, wherein this first programming mode means that those physical locations can be programmed, and this second programming mode means that only those first physical locations can be programmed

Wherein, when one first physical location set symbol unification second of this Second Region damages condition, this memory management circuitry is replaced this first physical location set with the one second physical location set in this firstth district, sets that this second physical location set belongs to this second programming mode and this second physical location set can't be set to this first programming mode again.

16. Memory Controller according to claim 15, wherein this second damage condition comprises: the number of times of erasing of this first physical location set reaches one second critical value, this first physical location set and position number that one misprogrammed or this first physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

17. Memory Controller according to claim 16, wherein this memory management circuitry is also in order to those physical location set from this firstth district, obtain and meet one first this second physical location set that damages condition and replace this first physical location set, wherein this first damage condition comprises: the number of times of erasing of this second physical location set reaches one first critical value, this second physical location set the upper limit that position number that one misprogrammed or this second physical location set make a mistake can be corrected over a bug check and correcting code occurs.

18. Memory Controller according to claim 16, wherein this memory management circuitry, also in order to those physical location set from this firstth district, obtains the number of times of erasing and replaces this first physical location set between this second physical location set of 0 to 1 first critical value.

19. Memory Controller according to claim 15, wherein when one the 3rd physical location set symbol unification first in this firstth district damages condition, this memory management circuitry is also in order to be divided into this Second Region by the 3rd physical location set, set that the 3rd physical location set belongs to this second programming mode and the 3rd physical location set can not be set to this first programming mode again, wherein this first damage condition comprises: the number of times of erasing of the 3rd physical location set reaches one first critical value, position number that one misprogrammed or the 3rd physical location set make a mistake occurs and surpasses the upper limit that a bug check and correcting code can be corrected in the 3rd physical location set.

20. Memory Controller according to claim 15, when wherein this memory management circuitry is also damaged in order to one the 3rd physical location set in this firstth district, obtain a plurality of the 4th physical location set that meet one first damage condition in the firstth district, set those the 4th physical location set and belong to this second programming mode, and replace the 3rd physical location set with those the 4th physical location set, wherein this first damage condition comprises: the number of times of erasing of those the 4th physical location set reaches one first critical value, position number that one misprogrammed or those the 4th physical location set make a mistake occurs and surpasses the upper limit that a bug check and correcting code can be corrected in those the 4th physical location set.

21. Memory Controller according to claim 20, wherein this memory management circuitry also in order to judge in this firstth district whether have the physical location set can be under this first programming mode storage data, if not, obtain those the 4th physical location set and replace the 3rd physical location set.

A 22. storage management method, for controlling a duplicative non-volatile memory module, this duplicative non-volatile memory module comprises a plurality of physical location set, each those physical location set comprises a plurality of physical location groups, each those physical location group comprises a plurality of physical locations, those physical locations of each those physical location group at least comprise one first physical location, and this storage management method comprises:

Those physical location set at least are divided into to one first district and a Second Region, those physical location set of setting this firstth district belong to one first programming mode, those physical location set of setting this Second Region belong to one second programming mode, wherein this first programming mode means that those physical locations can be programmed, and this second programming mode means that only those first physical locations can be programmed; And

When at least one first physical location set symbol unification first in this firstth district damages condition, this at least one first physical location set is divided to this Second Region, set this at least one first physical location set and belong to this second programming mode, and this at least one first physical location set can't be set to this first programming mode again.

23. storage management method according to claim 22, wherein this first damage condition comprises: the number of times of erasing of this at least one the first physical location set reaches one first critical value, this at least one first physical location set and position number that one misprogrammed or this at least one the first physical location set make a mistake occurs surpasses the upper limit that a bug check and correcting code can be corrected.

24. storage management method according to claim 23 also comprises:

This first zoning is divided into to a data field and Yi 3rd district, configures those physical location set to this data field of a plurality of logical block compound mappings;

When this at least one first physical location set symbol should first while damaging condition, judge Gai 3rd district whether have the physical location set can be under this first programming mode storage data, if not, obtain a plurality of the second physical location set from this Second Region; And

Those the second physical location set are divided into to Gai 3rd district.