CN102129353A

CN102129353A - Flash storage system, flash controller and data writing method

Info

Publication number: CN102129353A
Application number: CN2010100039376A
Authority: CN
Inventors: 蔡来福; 陈庆聪
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2010-01-13
Filing date: 2010-01-13
Publication date: 2011-07-20
Anticipated expiration: 2030-01-13
Also published as: CN102866861B; CN102866861A; CN102129353B

Abstract

The invention provides a flash storage system, a flash controller and a data writing method. The flash storage system comprises a flash chip and a flash controller, wherein the flash controller is provided with a second entity unit of the flash chip to serve as a midway cache entity unit corresponding to a first entity unit, and caches the first data which corresponds to a first host writing instruction and the second data which corresponds to the host writing instruction into a cache entity address of the midway cache entity unit; the first data and the second data correspond to a low-speed entity address of the first entity unit; and the flash controller synchronously copies the first data and the second data into the first entity unit from the midway cache entity unit; therefore, the time of writing data into the flash chip is shortened.

Description

Flash memory system, flash controller and method for writing data

Technical field

The present invention relates to a kind of flash memory system, relate in particular to a kind of flash memory system, flash controller and method for writing data of storage data apace.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years, make the consumer also increase rapidly the demand of Storage Media.Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., suitable portable applications, the most suitable being used on the battery-powered product of this class Portable.Memory card is exactly a kind of with the storage device of nand flash memory as Storage Media.Because flash memory volume low capacity is big, so be widely used in the storage of individual significant data.Therefore, the flash memory industry becomes a ring quite popular in the electronic industry in recent years.

In present NAND type flash memory technology, NAND type flash memory can be divided into individual layer memory cell (Single Level Cell according to storable bit number in each memory cell, SLC) NAND type flash memory and multilayer memory cell (Multi Level Cell, MLC) NAND type flash memory.Specifically, when the memory cell to SLC NAND type flash memory carries out sequencing (program), only can carry out the sequencing of single-order, so each memory cell only can store a bit.And the sequencing of the physical blocks of MLC NAND type flash memory can be divided into the multistage.For example, be example with 2 layers of memory cell, the sequencing of physical blocks can be divided into for 2 stages.Phase one is the part that writes of lower page (lower page), its physical characteristics is similar to individual layer memory cell (SingleLevel Cell, SLC) nand flash memory, just can sequencing after finishing the phase one on the page (upperpage), wherein the writing speed of lower page can be faster than the last page.Therefore, the page of each physical blocks can be divided into the page (that is the last page) and the quick page (that is lower page) at a slow speed.

Similarly, in the case of 8 layers of memory cell or 16 layers of memory cell, memory cell can comprise more a plurality of pages and can be so that more the multistage writes.At this, the page that writing speed is the fastest is called lower page, and the slower page of other writing speeds is referred to as the page.For example, the last page comprises a plurality of pages with different writing speeds.In addition, in other embodiments, the last page also can be the slowest page of writing speed, perhaps writing speed the slowest with writing speed partly faster than the writing speed page of the slow page.For example, in 4 layers of memory cell, lower page is the fastest and writing speed time fast page of writing speed, and the last page then is the slowest and writing speed time slow page of writing speed.

With respect to MLC NAND type flash memory, the access speed of SLC NAND type flash memory is very fast.But the storage volume of MLC NAND type flash memory is big and cost is lower.Therefore, the access speed that how to increase MLCNAND type flash memory is the target that those skilled in the art are endeavoured with the usefulness that promotes flash memory.

Summary of the invention

The invention provides a kind of flash memory system, it can improve the speed of data to flash memory that writes effectively.

The invention provides a kind of flash controller, it can improve the speed of data to flash memory that writes effectively.

The invention provides a kind of method for writing data, it can improve the speed of data to flash memory that writes effectively.

Exemplary embodiment of the present invention proposes a kind of flash memory system, and it comprises flash chip and flash controller.Flash chip has a plurality of physical blocks, each physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of quick physical address faster than writing data to the speed of physical address at a slow speed.Flash controller is electrically connected to flash chip, and in order to receive many 3rd data and described the 3rd data are temporary to quick physical address from host computer system, wherein said the 3rd data correspondence is physical address at a slow speed.In addition, when the quantity of temporary the 3rd data to quick physical address reaches a predetermined value, flash controller writes at least a portion of two the 3rd data of described the 3rd data in the physical address at a slow speed of described the 3rd data correspondence in a synchronous mode at least, and wherein this predetermined value is not less than 2.

Exemplary embodiment of the present invention proposes a kind of flash memory system, and it comprises flash chip, connector and flash controller.Flash chip has one first block face and one second block face, wherein the first block face and the second block face comprise a plurality of physical blocks respectively, each physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of quick physical address faster than writing data to the speed of physical address at a slow speed.Connector is in order to be electrically connected to a host computer system.Flash controller is electrically connected to flash chip and connector, be divided into a plurality of solid elements and solid element that will part is divided into a data field and a spare area in order to the physical blocks with the first block face and the second block face, wherein each solid element comprises one of them of physical blocks of one of them and the second block face of the physical blocks of the first block face.At this, flash controller is also in order to receive first data that corresponding first main frame writes instruction from host computer system, one first physical blocks of corresponding one first solid element of this first data wherein, and first physical blocks of this first solid element belongs to the above-mentioned first block face.In addition, flash controller is also got solid element in order to choose a solid element from the spare area midway as corresponding this first solid element soon.Moreover, flash controller is also in order to judge that whether above-mentioned first data are one first physical address at a slow speed of first physical blocks of a small data and corresponding first solid element, and when these first data be small data and corresponding this first at a slow speed during physical address, also in order in one of them of the quick physical address that these first data is temporary in first physical blocks of getting solid element midway soon, wherein this first physical blocks of getting solid element midway soon belongs to the above-mentioned first block face to flash controller.

Exemplary embodiment of the present invention proposes a kind of flash controller, is used to write many data to flash chips.Flash chip has a plurality of physical blocks, each physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of quick physical address faster than writing data to the speed of physical address at a slow speed.This flash controller comprises microprocessor unit, flash interface unit and Memory Management Unit.The flash interface unit is electrically connected to microprocessor unit, and in order to be electrically connected to flash chip.Memory Management Unit is electrically connected to microprocessor unit, and has a plurality of procedure codes and use for microprocessor unit and carry out a plurality of programs.Microprocessor unit is in order to receive many 3rd data and described the 3rd data are temporary to quick physical address from host computer system, wherein said the 3rd data correspondence is physical address at a slow speed.At this, when the quantity of temporary the 3rd data to quick physical address reaches a predetermined value, microprocessor unit also writes in the pairing physical address at a slow speed in a synchronous mode in order at least a portion with two the 3rd data in described the 3rd data at least, and wherein this predetermined value is not less than 2.

Exemplary embodiment of the present invention proposes a kind of flash controller, be used to write many data to flash chips, wherein this flash chip has the first block face and the second block face, the first block face and the second block face comprise a plurality of physical blocks respectively, each physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of quick physical address faster than writing data to the speed of physical address at a slow speed.This flash controller comprises microprocessor unit, flash interface unit, host interface unit and Memory Management Unit.The flash interface unit is electrically connected to microprocessor unit, in order to be electrically connected to flash chip.Host interface unit is electrically connected to microprocessor unit, in order to be electrically connected to a host computer system.Memory Management Unit is electrically connected to microprocessor unit and is electrically connected to microprocessor unit, and has a plurality of procedure codes and use for microprocessor unit and carry out a plurality of programs.Microprocessor unit is divided into a plurality of solid elements in order to the physical blocks with the first block face and the second block face and solid element that will part is divided into a data field and a spare area, and wherein each solid element comprises one of them of physical blocks of one of them and the second block face of the physical blocks of the first block face.At this, microprocessor unit is also in order to receive first data that corresponding first main frame writes instruction from host computer system, one first physical blocks of corresponding one first solid element of first data wherein, and first physical blocks of this first solid element belongs to the above-mentioned first block face.In addition, microprocessor unit is also got solid element in order to choose a solid element from the spare area midway as corresponding this first solid element soon.Moreover microprocessor unit is also in order to judge that whether these first data are first physical address at a slow speed of first physical blocks of small data and corresponding this first solid element.And, when these first data be small data and corresponding this first at a slow speed during physical address, also in order in one of them of the quick physical address that these first data is temporary in first physical blocks of getting solid element midway soon, wherein this first physical blocks of getting solid element midway soon belongs to the above-mentioned first block face to microprocessor unit.

Exemplary embodiment of the present invention proposes a kind of method for writing data, many data that are used for coming from a host computer system write to a flash chip, wherein flash chip has a plurality of physical blocks, each physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of quick physical address faster than writing data to the speed of physical address at a slow speed.The notebook data wiring method comprises many 3rd data of reception and described the 3rd data are temporary to quick physical address from host computer system, and wherein said the 3rd data correspondence is physical address at a slow speed.In addition, the notebook data wiring method also comprises when the quantity of temporary the 3rd data to quick physical address reaches a predetermined value, at least a portion of at least two the 3rd data in described the 3rd data is write in the corresponding physical address at a slow speed in a synchronous mode, and wherein this predetermined value is not less than 2.

Exemplary embodiment of the present invention proposes a kind of method for writing data, many data that are used for coming from a host computer system write to a flash chip, wherein this flash chip has the first block face and the second block face, the first block face and the second block face comprise a plurality of physical blocks respectively, each physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of quick physical address faster than writing data to the speed of physical address at a slow speed.The notebook data wiring method comprises that the physical blocks with the first block face and the second block face is divided into a plurality of solid elements and solid element that will part is divided into a data field and a spare area, and wherein each solid element comprises one of them of physical blocks of one of them and the second block face of the physical blocks of the first block face.The notebook data wiring method also comprises from host computer system and to receive first data that corresponding first main frame writes instruction, first physical blocks of corresponding first solid element of this first data wherein, and first physical blocks of this first solid element belongs to the above-mentioned first block face.The notebook data wiring method also comprise from the spare area, choose a solid element as corresponding first solid element get solid element midway soon, and judge that whether first data are first physical address at a slow speed of first physical blocks of small data and corresponding first solid element.The notebook data wiring method also comprise when first data be that small data and corresponding first is at a slow speed during physical address, first data are temporary in one of them of quick physical address of first physical blocks of getting solid element midway soon, wherein this first physical blocks of getting solid element midway soon belongs to the above-mentioned first block face.

Based on above-mentioned, exemplary embodiment of the present invention can shorten significantly and writes data to the required time of flash memory, promotes the usefulness of flash memory thus.

For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.

Description of drawings

Figure 1A is the host computer system of the use flash memory of the present invention's one exemplary embodiment.

Figure 1B is the synoptic diagram of computer, input/output device and the flash memory of exemplary embodiment of the present invention.

Fig. 1 C is the host computer system of another exemplary embodiment of the present invention and the synoptic diagram of flash memory.

Fig. 2 is the summary calcspar of the flash memory shown in Figure 1A.

Fig. 3 is the summary calcspar of the flash controller of the present invention's one exemplary embodiment.

Fig. 4 A is the summary calcspar of the flash chip of the present invention's one exemplary embodiment.

Fig. 4 B is the summary calcspar of the physical blocks of the present invention's one exemplary embodiment.

Fig. 5 A～5D is the synoptic diagram of the management flash chip of the present invention's one exemplary embodiment.

Fig. 6～14 are the example that writes continuous small data of the present invention's one exemplary embodiment.

Figure 15 is the process flow diagram that the data of the present invention's one exemplary embodiment write.

Main description of reference numerals:

1000: host computer system; 1100: computer;

1102: microprocessor; 1104: random access memory;

1106: input/output device; 1108: system bus;

1110: data transmission interface; 1202: mouse;

1204: keyboard; 1206: display;

1208: printer; 1212: flash disk;

1214: memory card; 1216: solid state hard disc;

1310: digital camera; The 1312:SD card;

The 1314:MMC card; 1316: memory stick;

The 1318:CF card; 1320: embedded storage device;

100: flash memory; 102: connector;

104: flash controller; 106: flash chip;

108: data bus; 110: the chip enable pin;

202: microprocessor unit; 204: Memory Management Unit;

206: host interface unit; 208: the flash interface unit;

252: memory buffer; 254: Power Management Unit;

256: error correction unit; 402: flash memory crystal grain;

412: the first block faces; 414: the second block faces;

422 (0)～422 (N), 424 (0)～424 (N): physical blocks;

430 (0)～430 (N): solid element; 460 (0)～460 (H): logical block;

302: system region; 304: the storage area;

304a: data field; 304b: spare area;

306: replace the district;

S1501、S1503、S1505、S1507、S1509、S1511、S1513、S1515、S1517、

S1519, S1521, S1523, S1525: the step that data write.

Embodiment

Generally speaking, flash memory (being also referred to as flash memory system) comprises flash chip and controller (being also referred to as control circuit).Usually flash memory can use with host computer system, so that host computer system can write to data flash memory or reading of data from flash memory.In addition, flash memory also being arranged is to comprise embedded flash memory and can be executed on the host computer system with substantially as the software of the controller of this embedded flash memory.

Figure 1A is the host computer system of the use flash memory of the present invention's one exemplary embodiment, Figure 1B is the synoptic diagram of computer, input/output device and the flash memory of exemplary embodiment of the present invention, and Fig. 1 C is the host computer system of another exemplary embodiment of the present invention and the synoptic diagram of flash memory.

Please refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and I/O (input/output, I/O) device 1106.Computer 1100 comprise microprocessor 1102, random access memory (random accessmemory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 as Figure 1B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Figure 1B, input/output device 1106 can also comprise other devices.

Flash memory 100 electrically connects by data transmission interface 1110 other elements with host computer system 1000 in embodiments of the present invention.Data can be write to flash memory 100 or reading of data from flash memory 100 by microprocessor 1102, random access memory 1104 with the processing of input/output device 1106.For example, flash memory 100 can be flash disk 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 shown in Figure 1B.

Generally speaking, but host computer system 1000 can be any system of storage data substantially.Though in this exemplary embodiment, host computer system 1000 is to explain with computer system, yet host computer system 1000 can be systems such as digital camera, video camera, communicator, audio player or video player in another exemplary embodiment of the present invention.For example, be digital camera (video camera) 1310 o'clock in host computer system, flash memory then is its employed SD card 1312, mmc card 1314, memory stick (memorystick) 1316, CF card 1318 or embedded storage device 1320 (shown in Fig. 1 C).Embedded storage device 1320 comprise the built-in multimedia card (Embedded MMC, eMMC).What deserves to be mentioned is that the built-in multimedia card is directly to be electrically connected on the substrate of host computer system.

Fig. 2 is the summary calcspar of the flash memory shown in the 1A.

Please refer to Fig. 2, flash memory 100 comprises connector 102, flash controller 104 and flash chip 106.

Connector 102 is electrically connected to flash controller 104 and in order to be electrically connected to host computer system 1000.In this exemplary embodiment, connector 102 is secure digital (secure digital, SD) interface connector.Yet, it must be appreciated and the invention is not restricted to this, connector 102 also can be universal serial bus (Universal Serial Bus, USB) connector, Institute of Electrical and Electric Engineers (Institute ofElectrical and Electronic Engineers, IEEE) 1394 connectors, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, PCI Express) connector, Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) connector, memory stick (Memory Stick, MS) interface connector, Multi Media Card (Multi Media Card, MMC) interface connector, compact flash (Compact Flash, CF) interface connector, integrated device electronics (IntegratedDevice Electronics, IDE) interface connector or other connectors that is fit to.

Flash controller 104 can be carried out a plurality of logic gates or the steering order with hardware pattern or firmware pattern, and carries out the runnings such as writing, read and erase of data in flash chip 106 according to the instruction of host computer system 1000.

Please refer to Fig. 3, flash controller 104 comprises microprocessor unit 202, Memory Management Unit 204, host interface unit 206, flash interface unit 208.

Microprocessor unit 202 is the main control unit of flash controller 104, in order to carry out a memory management firmware code with host interface unit 206 and flash interface unit 208 cooperative cooperatings such as grade to carry out the various runnings of flash memory 100.

Memory Management Unit 204 is electrically connected to microprocessor unit 202, so that microprocessor unit 202 is carried out the data access mechanism and block management mechanism according to this exemplary embodiment, the running of Memory Management Unit 204 will elaborate in following cooperation is graphic in order to collocation microprocessor unit 202.

In this exemplary embodiment, Memory Management Unit 204 is to be embodied in the flash controller 104 with a firmware pattern.For example, the Memory Management Unit 204 that will comprise a plurality of steering orders (for example is burned onto a program storage, ROM (read-only memory) (Read Only Memory, ROM)) be embedded in the flash controller 104 in and with this program storage, when flash memory 100 runnings, a plurality of steering orders of Memory Management Unit 204 can be carried out to finish the data access mechanism and block management mechanism according to the embodiment of the invention by microprocessor unit 202.

In another exemplary embodiment of the present invention, the steering order of Memory Management Unit 204 also can the procedure code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the flash chip) of flash chip 106.In addition, Memory Management Unit 204 can have a ROM (read-only memory) (not shown), and a random access memory (Random Access Memory, RAM) (not shown).Wherein, this ROM (read-only memory) has one and drives the sign indicating number section, in order to when flash controller 104 activations, carry out this earlier by microprocessor unit 202 and drive the sign indicating number section, so that microprocessor unit 202 will be stored in earlier after the steering order of the Memory Management Unit 204 in the flash chip 106 is sent to the random access memory of Memory Management Unit 204, carry out data access mechanism of the present invention and block management mechanism according to these steering orders again.In addition, in another exemplary embodiment of the present invention, Memory Management Unit 204 also can a hardware pattern be embodied in the flash controller 104.

Instruction and data that host interface unit 206 is electrically connected to microprocessor unit 202 and is transmitted in order to reception and identification host computer system 1000.That is to say that instruction that host computer system 1000 is transmitted and data can be sent to microprocessor unit 202 by host interface unit 206.In this exemplary embodiment, host interface unit 206 corresponding connectors 102 are the SD interface.Yet, it must be appreciated to the invention is not restricted to this that host interface unit 206 also can be PATA interface, USB interface, IEEE1394 interface, PCI Express interface, SATA interface, MS interface, MMC interface, CF interface, ide interface or other data transmission interfaces that is fit to.

Flash interface unit 208 is electrically connected to microprocessor unit 202 and in order to access flash chip 106.That is to say that the data of desiring to write to flash chip 106 can be converted to 106 receptible forms of flash chip via flash interface unit 208.

In the present invention's one exemplary embodiment, flash controller 104 also comprises memory buffer 252.Memory buffer 252 is electrically connected to microprocessor unit 202 and in order to the temporary data that come from the data and instruction of host computer system 1000 or come from flash chip 106.

In the present invention's one exemplary embodiment, flash controller 104 also comprises Power Management Unit 254.Power Management Unit 254 be electrically connected to microprocessor unit 202 and in order to control flash memory 100 power supply.

In the present invention's one exemplary embodiment, flash controller 104 also comprises error correction unit 256.Error correction unit 256 is electrically connected to microprocessor unit 202 and in order to carry out an error-correcting routine to guarantee the correctness of data.Specifically, when receiving main frame from host computer system 1000, microprocessor unit 202 writes when instruction, error correction unit 256 can write the bug check and correcting code (the Error Checking and Correcting Code that data produce correspondence that write of instruction for corresponding this main frame, ECCCode), and microprocessor unit 202 this can be write data and write in the flash chip 106 with corresponding error-correcting code.Afterwards, when microprocessor unit 202 can read the error-correcting code of this data correspondence during reading of data simultaneously from flash chip 106, and error correction unit 256 can be according to the data execution error correction program of this error-correcting code to being read.

Referring again to Fig. 2, flash chip 106 is Storage Medias of flash memory 100, comes from the data of host computer system 1000 in order to storage.Flash chip 106 is to electrically connect with flash controller 104 by a data bus (DataBus) 108 and a chip enable pin (Chip Enable Pin) 110.In this exemplary embodiment, flash chip 106 is multilayer memory cell (Multi Level Cell, a MLC) nand flash memory chip.

Fig. 4 A is the summary calcspar of the flash chip of the present invention's one exemplary embodiment, and Fig. 4 B is the summary calcspar of the physical blocks of the present invention's one exemplary embodiment.

Please refer to Fig. 4 A and 4B, flash chip 106 is made up of 402 of flash memory crystal grain (die).It must be appreciated, though exemplary embodiment flash chip 106 of the present invention formed by 1 flash memory crystal grain, yet, the invention is not restricted to this, in another exemplary embodiment of the present invention, flash chip can be made up of a plurality of flash memory crystal grain.

Flash memory crystal grain 402 has the first block face (Plane) 412 and the second block face 414.The first block face 412 has physical blocks 422 (0)～422 (N), and the second block face 414 has physical blocks 424 (0)～424 (N).Physical blocks is the least unit of erasing.That is each physical blocks contains the memory cell of being erased in the lump of minimal amount.Each physical blocks can be divided into several physical address (that is physical page (page)) usually.Because in this exemplary embodiment, flash chip 106 is the MLC nand flash memory chip, therefore, physical page is the minimum unit of sequencing (program).In other words, physical page is the minimum unit that writes data or reading of data.Each physical page generally includes user data field and redundant area.The user data field is in order to storage user's data, and redundant area is in order to data (for example, the bug check and the correcting code (Error Checking and Correcting Code, ECC Code) of stocking system.In this exemplary embodiment, the capacity of each physical page be 8 kilobyte (kilobyte, KB).In addition, in this exemplary embodiment, flash chip 106 is 2 layers of memory cell flash chip, and the physical address of physical blocks 422 (0)～422 (N) and physical blocks 424 (0)～424 (N) can be distinguished quick physical address (also being called the quick page) and physical address (also being called the page at a slow speed) at a slow speed according to its sequencing speed.Particularly, write the speed of the extremely quick physical address of data far faster than writing the data speed of physical address extremely at a slow speed.For example, with solid element 430 (S+1) is example, (0) physical address of physical blocks, (2) physical address, (4) physical address ... (K-1) is quick physical address, and (1) physical address, (3) physical address, (5) physical address ... (K) physical address is physical address at a slow speed, and wherein K is an odd-integral number.Yet, it must be appreciated that in another exemplary embodiment of the present invention, flash chip 106 also can be 3 layers of memory cell flash chip, 4 layers of memory cell flash chip or other multilayer memory cell flash chips.

What deserves to be mentioned is, in this exemplary embodiment, the first block face 412 and the second block face 414 are configured in the flash memory crystal grain 402, and flash controller 104 transmits data to the first block face 412 and the second block face 414 or receive data from the first block face 412 and the second block face 414 by single data bus 108.Yet, have in the example of a plurality of flash memory crystal grain at flash chip, the first block face 412 also can be configured in the different flash memory crystal grain with the second block face 414, and flash controller 104 transfers data to the first block face 412 and the second block face 414 respectively by different data buss.

In this exemplary embodiment, the physical page number of each physical blocks is for having 128, yet, it must be appreciated that the invention is not restricted to this, the physical page number of each physical blocks also can be 192,256 or other suitable page numbers.In addition, the physical blocks of the first block face 412 and the second block face 414 also can be grouped into several zones (zone) usually, comes management entity block 422 (0)～422 (N) and physical blocks 424 (0)～424 (N) can increase the parallel degree of operation execution and the complexity of streamlining management with each distinct area.

In addition, the microprocessor unit 202 of flash controller 104 can logically be grouped into a plurality of solid elements with the physical blocks of the first block face 412 and the second block face 414 and manages.For example, 1 solid element comprises 2 physical blocks, and with solid element as the unit of erasing.In exemplary embodiment of the present invention, physical blocks 422 (0)～422 (N) can logically be grouped into solid element 430 (0)～430 (N) with physical blocks 424 (0)～424 (N).It must be appreciated, although this exemplary embodiment is to manage with the solid element that 2 physical blocks are formed.Yet, the invention is not restricted to this, in another exemplary embodiment of the present invention, 1 solid element also can be made up of the physical blocks more than 3.

It must be appreciated that when this described the running of physical blocks of flash memory, coming the application entity block with speech such as " extraction ", " exchange ", " grouping ", " rotating " was in logic notion.That is to say that the physical location of the physical blocks of flash memory is not changed, but in logic the physical blocks of flash memory is operated.

Please refer to Fig. 5 A, microprocessor unit 202 can logically be grouped into solid element 430 (0)～430 (N) system region 302, storage area 304 and replace district 306.

The solid element that belongs to system region 302 in logic is in order to the register system data, wherein this system data comprises the block face number about the manufacturer of flash chip and model, each flash memory crystal grain, the physical blocks number of each block face, the page number of each physical blocks etc.

The solid element that belongs to storage area 304 in logic is in order to store the data that host computer system 1000 is write.That is to say that flash memory 100 can use the solid element that is grouped into storage area 304 to store the data that host computer system 1000 is write practically.Particularly, in this exemplary embodiment, microprocessor unit 202 is grouped into data field 304a and spare area 304b with the solid element of storage area 304.The solid element of data field 304a is exactly the solid element that the logical block of 1000 accesses of host computer system is shone upon.That is to say that the solid element of data field 304a is for storing the unit of valid data.The solid element of spare area 304b is in order to the solid element among the data field 304a that rotates.Therefore, the solid element in spare area 304b is empty or spendable unit, i.e. no record data or be labeled as invalid data useless.That is to say that the solid element of data field 304a and spare area 306b can store the data that 1000 pairs of flash memories 100 of host computer system write in the mode of rotating.

Please be simultaneously with reference to Fig. 5 B～5D, for example, when flash controller 104 receives from host computer system 1000 that main frame writes instruction and when desiring to write data to the solid element 430 (S+1) of data field 304a, microprocessor unit 202 can extract the rotate solid element 430 (S+1) of data field 304a of solid element 430 (D+1) from spare area 304b.Yet, when microprocessor unit 202 write to solid element 430 (D+1) with new data, microprocessor unit 202 can not moved all valid data in the solid element 430 (S+1) at once to solid element 430 (D+1) and the solid element 430 (S+1) of erasing.Specifically, microprocessor unit 202 can write physical address valid data before (promptly with desiring in the solid element 430 (S+1), the 0th physical address and the 1st physical address) be copied to solid element 430 (D+1) (shown in Fig. 5 B), and new data (that is, the 2nd physical address of solid element 310-(D+1) and the 3rd physical address) is write to solid element 430 (D+1) (shown in Fig. 5 C).At this moment, microprocessor unit 202 is promptly finished the action that writes.Because the valid data in the solid element 430 (S+1) might be in next operation (for example, main frame writes instruction) in become invalidly, therefore at once all valid data in the solid element 430 (S+1) are moved to replacing solid element 430 (D+1) and may be caused meaningless moving.In this exemplary embodiment, the action of temporarily keeping this mother and sons' transient state relation (that is, solid element 430 (S+1) and solid element 430 (D+1)) is called unlatching (open) mothers and sons unit.

Afterwards, in the time the content of solid element 430 (S+1) and solid element 430 (D+1) really need being merged, microprocessor unit 202 can be put in order solid element 430 (S+1) and solid element 430 (D+1) and be a solid element, promote the service efficiency of block thus, at this, the action that merges the mothers and sons unit is called closes (close) mothers and sons unit.For example, shown in Fig. 5 D, when closing the mothers and sons unit, microprocessor unit 202 can be with remaining valid data in the solid element 430 (S+1) (promptly, the 4th physical address page or leaf～K physical address) is copied to replacement solid element 433 (D+1), then solid element 430 (S+1) is erased and be associated to spare area 304b, simultaneously, (D+1) is associated to data field 304a with solid element 430.

Belong to the solid element that replaces in the district 306 in logic and substitute solid element.For example, flash chip 106 can be reserved 4% physical blocks and uses as changing when dispatching from the factory.That is to say, when the solid element damage in system region 302 and the storage area 304, be reserved in the solid element that replaces in the district 306 in order to replacing damaged solid element (that is bad physical blocks (bad block)).Therefore, if replace when still having normal physical blocks in the district 306 and the physical blocks damage taking place, Memory Management Unit 204 can be extracted the physical blocks that normal physical blocks is changed damage from replace district 306.If when no normal physical blocks and generation physical blocks were damaged in the replacement district 306, then flash memory 100 will be declared to be write protection (write protect) state, and can't write data again.

Particularly, the quantity of the solid element in system region 302, storage area 304 and replacement district 306 can be different according to different flash memory specifications.In addition, it must be appreciated that in the running of flash memory 100, solid element is associated to system region 302, storage area 304 can dynamically change with the grouping relation that replaces district 306.For example, when the solid element in the storage area damages and the solid element that is substituted the district when replacing, the solid element that then replaces the district originally can be associated to the storage area.

In this exemplary embodiment, microprocessor unit 202 configuration logic addresses are beneficial to carry out data access for host computer system 1000 in the solid element of the above-mentioned mode of rotating.In addition, microprocessor unit 202 can be grouped into logical block 460 (0)～460 (H) with the logical address that is provided, and logical block 460 (0)～460 (H) is mapped to the solid element (shown in Fig. 5 A) of data field 304a.

For example, be mapped in the example of solid element 430 (S+1) in logical block 460 (0), when host computer system 1000 desires write to the logical address that belongs to logical block 460 (0) with data, microprocessor unit 202 can be discerned logical block 460 (0) under this logical address according to a dispensing unit (not shown) or an arithmetic expression.Afterwards, microprocessor unit 202 can be discerned the solid element 430 (S+1) of mapping logic unit 460 (0) according to logical block-solid element mapping table (logicalunit-physical unit mapping table); From spare area 304b, extract solid element 430 (D+1); And the data that the effective legacy data in the solid element 430 (S+1) and host computer system 1000 are desired to write are write to solid element 430 (D+1).Then, microprocessor unit 202 can upgrade logical block-solid element mapping table so that logical block 460 (0) is remapped to solid element 430 (D+1).

Particularly, in this exemplary embodiment, except above-mentioned general write operation (shown in Fig. 5 B～5D), microprocessor unit 202 can extract the solid element conduct and get solid element midway soon from spare area 304b, and the small data of physical address is temporary in the quick physical address of midway getting soon in the solid element with desiring to write at a slow speed.Particularly, microprocessor unit 202 can with many be temporary in get solid element midway soon data sync ground sequencing to the pairing physical address at a slow speed of these data, write the speed of data with lifting.At this, when the data of desiring to write when being less than or equal to the capacity of a physical address (that is, physical page), microprocessor unit 202 can be considered as small data with these data.For example, as mentioned above, the capacity of each physical address is 8KB, so microprocessor unit 202 meetings are considered as small data with the data that data volume be less than or equal to 8KB.

Please refer to Fig. 6, suppose that in logical block 460 (0) be under the state of mapping solid element 430 (S+1), if host computer system 1000 is assigned first main frame and is write instruction and come to begin writing data and the data desiring to write when being small data from (0) logical address of logical block 460 (0), microprocessor unit 202 can extract solid element 430 (D+1) and microprocessor unit 202 from spare area 304b can judge that being used to write (0) physical address (that is (0) physical address of physical blocks 422 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is quick physical address.Based on this, microprocessor unit 202 can directly write to the data that corresponding this main frame write instruction in (0) physical address of physical blocks 422 (D+1) of solid element 430 (D+1).What deserves to be mentioned is, as mentioned above, therefore the sequencing of flash chip 106 is to be unit with the physical address, if when respective hosts writes the discontented physical address of the size of data of instruction, microprocessor unit 202 can be that the size of a physical address is carried out sequencing with data filling.

Please refer to Fig. 7, if assigning second main frame in host computer system 1000 under the state shown in Figure 6 writes instruction and comes to begin writing data and the data desiring to write when being small data from (1) logical address of logical block 460 (0), microprocessor unit 202 can judge that being used to write (1) physical address (that is (0) physical address of physical blocks 424 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is quick physical address.Based on this, microprocessor unit 202 can directly write to the data that corresponding this main frame write instruction in (0) physical address of physical blocks 424 (0) of solid element 430 (D+1).

Please refer to Fig. 8, if assigning the 3rd main frame in host computer system 1000 under the state shown in Figure 7 writes instruction and comes to begin writing data and the data desiring to write when being small data from (2) logical address of logical block 460 (0), microprocessor unit 202 can judge that being used to write (2) physical address (that is (1) physical address of physical blocks 422 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is physical address at a slow speed.Based on this, microprocessor unit 202 can extract solid element 430 (D+2) and get solid element midway soon as correspondent entity unit 430 (D+1) from spare area 304b, and the data that corresponding this main frame write instruction are temporary to the quick physical address (that is (0) physical address of physical blocks 422 (D+2)) of getting solid element 430 (D+2) midway soon.At this, the physical blocks of getting solid element 430 (D+2) midway soon is also referred to as gets physical blocks midway soon.

Please refer to Fig. 9, if assigning the 4th main frame in host computer system 1000 under the state shown in Figure 8 writes instruction and comes to begin writing data and the data desiring to write when being small data from (3) logical address of logical block 460 (0), microprocessor unit 202 can judge that being used to write (3) physical address (that is (1) physical address of physical blocks 424 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is physical address at a slow speed.Based on this, microprocessor unit 202 can write corresponding this main frame the temporary quick physical address (that is, getting (0) physical address of physical blocks 424 (D+2) midway soon) of extremely getting solid element 430 (D+2) midway soon of data of instruction.

Please refer to Figure 10, if assigning the 5th main frame in host computer system 1000 under the state shown in Figure 9 writes instruction and comes to begin writing data and the data desiring to write when being small data from (4) logical address of logical block 460 (0), microprocessor unit 202 can judge that being used to write (4) physical address (that is (2) physical address of physical blocks 422 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is quick physical address.Based on this, microprocessor unit 202 can will be temporary in (2) physical address of getting correspondent entity unit 430 (D+1) in the solid element 430 (D+2) midway soon and the data of (3) physical address and duplicate back in (1) physical address of (1) physical address of physical blocks 422 (D+1) and physical blocks 424 (D+1), and the data that again this main frame of correspondence write instruction afterwards write in (2) physical address of physical blocks 422 (D+1) of solid element 430 (D+1).What deserves to be mentioned is, because in (1) physical address of (2) physical address of correspondent entity unit 430 (D+1) and (1) physical address that (3) physical address has duplicated back physical blocks 422 (D+1) and physical blocks 424 (D+1), the data that therefore are temporary in (0) physical address of getting physical blocks 422 (D+2) midway soon of getting solid element 430 (D+2) midway soon and (0) physical address of getting physical blocks 424 (D+2) midway soon can be marked as invalid data.

Particularly, physical blocks 422 (D+1) and physical blocks 424 (D+1) belong to the first block face 412 and the second block face 414 respectively, thus microprocessor unit 202 understand with the method for synchronization with the data programization of (2) physical address of correspondent entity unit 430 (D+1) and (3) physical address to (1) physical address of (1) physical address of physical blocks 422 (D+1) and physical blocks 424 (D+1).Based on this, the time that writes data can be shortened effectively.For example, in this exemplary embodiment, because the first block face 412 and the second block face 414 are configured in the same flash memory crystal grain 402, microprocessor unit 202 uses the pair of pages faces to write (two plane program) instruction or pair of pages face and duplicates back and deposit (two plane copyback) and instruct synchronously the data with two physical address to be copied to solid element 430 (D+1) from get solid element 430 (D+2) midway soon.It must be appreciated that the physical address that writes simultaneously is not limited to two, also can be three or other most physical address.

What deserves to be mentioned is, in another exemplary embodiment of the present invention, when the first block face 412 and the second block face 414 are configured in different flash memory crystal grain, for example, microprocessor unit 202 from midway soon get solid element 430 (D+2) is copied to solid element 430 (D+1) with the data of two physical address with the part method of synchronization with interleaving mode (interleave mode).Specifically, write data to the program of flash memory crystal grain and can divide into data transmission (transfer) and two parts of data programization (program).When host computer system 1000 is desired in flash memory 100 storage data; to the intragranular buffer zone of flash memory, flash memory crystal grain can be with the data programization in the buffer zone to the memory cell of flash memory module crystal grain afterwards with data transmission for microprocessor unit 202 meetings the passing through data input/output bus of flash controller 104.At this so-called interleaving mode, be exactly in the example of two flash memory crystal grain that use same data input/output bus transmission data, utilize one of them flash memory crystal grain just carrying out the data sequencing during transmit data and give another flash memory crystal grain.Then, in two flash memory crystal grain at least partial data be to be programmed in the corresponding memory cell in mode synchronously.

Please refer to Figure 11, if assigning the 6th main frame in host computer system 1000 under the state shown in Figure 10 writes instruction and comes to begin writing data and the data desiring to write when being small data from (5) logical address of logical block 460 (0), microprocessor unit 202 can judge that being used to write (5) physical address (that is (2) physical address of physical blocks 424 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is quick physical address.Based on this, microprocessor unit 202 can directly write to the data that corresponding this main frame write instruction in (2) physical address of physical blocks 424 (D+1) of solid element 430 (D+1).

Please refer to Figure 12, if assigning the 7th main frame in host computer system 1000 under the state shown in Figure 11 writes instruction and comes to begin writing data and the data desiring to write when being small data from (6) logical address of logical block 460 (0), microprocessor unit 202 can judge that being used to write (6) physical address (that is (3) physical address of physical blocks 422 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is physical address at a slow speed.Based on this, microprocessor unit 202 can write corresponding this main frame the temporary quick physical address (that is, getting (2) physical address of physical blocks 422 (D+2) midway soon) of extremely getting solid element 430 (D+2) midway soon of data of instruction.

Please refer to Figure 13, if assigning the 8th main frame in host computer system 1000 under the state shown in Figure 12 writes instruction and comes to begin writing data and the data desiring to write when being small data from (7) logical address of logical block 460 (0), microprocessor unit 202 can judge that being used to write (7) physical address (that is (3) physical address of physical blocks 424 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is physical address at a slow speed.Based on this, microprocessor unit 202 can write corresponding this main frame the temporary quick physical address (that is, getting (2) physical address of physical blocks 424 (D+2) midway soon) of extremely getting solid element 430 (D+2) midway soon of data of instruction.

Please refer to Figure 14, if assigning the 9th main frame in host computer system 1000 under the state shown in Figure 13 writes instruction and comes to begin writing data and the data desiring to write when being small data from (8) logical address of logical block 460 (0), microprocessor unit 202 can judge that being used to write (8) physical address (that is (4) physical address of physical blocks 422 (D+1)) of solid element 430 (D+1) that this main frame writes the data of instruction is quick physical address.Based on this, microprocessor unit 202 can will be temporary in (6) physical address of getting correspondent entity unit 430 (D+1) in the solid element 430 (D+2) midway soon and the data of (7) physical address and duplicate back in (3) physical address of (3) physical address of physical blocks 422 (D+1) and physical blocks 424 (D+1), and the data that again this main frame of correspondence write instruction afterwards write in (4) physical address of physical blocks 422 (D+1) of solid element 430 (D+1).And the data that are temporary in (2) physical address of getting physical blocks 422 (D+2) midway soon of getting solid element 430 (D+2) midway soon and (2) physical address of getting physical blocks 424 (D+2) midway soon can be marked as invalid data.Same, physical blocks 422 (D+1) and physical blocks 424 (D+1) belong to the first block face 412 and the second block face 414 respectively, so microprocessor unit 202 is understood synchronously the data programization of (6) physical address of correspondent entity unit 430 (D+1) and (7) physical address to (3) physical address of (3) physical address of physical blocks 422 (D+1) and physical blocks 424 (D+1).Based on this, the time that writes data can be shortened effectively.

In this exemplary embodiment, when the physical address of getting the pairing solid element of solid element has midway soon been write full data, microprocessor unit 202 can be got solid element midway soon to this and carry out erase operation for use, and the solid element that will erase is associated to spare area 304b.What deserves to be mentioned is that during the running of flash memory 100, microprocessor unit 202 can be the solid element configuration that a plurality of logical block shines upon and gets solid element midway soon.That is to say have under the enough available physical blocks at spare area 304b, solid element is got in the solid element configuration that microprocessor unit 202 shines upon for a plurality of logical block discriminably midway soon, writes the speed of data with lifting.

Comprehensive above-mentioned example, microprocessor unit 202 can will be desired sequencing to the small data of physical address at a slow speed earlier and be temporary in the quick physical address of getting solid element midway soon of correspondence, and the mode that re-uses synchronization programization when the quantity of temporary small data reaches a predetermined value will write in the solid element together corresponding to the small data of a plurality of physical address at a slow speed, promote the efficient that data write thus.Be worth mentioning is at above-mentioned example, because flash chip 106 is 2 layers of memory cell flash chip, therefore, when writing 2 data that belong to physical address at a slow speed continuously in solid element, microprocessor unit 202 will write to temporary small data in the corresponding physical address.Based on this, this predetermined value is to be set at 2.Yet, it must be appreciated that the invention is not restricted to this, this predetermined value can be because of other the suitable numerical value that is set at of different multilayer memory body flash chip correspondences.

For example, writing instruction with the described main frame of above-mentioned Fig. 6～Figure 10 is example, and in this exemplary embodiment, 5 host computer systems of sequencing required time of instruction comprises 1 of time of 5 quick physical address of sequencing and sequencing time of physical address at a slow speed.Yet in same example, in traditional wiring method, 5 host computer systems of sequencing required time of instruction comprises 2 of time of 3 quick physical address of sequencing and sequencing time of physical address at a slow speed.As mentioned above, since write data to time of quick physical address far faster than writing data to time of physical address at a slow speed.Therefore, compared to traditional method for writing data, carry out the quick physical address of 2 secondary programizations and can save 1 secondary programization at a slow speed under the situation of physical address, the flash memory 100 of this exemplary embodiment can significantly shorten the required time of data that writes.

According to above-mentioned principle, in the MLC NAND type flash memory of 3 layers of memory cell (three bits per cell) or other number multilayer memory cells, it is temporary earlier to middling speed or physical address fast also can to write the data of physical address at a slow speed, maybe will write at a slow speed or the data of middling speed physical address temporary earlier to physical address fast.Afterwards, when the equal and opposite in direction of the data that are temporary in quick physical address duplicates back when depositing (multi-plane copyback) instruction or multipage face writing the predetermined entity address number that instruction (multi-plane program) instruction can write in the write-once program in the multipage face, utilize the multipage face to duplicate back again to deposit and instruct or the multipage face writes that the data of will be kept in write to the middling speed physical address of correspondence or at a slow speed in the physical address.

Similarly, in another exemplary embodiment, in the MLC NAND type flash memory of 3 layers of memory cell (three bits per cell) or other number multilayer memory cells, it is temporary earlier to middling speed or physical address fast also can to write the data of physical address at a slow speed, maybe will write at a slow speed or the data of middling speed physical address temporary earlier to physical address fast.Afterwards, when the size of the data that are temporary in quick physical address is not less than two pages, utilize interleaving mode (interleave mode) that the data of these physical address are write to corresponding middling speed physical address or at a slow speed the physical address with the part method of synchronization from quick physical address again.

Please refer to Figure 15, microprocessor unit 202 receives main frames from host computer system 1000 and writes the data that instruction and corresponding this main frame write instruction in step S1501.

Microprocessor unit 202 writes the corresponding logical address of instruction according to this main frame and judges logical block under this logical address in step S1503, and know the solid element that this logical block is shone upon according to logical block-solid element mapping table, and microprocessor unit 202 judges whether the data that corresponding this main frame writes instruction are small data in step S1505.

If the data that corresponding this main frame writes instruction are non-to be small data, then can to carry out general write operation programs (shown in Fig. 5 B～5C) these data are write in the solid element that is shone upon at microprocessor unit among the step S1507 202.

If judge that in step S1505 the data that corresponding this main frame writes instruction are small data, then microprocessor unit 202 can judge whether the pairing physical address of these data (that is, this main frame writes the physical address that the corresponding logical address of instruction is shone upon) is quick physical address in step S1509.If the pairing physical address of these data is quick physical address, what then microprocessor unit 202 can judge whether to have solid element that corresponding this logical block shines upon in step S1511 gets solid element midway soon.

If do not have solid element that corresponding this logical block shines upon get solid element soon midway the time, microprocessor unit 202 data can be write direct so far (as Fig. 6 and shown in Figure 7) in the pairing physical address of data in step S1513 then.

If have solid element that corresponding this logical block shines upon get solid element soon midway the time, then microprocessor unit 202 can judge getting soon of correspondence whether have valid data (that is whether the valid data of the physical address before, corresponding this main frame writes the physical address of instruction are temporary in corresponding getting in the solid element soon midway) in the solid element midway in step S1515.

If judge in step S1515 when getting soon of correspondence do not have valid data in the solid element midway, then step S1517 microprocessor unit 202 can write direct data so far (as shown in figure 11) in the pairing physical address of data.If when getting soon of correspondence has valid data in the solid element midway, then microprocessor unit 202 can duplicate the valid data solid element that shines upon of logical block so far from getting soon of correspondence midway the solid element in step S1519, and afterwards data is write so far in the pairing physical address of data (as shown in figure 10).

If judge the non-quick physical address of the pairing physical address of these data in step S1509, what then microprocessor unit 202 can judge whether to have solid element that corresponding this logical block shines upon in step S1521 gets solid element midway soon.If have solid element that corresponding this logical block shines upon get solid element soon midway the time, then microprocessor unit 202 can be temporary in (as Fig. 9, Figure 12 and shown in Figure 13) in the quick physical address of so far getting solid element midway soon with data in step S1523.

If in step S1521, judge do not have solid element that corresponding this logical block shines upon get solid element soon midway the time, then in step S1525 microprocessor unit 202 can from spare area 304b, extract a solid element as correspondence get solid element midway soon, and data are temporary in to the quick physical address of getting solid element midway soon that is extracted (as shown in Figure 8).

In sum, the method for writing data of exemplary embodiment of the present invention can with correspondence at a slow speed many small datas of physical address be temporary in the quick physical address of getting solid element midway soon, and afterwards by synchronously in the physical blocks of a plurality of block faces the executive routine instruction described small data is write in a parallel manner in the corresponding physical address at a slow speed.Based on this, write the required time of data can be shortened effectively, and then the usefulness of flash memory can be raised effectively.

It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.

Claims

1. flash memory system comprises:

One flash chip, have a plurality of physical blocks, each described physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of described quick physical address faster than writing the speed of data to described physical address at a slow speed; And

One flash controller is electrically connected to this flash chip, in order to carry out follow procedure at least:

From a host computer system, receive many 3rd data and will described the 3rd data temporary to described quick physical address, wherein said the 3rd data write the described physical address at a slow speed of address correspondence; And, when the quantity of temporary described the 3rd data to described quick physical address reaches a predetermined value, at least a portion of at least two the 3rd data in described the 3rd data is write in the described physical address at a slow speed of described the 3rd data correspondence in a synchronous mode, and wherein this predetermined value is not less than 2.

2. flash memory system according to claim 1, wherein this flash chip comprises a plurality of block faces, and each described physical blocks belongs to described block face one of them,

The described physical address at a slow speed of wherein said the 3rd data correspondence belongs to different block face among the described block face.

3. flash memory system according to claim 1, wherein from this host computer system, receive described the 3rd data and will the temporary extremely described quick physical address of described the 3rd data in program comprise:

(a) from this host computer system, receive data;

(b) judge whether corresponding described physical address at a slow speed of these data, and when the corresponding described physical address at a slow speed of these data, with these data be identified as described the 3rd data one of them and temporary to described quick physical address; And

(c) whether the quantity of judging temporary described the 3rd data to described quick physical address reaches this predetermined value, and if execution in step (a) and step (b) when the quantity of temporary described the 3rd data to described quick physical address does not reach this predetermined value.

4. flash memory system comprises:

One flash chip, have one first block face and one second block face, wherein this first block face and this second block face comprise a plurality of physical blocks respectively, each described physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of described quick physical address faster than writing the speed of data to described physical address at a slow speed;

A connector is in order to be electrically connected to a host computer system; And

One flash controller is electrically connected to this flash chip and this connector, in order to carry out following at least action:

The described physical blocks of this first block face and this second block face is divided into a plurality of solid elements and described solid element that will part is divided into a data field and a spare area, wherein each described solid element comprises one of them of described physical blocks of one of them and this second block face of the described physical blocks of this first block face;

From this host computer system, receive one first data that corresponding one first main frame writes instruction, one first physical blocks of one first solid element among the corresponding described solid element of this first data wherein, and this first physical blocks of this first solid element belongs to this first block face;

Choose among the described solid element of this spare area a solid element as to should first solid element one get solid element midway soon;

Judge that whether these first data are a small data and to the physical address at a slow speed of one first among the described physical address at a slow speed of this first physical blocks that should first solid element; And

When these first data are this small data and to should first at a slow speed during physical address, these first data are temporary in one of them of described quick physical address of this one first physical blocks of getting solid element midway soon,

Wherein this this first physical blocks of getting solid element midway soon belongs to this first block face.

5. flash memory system according to claim 4, wherein this flash controller is also in order to carry out following action:

From this host computer system, receive one second data that corresponding one second main frame writes instruction, one second physical blocks of this first solid element among the corresponding described solid element of this second data wherein, and this second physical blocks of this first solid element belongs to this second block face;

Judge that whether these second data are a small data and to the physical address at a slow speed of one second among the described physical address at a slow speed of this second physical blocks that should first solid element; And

When these second data are this small data and this second data to should second at a slow speed during physical address, these second data are temporary in one of them of described quick physical address of this one second physical blocks of getting solid element midway soon,

Wherein this this second physical blocks of getting solid element midway soon belongs to this second block face.

6. flash memory system according to claim 5, wherein this flash controller is also in order to carry out following action:

Get soon from this midway and to read these first data and this second data the solid element and these first data and this second data are write to this first physical address and this second at a slow speed in the physical address at a slow speed respectively,

Wherein to these first data of small part be written into this first physical address and this second at a slow speed in the physical address at a slow speed to these second data of small part in a synchronous mode.

7. flash memory system according to claim 6, wherein this flash controller is also in order to carry out following action:

When this first solid element has been write full data, this is got solid element midway soon carry out an erase operation and this is got solid element midway soon be associated in this spare area.

8. flash memory system according to claim 6, wherein this flash controller is also in order to use one to duplicate back and deposit instruction and get soon from this and read these first data and this second data solid element and with this method of synchronization these first data and this second data are write to this first physical address and this second at a slow speed in the physical address at a slow speed respectively midway.

9. flash controller, be used to write many data to flash chips, wherein this flash chip has a plurality of physical blocks, each described physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of described quick physical address faster than writing the speed of data to described physical address at a slow speed, this flash controller comprises:

One microprocessor unit;

One flash interface unit is electrically connected to this microprocessor unit, in order to be electrically connected to this flash chip; And

One Memory Management Unit is electrically connected to this microprocessor unit, and wherein this Memory Management Unit has a plurality of procedure codes and uses for this microprocessor unit and carry out follow procedure at least:

Receive many 3rd data and described the 3rd data are temporary to described quick physical address from a host computer system, the address that writes of wherein said the 3rd data corresponds to described physical address at a slow speed; And

When the quantity of temporary described the 3rd data to described quick physical address reaches a predetermined value, at least a portion of at least two the 3rd data in described the 3rd data is write in the described physical address at a slow speed of described the 3rd data correspondence in a synchronous mode, and wherein this predetermined value is not less than 2.

10. flash controller according to claim 9, wherein from this host computer system, receive described the 3rd data and will the temporary extremely described quick physical address of described the 3rd data in program comprise:

(a) from this host computer system, receive data;

(b) judge whether corresponding described physical address at a slow speed of these data, and when these data correspond in the described physical address at a slow speed, with these data be identified as described the 3rd data one of them and temporary to described quick physical address; And

11. flash controller, be used to write many data to flash chips, wherein this flash chip has one first block face and one second block face, this first block face and this second block face comprise a plurality of physical blocks respectively, each described physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of described quick physical address faster than writing the speed of data to described physical address at a slow speed, this flash controller comprises:

One microprocessor unit;

One flash interface unit is electrically connected to this microprocessor unit, in order to be electrically connected to this flash chip;

One host interface unit is electrically connected to this microprocessor unit, in order to be electrically connected to a host computer system; And

12. flash controller according to claim 11, wherein this microprocessor unit is also in order to carry out following at least action:

When these second data are this small data and to should second at a slow speed during physical address, these second data are temporary in one of them of described quick physical address of this one second physical blocks of getting solid element midway soon,

13. flash controller according to claim 12, wherein this microprocessor unit is also in order to carry out following action:

14. method for writing data, many data that are used for coming from a host computer system write to a flash chip, wherein this flash chip has a plurality of physical blocks, each described physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of described quick physical address faster than writing the speed of data to described physical address at a slow speed, this method for writing data comprises:

15. method for writing data according to claim 14, wherein from this host computer system, receive described the 3rd data and will the temporary extremely described quick physical address of described the 3rd data in step comprise:

(a) from this host computer system, receive data;

16. method for writing data, many data that are used for coming from a host computer system write to a flash chip, wherein this flash chip has one first block face and one second block face, this first block face and this second block face comprise a plurality of physical blocks respectively, each described physical blocks has a plurality of physical address, described physical address comprises a plurality of quick physical address and a plurality of physical address at a slow speed, and write data to the speed of described quick physical address faster than writing the speed of data to described physical address at a slow speed, this method for writing data comprises:

The described physical blocks of this first block face and this second block face is divided into a plurality of solid elements and described solid element partly is divided into a data field and a spare area,

Wherein each described solid element comprises one of them of described physical blocks of one of them and this second block face of the described physical blocks of this first block face;

17. method for writing data according to claim 16 also comprises:

18. method for writing data according to claim 17 also comprises:

19. method for writing data according to claim 18 also comprises:

20. method for writing data according to claim 18, wherein from this get soon midway read the solid element these first data and this second data and with these first data and this second data write to respectively this first at a slow speed physical address and this second at a slow speed the step in the physical address comprise:

Use one to duplicate back and deposit instruction and get soon from this and read these first data and this second data solid element and these first data and this second data are write to this first physical address and this second at a slow speed in the physical address at a slow speed respectively midway with this method of synchronization.