CN106325764A - Memory management method, memory control circuit unit and memory storage apparatus - Google Patents

Memory management method, memory control circuit unit and memory storage apparatus Download PDF

Info

Publication number
CN106325764A
CN106325764A CN201510396806.1A CN201510396806A CN106325764A CN 106325764 A CN106325764 A CN 106325764A CN 201510396806 A CN201510396806 A CN 201510396806A CN 106325764 A CN106325764 A CN 106325764A
Authority
CN
China
Prior art keywords
erasing unit
threshold value
physics
physics erasing
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510396806.1A
Other languages
Chinese (zh)
Other versions
CN106325764B (en
Inventor
颜鸿圣
陈国荣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phison Electronics Corp
Original Assignee
Phison Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phison Electronics Corp filed Critical Phison Electronics Corp
Priority to CN201510396806.1A priority Critical patent/CN106325764B/en
Publication of CN106325764A publication Critical patent/CN106325764A/en
Application granted granted Critical
Publication of CN106325764B publication Critical patent/CN106325764B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The invention provides a memory management method, a memory control circuit unit and a memory storage apparatus. The method comprises the steps of receiving a first writing instruction and writing data corresponding to the first writing instruction into first idle physical erasure units in physical erasure units; detecting the number of second idle physical erasure units which do not include the first idle physical erasure units; judging whether the number of the second idle physical erasure units is less than a threshold or not; and if the number of the second idle physical erasure units is less than the threshold, executing a first program, wherein the first program comprises the processes of transferring multiple pieces of effective data in the physical erasure units into at least one third idle physical erasure unit in the physical erasure units; and adjusting the threshold to a second threshold from a first threshold. According to the memory management method, the memory control circuit unit and the memory storage apparatus, the problem of instable data access speed due to execution of effective data transfer by a storage apparatus of a rewriteable nonvolatile memory can be improved.

Description

Storage management method, memorizer control circuit unit and memory storage apparatus
Technical field
The invention relates to a kind of memory management mechanism, and in particular to a kind of memorizer management Method, memorizer control circuit unit and memory storage apparatus.
Background technology
Digital camera, mobile phone and MP3 are the rapidest in growth over the years so that consumer is to storage The demand of media increases the most rapidly.Due to type nonvolatile (rewritable non-volatile Memory) there is the characteristics such as data non-volatile, power saving, volume is little, mechanical structure, read or write speed are fast, It is most suitable for portable type electronic product, such as notebook computer.Solid state hard disc is exactly a kind of with flash memory Memory storage apparatus as storage media.Therefore, flash memory industry becomes electronic industry in recent years In a quite popular ring.
In general, type nonvolatile storage device carries out one at set intervals The restructuring program of moving of secondary valid data, and be used for deciding whether to perform these valid data move restructuring journey Just determining well according to when type nonvolatile storage device dispatches from the factory of sequence.But, Due to bad during the execution efficiency fashion of the restructuring program of moving of valid data, often lead to duplicative non-easily The data access speed of the property lost memory storage apparatus is the most up and down.
In view of this, the most non-volatile with maintenance duplicative in the restructuring program of moving performing valid data Property memory storage apparatus data access speed between obtain balance the target endeavoured actually this area it One.
Summary of the invention
The present invention provides a kind of storage management method, memorizer control circuit unit and memorizer storage dress Put, type nonvolatile storage device can be improved and caused because performing moving of valid data The unstable problem of data access speed.
One example of the present invention embodiment provides the one for reproducible nonvolatile memorizer module to deposit Reservoir management method, wherein said reproducible nonvolatile memorizer module includes that the erasing of multiple physics is single Unit.Described storage management method includes receiving the first write instruction and by right for described first write instruction institute Answer data write to described physics erasing unit in first leave unused physics erasing unit；Detect described thing Reason erasing unit does not comprise the described first multiple the second of physics erasing unit physics erasing of leaving unused of leaving unused single The number of unit；Judge whether the described second number leaving unused physics erasing unit is less than threshold value；And if Described second number leaving unused physics erasing unit is less than described threshold value, performs the first program, Qi Zhongsuo First program of stating includes moving to described physics many valid data in described physics erasing unit wiping In unit at least one the 3rd is left unused in physics erasing unit；And by described threshold value from the first threshold value It is adjusted to the second threshold value.
In one example of the present invention embodiment, wherein described threshold value is adjusted from described first threshold value Include described in record storage valid data that at least one the 3rd leaves unused physics for the step of described second threshold value The number of erasing unit；And leave unused physics erasing singly according to described in storage valid data at least one the 3rd The number of unit determines described second threshold value.
In one example of the present invention embodiment, wherein described at least the one the 3rd of record storage valid data The step of the number of idle physics erasing unit includes: judge that stored in described physics erasing unit has Whether one number of the most allochthonous multiple first non-idle physics erasing unit of effect data meets present count Mesh；And if the described number of described first non-idle physics erasing unit meets described preset number, note Described at least the one the 3rd of address book stored valid data leave unused physics erasing unit number.
In one example of the present invention embodiment, wherein according to described in storage valid data at least one the 3rd The number of idle physics erasing unit determines that the step of described second threshold value includes according to corresponding to described The reference value of preset number with storage valid data described at least one the 3rd leave unused physics erasing unit number Mesh determines the difference between described first threshold value and described second threshold value, and wherein said reference value is Described preset number subtracts one.
In one example of the present invention embodiment, described storage management method also includes configuring multiple logic Unit；And hold with total logic of described logical block according to total physical capacity of described physics erasing unit Amount determines described preset number, and wherein said total physical capacity is more than described total logical capacity.
In one example of the present invention embodiment, wherein said first program also include according to the first rule from Described physics erasing unit selects described first non-idle physics erasing unit；And judging described the After the number of one non-idle physics erasing unit meets described preset number, according to Second Rule from described Physics erasing unit selects not comprise at least one second non-spare time of described first non-idle physics erasing unit Glove reason erasing unit, wherein said first regular and described Second Rule is different.
In one example of the present invention embodiment, described storage management method is additionally included in execution described the After one program, receive the second write instruction；Detect multiple 4th unused materials in described physics erasing unit The number of reason erasing unit；Judge that the described 4th leaves unused the number of physics erasing unit whether more than described the Two threshold values；And if the described 4th number leaving unused physics erasing unit is more than described second threshold value, Stop performing described first program and from described second threshold value, described threshold value being adjusted to the 3rd threshold Value.
In one example of the present invention embodiment, wherein said 3rd threshold value is equal to described first threshold value.
One example of the present invention embodiment provides for controlling the one of reproducible nonvolatile memorizer module Plant memorizer control circuit unit.Described memorizer control circuit unit includes that HPI, memorizer connect Mouth and memory management circuitry.HPI is electrically connected to host computer system.Memory interface in order to Being electrically connected to described reproducible nonvolatile memorizer module, wherein said duplicative is non-volatile Memory module includes that multiple physics wipes unit.Memory management circuitry is electrically connected to described main frame and connects Mouth and described memory interface.Described memory management circuitry is write in order to receive the first write instruction transmission Enter job sequence and the data corresponding to described first write instruction are write to the erasing of described physics single with instruction In unit first leave unused physics erasing unit.Described memory management circuitry is also in order to detect the wiping of described physics Leave unused physics erasing unit except unit does not comprise described first multiple the second of the physics erasing unit that leaves unused Number, and judge whether the described second number leaving unused physics erasing unit is less than threshold value.If it is described Second the leave unused number of physics erasing unit less than described threshold value, described memory management circuitry also in order to Perform the first program.Described first program includes removing many valid data in described physics erasing unit Move in described physics erasing unit at least one the 3rd leave unused in physics erasing unit；And by described door Threshold value is adjusted to the second threshold value from the first threshold value.
In one example of the present invention embodiment, wherein said memory management circuitry by described threshold value from Described first threshold value is adjusted to the operation of described second threshold value and includes the described of record storage valid data At least one the 3rd leave unused physics erasing unit number；And according to described in storage valid data at least one 3rd leave unused physics erasing unit number to determine described second threshold value.
In one example of the present invention embodiment, wherein said memory management circuitry record storage significant figure At least one the 3rd operation of number leaving unused physics erasing unit described according to includes judging that described physics is wiped The number of the most allochthonous multiple first non-idle physics erasing unit of valid data stored in unit Whether meet preset number；And if the described number of described first non-idle physics erasing unit meets institute Stating preset number, described at least the one the 3rd of record storage valid data is left unused the number of physics erasing unit.
In one example of the present invention embodiment, wherein said memory management circuitry is according to storage significant figure Described in according at least one the 3rd leave unused physics erasing unit number to determine the operation of described second threshold value Including not busy with described in storage valid data at least one the 3rd according to the reference value corresponding to described preset number The number of glove reason erasing unit determines the difference between described first threshold value and described second threshold value Value, wherein said reference value is that described preset number subtracts one.
In one example of the present invention embodiment, wherein said memory management circuitry is also multiple in order to configure Logical block, and wipe a total physical capacity of unit and the total of described logical block according to described physics Logical capacity determines described preset number, and wherein said total physical capacity is more than described total logical capacity.
In one example of the present invention embodiment, wherein said memory management circuitry performs described first journey The operation of sequence also includes selecting described first non-unused material according to the first rule from described physics erasing unit Reason erasing unit；And meet described presetting at the number judging described first non-idle physics erasing unit After number, select not comprise described first non-idle from described physics erasing unit according to Second Rule At least one second non-idle physics erasing unit of physics erasing unit, wherein said first regular and described Second Rule is different.
In one example of the present invention embodiment, after performing described first program, described memorizer pipe Reason circuit is also in order to receive the second write instruction.Described memory management circuitry is also in order to detect described physics Multiple 4th number leaving unused physics erasing unit in erasing unit, and judge that the described 4th leaves unused physics Whether the number of erasing unit is more than described second threshold value.If described 4th leaves unused physics erasing unit Number is more than described second threshold value, and described memory management circuitry also performs described first journey in order to stopping Sequence and described threshold value is adjusted to the 3rd threshold value from described second threshold value.
One example of the present invention embodiment provides a kind of memory storage apparatus, it include connecting interface unit, Reproducible nonvolatile memorizer module and memorizer control circuit unit.Connect interface unit in order to electricity Property is connected to host computer system.Reproducible nonvolatile memorizer module includes that multiple physics wipes unit. It is non-volatile with described duplicative that memorizer control circuit unit is electrically connected to described connection interface unit Memory module.Described memorizer control circuit unit is in order to receive the first write instruction and to send write and refer to Sequence is made the data corresponding to described first write instruction to be write to described physics erasing unit with instruction First leave unused physics erasing unit.Described memorizer control circuit unit is also in order to detect the wiping of described physics Leave unused physics erasing unit except unit does not comprise described first multiple the second of the physics erasing unit that leaves unused Number, and judge whether the described second number leaving unused physics erasing unit is less than threshold value.If it is described Second number leaving unused physics erasing unit is less than described threshold value, and described memorizer control circuit unit is also In order to perform the first program.Described first program includes many significant figures in described physics erasing unit Leave unused in physics erasing unit according at least the 3rd moved to described physics erasing unit；And by institute State threshold value and be adjusted to the second threshold value from the first threshold value.
In one example of the present invention embodiment, wherein said memorizer control circuit unit is by described threshold The operation that value is adjusted to described second threshold value from described first threshold value includes record storage valid data Described at least one the 3rd leave unused physics erasing unit number；And according to storage valid data described in extremely Few one the 3rd leaves unused the number of physics erasing unit to determine described second threshold value.
In one example of the present invention embodiment, wherein said memorizer control circuit unit record storage has The leave unused operation of number of physics erasing unit of described at least the one the 3rd of effect data includes judging described physics The most allochthonous multiple first non-idle physics erasing unit of valid data stored in erasing unit Whether number meets preset number；And if the number of described first non-idle physics erasing unit meets institute Stating preset number, described at least the one the 3rd of record storage valid data is left unused the number of physics erasing unit.
In one example of the present invention embodiment, wherein said memorizer control circuit unit has according to storage Effect data described at least one the 3rd leave unused physics erasing unit number to determine described second threshold value Operation includes according to the reference value and described in storage valid data at least one the corresponding to described preset number Three leave unused physics erasing unit number to determine between described first threshold value and described second threshold value Difference, wherein said reference value is that described preset number subtracts one.
In one example of the present invention embodiment, described memorizer control circuit unit is also multiple in order to configure Logical block, and according to described physics erasing total physical capacity of unit and always patrolling of described logical block Collecting capacity and determine described preset number, wherein said total physical capacity is more than described total logical capacity.
In one example of the present invention embodiment, wherein said memorizer control circuit unit performs described the The operation of one program also includes selecting the described first non-spare time according to the first rule from described physics erasing unit Glove reason erasing unit；And meet described at the number judging described first non-idle physics erasing unit After preset number, select not comprise described first non-from described physics erasing unit according to Second Rule At least one second non-idle physics erasing unit of idle physics erasing unit, wherein said first rule with Described Second Rule is different.
In one example of the present invention embodiment, after performing described first program, described memorizer control Circuit unit processed is also in order to receive the second write instruction, and detects in described physics erasing unit multiple the Four leave unused physics erasing unit number.Described memorizer control circuit unit is also in order to judge the described 4th Whether the number of idle physics erasing unit is more than described second threshold value.If the described 4th leave unused physics wipe Except the number of unit is more than described second threshold value, described memorizer control circuit unit is also held in order to stopping Row described first program and described threshold value is adjusted to the 3rd threshold value from described second threshold value.
Based on above-mentioned, storage management method provided by the present invention, memorizer control circuit unit with deposit Reservoir storage device, is dynamically adjusted for deciding whether that execution moves operation for valid data Threshold value.Whereby, by moving the control of operation for triggering valid data, duplicative can be made The data access speed of non-volatile memory module is relatively stable.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate Accompanying drawing is described in detail below.
Accompanying drawing explanation
Fig. 1 is host computer system shown by one example of the present invention embodiment and the showing of memory storage apparatus It is intended to；
Fig. 2 is that the computer shown by one example of the present invention embodiment, input/output device are deposited with memorizer The schematic diagram of storage device；
Fig. 3 is host computer system shown by one example of the present invention embodiment and the showing of memory storage apparatus It is intended to；
Fig. 4 is the schematic block diagram illustrating the memory storage apparatus shown in Fig. 1；
Fig. 5 is the summary square of the memorizer control circuit unit shown by one example of the present invention embodiment Figure；
Fig. 6 is the management type nonvolatile mould shown by one example of the present invention embodiment The schematic diagram of block；
Fig. 7 A and Fig. 7 B is the schematic diagram of the first program shown by one example of the present invention embodiment；
Fig. 8 is the flow chart of the storage management method shown by one example of the present invention embodiment.
Description of reference numerals:
10: memory storage apparatus；
11: host computer system；
12: computer；
122: microprocessor；
124: random access memory；
126: system bus；
128: data transmission interface；
13: input/output (I/O) device；
21: mouse；
22: keyboard；
23: display；
24: printer；
25: Portable disk；
26: memory card；
27: solid state hard disc；
31: digital camera；
32:SD card；
33:MMC card；
34: memory stick；
35:CF card；
36: embedded storage device；
402: connect interface unit；
404: memorizer control circuit unit；
406: reproducible nonvolatile memorizer module；
502: memory management circuitry；
504: HPI；
506: memory interface；
508: error checking and correcting circuit；
510: buffer storage；
512: electric power management circuit；
600 (0)～600 (R): physics erasing unit；
610 (0)～610 (D): logical block；
602: memory block；
606: system area；
S801～S806: step.
Detailed description of the invention
It is said that in general, memory storage apparatus (also referred to as, storage system) includes that duplicative is non-volatile Property memory module (rewritable non-volatile memory module) with controller (also referred to as, control electricity Road).Being commonly stored device storage device is to be used together with host computer system, so that data can be write by host computer system Enter to memory storage apparatus or from memory storage apparatus, read data.
Fig. 1 is host computer system shown by one example of the present invention embodiment and the showing of memory storage apparatus It is intended to.Fig. 2 is the computer shown by one example of the present invention embodiment, input/output device and memorizer The schematic diagram of storage device.
Refer to Fig. 1, host computer system 11 generally comprises computer 12 and input/output (input/output, letter Claim: I/O) device 13.Computer 12 includes microprocessor 122, random access memory (random access Memory, is called for short: RAM) 124, system bus 126 and data transmission interface 128.Input/output fills Put 13 and include mouse 21 such as Fig. 2, keyboard 22, display 23 and printer 24.Have to be understood that Being, the unrestricted input/output device of device 13 shown in Fig. 2, input/output device 13 can also include it His device.
In an exemplary embodiment, memory storage apparatus 10 is by data transmission interface 128 and main frame Other elements of system 11 are electrically connected with.By microprocessor 122, random access memory 124 with defeated Enter/running of output device 13 can write data into memory storage apparatus 10 or from memorizer storage dress Put reading data in 10.Such as, memory storage apparatus 10 can be Portable disk 25 as shown in Figure 2, (Solid State Drive is called for short: SSD) duplicative of 27 grades is non-volatile for memory card 26 or solid state hard disc Property memory storage apparatus.
Fig. 3 is host computer system shown by one example of the present invention embodiment and the showing of memory storage apparatus It is intended to.
It is said that in general, host computer system 11 is for coordinating to store number with memory storage apparatus 10 substantially According to any system.Although in this exemplary embodiment, host computer system 11 is to explain with computer system, But, in another exemplary embodiment, host computer system 11 can be digital camera, video camera, communicator, The system such as audio player or video player.Such as, it is digital camera (video camera) 31 in host computer system Time, type nonvolatile storage device is then by its SD card 32 used, mmc card 33, memory stick (memory stick) 34, CF card 35 or embedded storage device 36 (as shown in Figure 3). Embedded storage device 36 includes that (Embedded MMC is called for short: eMMC) embedded multi-media card. It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host computer system.
Fig. 4 is the schematic block diagram illustrating the memory storage apparatus shown in Fig. 1.
Refer to Fig. 4, memory storage apparatus 10 includes connecting interface unit 402, memorizer controls electricity Road unit 404 and reproducible nonvolatile memorizer module 406.
In this exemplary embodiment, connect interface unit 402 and be compatible with Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, is called for short: SATA) standard.However, it is necessary to be appreciated that, The invention is not restricted to this, connecting interface unit 402 can also be to meet parallel advanced technology adnexa (Parallel Advanced Technology Attachment, is called for short: PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, is called for short: IEEE) 1394 standards, at a high speed week (Peripheral Component Interconnect Express is called for short: PCI limit component connecting interface Express) (Universal Serial Bus is called for short: USB) standard, safe number for standard, USB (universal serial bus) Word (Secure Digital, be called for short: SD) interface standard, a ultrahigh speed generation (Ultra High Speed-I, be called for short: UHS-I) interface standard, ultrahigh speed secondary (Ultra High Speed-II, is called for short: UHS-II) interface standard, Memory stick (Memory Stick, be called for short: MS) interface standard, multimedia storage card (Multi Media Card, Be called for short: MMC) interface standard, enter formula multimedia storage card (Embedded Multimedia Card, EMMC) (Universal Flash Storage is called for short: UFS) interface for interface standard, general flash memory (Compact Flash, is called for short: CF) interface standard, integrated form drive electrical interface for standard, compact flash (Integrated Device Electronics, is called for short: IDE) standard or other standards being suitable for.Connect interface Unit 402 can be encapsulated in a chip with memorizer control circuit unit 404, or connects interface list Unit 402 is to be laid in outside a chip comprising memorizer control circuit unit 404.
Memorizer control circuit unit 404 is in order to perform with hardware pattern or multiple the patrolling of software pattern implementation Volume lock or control instruction and according to the instruction of host computer system 11 at type nonvolatile mould Block 406 carries out the write of data, reads and operate with erasing etc..
Reproducible nonvolatile memorizer module 406 is electrically connected to memorizer control circuit unit 404 and the data that write in order to host system 11.Reproducible nonvolatile memorizer module 406 can be that (Single Level Cell is called for short: SLC) NAND type flash memory single-order memory element Module (that is, the flash memory module of 1 Bit data can be stored in one memory element), multistage storage (Multi Level Cell is called for short: MLC) NAND type flash memory module (that is, one storage unit Unit can store the flash memory module of 2 Bit datas), Complex Order memory element (Triple Level Cell, is called for short: TLC) NAND type flash memory module (that is, can store 3 in one memory element The flash memory module of Bit data), other flash memory module or other there is depositing of identical characteristics Memory modules.
Fig. 5 is the summary square of the memorizer control circuit unit shown by one example of the present invention embodiment Figure.
Refer to Fig. 5, memorizer control circuit unit 404 includes that memory management circuitry 502, main frame connect Mouth 504, memory interface 506 and error checking and correcting circuit 508.
Memory management circuitry 502 is in order to control the overall operation of memorizer control circuit unit 404.Tool For body, memory management circuitry 502 has multiple control instruction, and at memory storage apparatus 10 During running, these a little control instructions can be performed to carry out the write of data, read and operate with erasing etc..With During the operation of lower explanation memory management circuitry 502, it is equal to memorizer control circuit unit 404 is described Operation.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to come in fact with software pattern Make.Such as, memory management circuitry 502 has microprocessor unit (not shown) with read only memory (not Illustrate), and these a little control instructions are to be programmed so far in read only memory.When memory storage apparatus 10 During running, these a little control instructions can by microprocessor unit perform to carry out data write, read with The runnings such as erasing.
In another exemplary embodiment, the control instruction of memory management circuitry 502 can also program pattern Formula is stored in the specific region of reproducible nonvolatile memorizer module 406 (such as, in memory module It is exclusively used in the system area of storage system data) in.Additionally, memory management circuitry 502 has microprocessor Unit (not shown), read only memory (not shown) and random access memory (not shown).Particularly, this Read only memory has boot code (boot code), and when memorizer control circuit unit 404 is enabled Time, microprocessor unit can first carry out this boot code will be stored in type nonvolatile mould Control instruction in block 406 is loaded in the random access memory of memory management circuitry 502.Afterwards, Microprocessor unit can operate these a little control instructions to carry out the write of data, to read and operate with erasing etc..
Additionally, in another exemplary embodiment, the control instruction of memory management circuitry 502 can also one Hardware pattern carrys out implementation.Such as, memory management circuitry 502 includes that microcontroller, physical location manage Circuit, memorizer write circuit, memory reading circuitry, memorizer erasing circuit and data processing circuit. Physical location management circuit, memorizer write circuit, memory reading circuitry, memorizer erasing circuit with Data processing circuit is electrically connected to microcontroller.Wherein, physical location management circuit can in order to manage The physics erasing unit of manifolding formula non-volatile memory module 406；Memorizer write circuit is in order to can Manifolding formula non-volatile memory module 406 assigns write instruction sequence to write data into duplicative In non-volatile memory module 406；Memory reading circuitry is in order to duplicative non-volatile memories Device module 406 assigns reading job sequence to read from reproducible nonvolatile memorizer module 406 Data；Memorizer erasing circuit refers in order to reproducible nonvolatile memorizer module 406 is assigned erasing Make sequence data to be wiped from reproducible nonvolatile memorizer module 406；And data process electricity Road is intended to write to the data of reproducible nonvolatile memorizer module 406 and from making carbon copies in order to process The data read in formula non-volatile memory module 406.Write instruction sequence, read job sequence and Erasing instruction sequence can distinctly include one or more procedure code or order code and in order to indicate duplicative non- Volatile 406 performs corresponding write, read and the operation such as erasing.
HPI 504 is electrically connected to memory management circuitry 502 and in order to receive and to identify master Instruction that machine system 11 is transmitted and data.It is to say, the instruction that transmitted of host computer system 11 and number According to being sent to memory management circuitry 502 by HPI 504.In this exemplary embodiment, HPI 504 is compatible with SATA standard.However, it is necessary to be appreciated that and the invention is not restricted to this, HPI 504 can also be compatible with PATA standard, IEEE 1394 standard, PCI Express mark Standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, EMMC standard, UFS standard, CF standard, IDE standard or other data transmission standards being suitable for.
Memory interface 506 is electrically connected to memory management circuitry 502 and can make carbon copies in order to access Formula non-volatile memory module 406.It is to say, be intended to write to type nonvolatile The data of module 406 can be converted to reproducible nonvolatile memorizer module by memory interface 506 406 receptible forms.Specifically, if memory management circuitry 502 duplicative to be accessed is non- Volatile 406, memory interface 506 can transmit the job sequence of correspondence.Such as, this A little job sequences can include that the write instruction sequence of instruction write data, instruction read the reading instruction of data Sequence, instruction wipe the erasing instruction sequence of data and in order to indicate various storage operation (such as, Change read voltage level or perform garbage reclamation program etc.) corresponding job sequence, differ at this One repeats.These job sequences are e.g. produced by memory management circuitry 502 and are connect by memorizer Mouth 506 is sent to reproducible nonvolatile memorizer module 406.These job sequences can include one or Multiple signals, or the data in bus.These signals or data can include order code or procedure code. Such as, in reading job sequence, the information such as the identification code of reading, storage address can be included.
Error checking and correcting circuit 508 are electrically connected to memory management circuitry 502 and in order to hold Row error checking and correction program are to guarantee the correctness of data.Specifically, memory management circuitry is worked as 502 when receiving write instruction from host computer system 11, and error checking can be corresponding with correcting circuit 508 The data of this write instruction produce corresponding error correcting code, and (error correcting code is called for short: ECC) And/or error checking code (error detecting code, is called for short: EDC), and memory management circuitry 502 Can the data of this write instruction corresponding be write with corresponding error correcting code and/or error checking code extremely can In manifolding formula non-volatile memory module 406.Afterwards, when memory management circuitry 502 is from making carbon copies Can read, when formula non-volatile memory module 406 reads data, the error correction that these data are corresponding simultaneously Code and/or error checking code, and error checking and correcting circuit 508 can according to this error correcting code and/ Or the data that error checking code is to being read perform error checking and correction program.
In an exemplary embodiment, memorizer control circuit unit 404 also include buffer storage 510 with Electric power management circuit 512.Buffer storage 510 be electrically connected to memory management circuitry 502 and It is configured to temporarily store and comes from data and the instruction of host computer system 11 or come from duplicative non-volatile memories The data of device module 406.Electric power management circuit 512 is electrically connected to memory management circuitry 502 also And in order to control the power supply of memory storage apparatus 10.
Fig. 6 is the management type nonvolatile mould shown by one example of the present invention embodiment The schematic diagram of block.It will be appreciated that be described herein reproducible nonvolatile memorizer module 406 When physics wipes the running of unit, carry out operating physical with the word such as " selection ", " packet ", " division ", " association " Erasing unit is concept in logic.It is to say, the physics of reproducible nonvolatile memorizer module The physical location of erasing unit is not changed, but in logic to reproducible nonvolatile memorizer module Physics erasing unit operate.
It is single that the memory element of reproducible nonvolatile memorizer module 406 can constitute the programming of multiple physics Unit, and these a little physics programming units can constitute multiple physics erasing unit 600 (0)～600 (R).Concrete next Saying, the memory element on same word-line can form one or more physics programming unit.If each is deposited Storage unit can store the bit of more than 2, then the physics programming unit on same word-line at least can quilt It is categorized as lower physics programming unit and upper physics programming unit.Such as, in MLC NAND flash memory In reservoir, (Least Significant Bit, is called for short the minimum effective bit of a memory element: LSB) be to belong to In lower physics programming unit, and the highest significant bit (Most Significant Bit, the letter of a memory element Claim: MSB) be belonging to physics programming unit.In general, the writing speed meeting of lower physics programming unit More than the writing speed of upper physics programming unit, or the reliability of lower physics programming unit is above physics The reliability of programming unit.
In this exemplary embodiment, physics programming unit is the minimum unit of programming.That is, physics programming is single Unit is the minimum unit of write data.Such as, physics programming unit is physical page or physics fan (sector).If physics programming unit is physical page, then each physics programming unit generally includes data Bit area and redundancy ratio special zone.Data bit district comprises multiple physics fan, in order to store user data, And redundancy ratio special zone is in order to memory system data (such as, error correcting code).In this exemplary embodiment, Data bit district comprises 32 physics fan, and the size of a physics fan be 512 bytes (byte, is called for short: B).But, in other exemplary embodiment, data bit district also can comprise 8,16 or number More or less of physics is fanned, and the size of each physics fan can also be greater or lesser.Another Aspect, physics erasing unit is the least unit of erasing.That is, each physics erasing unit contains minimum The memory element being wiped free of in the lump of number.Such as, physics erasing unit is physical blocks.
Refer to Fig. 6, memory management circuitry 502 can be by reproducible nonvolatile memorizer module 406 Physics erasing unit 600 (0)～600 (R) be logically divided into multiple region, for example, memory block 602 with System area 606.
The physics erasing unit of memory block 602 is to store the data from host computer system 11.Memory block Valid data and invalid data can be stored in 602.Such as, a valid data are deleted when host computer system Time, deleted data may also be stored in memory block 602, but can be marked as invalid data. In following exemplary embodiment, the physics erasing unit not storing valid data is the most idle (spare) Physics erasing unit.Such as, it is wiped free of later physics erasing unit and will become idle physics erasing list Unit.Additionally, in following exemplary embodiment, have the physics erasing unit of storage valid data also referred to as Non-idle (non-spare) physics erasing unit.
In an exemplary embodiment, if memory block 602 or system area 606 have physics erasing unit to damage Time, the physics erasing unit in memory block 602 may also be used for replacing the physics erasing unit damaged.If If memory block 602 does not has can physics erasing unit to replace damage physics wipe unit time, then Whole memory storage apparatus 10 may be declared as write protection (write by memory management circuitry 502 Protect) state, and data cannot be write again.
The physics erasing unit of system area 606 is to record system data, and wherein this system data includes Manufacturer and model, physics erasing unit number, each physics of memory chip about memory chip The physics programming unit number etc. of erasing unit.
In an exemplary embodiment, the quantity meeting of the physics erasing unit of memory block 602 and system area 606 Different according to different memorizer specifications.Further, it is necessary to be appreciated that, at memorizer storage dress Putting in the running of 10, physics erasing unit pass is coupled to the packet relation of memory block 602 and system area 606 can Can be able to dynamically change.Such as, when the physics erasing unit in system area 606 damages by memory block 602 Physics erasing unit when replacing, then originally physics erasing unit in memory block 602 can be associated to be System district 606.
In this exemplary embodiment, memory management circuitry 502 can configuration logic unit 610 (0)～610 (D) To map to physics erasing unit 600 (0)～600 (A) in memory block 602.Such as, implement at this example In example, host computer system 11 is to access the data in memory block 602 by logical address, therefore, each Individual logical block 610 (0)～610 (D) refers to a logical address.Additionally, in an exemplary embodiment, often One logical block 610 (0)～610 (D) may also mean that a logic fan, programming in logic unit, one Individual logic is wiped unit or is made up of multiple continuous print logical addresses.
In this exemplary embodiment, each logical block 610 (0)～610 (D) is to map to one or more thing Reason unit.In this exemplary embodiment, a physical location refers to a physics erasing unit.But, In another exemplary embodiment, physical location can also be a physical address, physics fan, One physics programming unit or be made up of multiple continuous print physical address, the present invention is not any limitation as. Mapping relations between logical block and physical location can be recorded at least one by memory management circuitry 502 Logical-physical mapping table.When host computer system 11 is intended to read data or write number from memory storage apparatus 10 According to during to memory storage apparatus 10, memory management circuitry 502 can be according to this logical-physical mapping table Perform the data access for memory storage apparatus 10.
In general, receiving after the write instruction of host computer system 11, in memory block 602 Idle physics erasing unit can be used to store the data corresponding to this write instruction.If in memory block 602 Idle physics erasing unit not enough, memory management circuitry 502 can indicate that duplicative is non-volatile to be deposited Memory modules 406 performs that data are whole and program.In an exemplary embodiment, these data are whole and program also It is referred to as garbage reclamation (garbage collection) program.
In and program whole in data, the part valid data being dispersed in memory block 602 can be collected and collect In move some idle physics erasing unit in, with release storage invalid data physics erasing unit. If the data that a certain original marking is valid data are moved out from some non-idle physics erasing unit Go, then these data can be marked as invalid data at this in non-idle physics erasing unit.If some is non- All valid data that idle physics erasing unit is stored are moved away (that is, this non-idle physics the most All data that erasing unit is stored all have been labeled as invalid data), then this non-idle physics erasing unit A new idle physics erasing unit is become by being wiped free of.On the other hand, whole in data and journey The idle physics erasing unit being used to store collected valid data in sequence can become a new non-spare time Glove reason erasing unit.
In this exemplary embodiment, memory management circuitry 502 can receive to be write from the one of host computer system 11 Enter instruction (the hereinafter also referred to first write instruction) and select from memory block 602 according to the first write instruction One physics erasing unit.In this exemplary embodiment, selected physics erasing unit is idle physics Erasing unit (hereinafter also referred to first leave unused physics erasing unit).But, in another exemplary embodiment, Selected physics erasing unit is also likely to be the idle physics erasing of the most stored write data having other Unit.
Memory management circuitry 502 can send a write instruction sequence to type nonvolatile Module 406 would correspond to data (the hereinafter also referred to first data) write of this first write instruction with instruction So far first leave unused in physics erasing unit.Such as, these first data are to need to deposit indicated by this write instruction The data of storage.After physics erasing unit is left unused in selection first, memory management circuitry 502 can detect Memory block 602 does not comprise the first idle physics leaving unused physics erasing unit and wipes unit (hereinafter also referred to Second leave unused physics erasing unit) number.Such as, this second leave unused physics erasing unit number for First leave unused physics erasing unit be chosen after remaining idle physics erasing unit in memory block 602 Sum.
Memory management circuitry 502 can judge whether the second number leaving unused physics erasing unit is less than one Threshold value.Such as, it is judged that whether the second number leaving unused physics erasing unit is less than the operation of this threshold value is React on above-mentioned memory management circuitry 502 receive the first write instruction or select first leave unused physics erasing Unit and perform.This threshold value can be as judging that in memory block 602, remaining idle physics erasing unit is No enough foundations.Such as, in this exemplary embodiment, this threshold value can be " 6 ".But, In another exemplary embodiment, this threshold value can also be greater or lesser positive integer.If the second unused material The number of reason erasing unit, less than this threshold value, represents that in memory block 602, the erasing of remaining idle physics is single Unit will be not enough, therefore memory management circuitry 502 can perform that data are whole and program (hereinafter also referred to the One program) discharge the physics erasing unit having invalid data.But, if second leaves unused physics erasing singly The number of unit, not less than this threshold value, represents that in memory block 602, remaining idle physics erasing unit is still Enough, thus memory management circuitry 502 can select not perform this first program.
If determining first program that performs, memory management circuitry 502 can select another from memory block 602 Individual idle physics erasing unit stores valid data collected in the first program.Determining execution first After program, corresponding to memory management circuitry 502, the data from host computer system 11 are write extremely First leaves unused a physics programming unit in physics erasing unit, and many pen data (that is, valid data) can quilt " N number of " continuous or discrete physics programming unit from memory block 602 is moved for storing In the idle physics erasing unit of valid data collected in the first program, until the first program is stopped Till.This " N number of " continuous or discrete physics programming unit can be contained within one or more physics In erasing unit.Such as, if " N " is " 2 ", then in the first program, corresponding to by above-mentioned first Data write is left unused some the physics programming unit in physics erasing unit to first, and " 2 " are effective Data can be moved in " 2 " continuous or discrete physics programming unit from memory block 602 The idle physics being used for storing collected valid data is wiped in unit.
Before the first program is stopped, if receiving more write instruction, then more from main frame The data of system 11 can be stored to above-mentioned first leave unused physics erasing unit in and more from storage The valid data in district 602 can be collected and be concentrated to for storing the idle of collected valid data In physics erasing unit.If above-mentioned first leave unused physics erasing unit or will be fully written, the most more Many idle physics erasing unit can be selected to store the data from host computer system 11.Following In exemplary embodiment, it is also possible to store the data from host computer system 11 by the first program is selected to Each idle physics erasing unit be referred to as first leave unused physics erasing unit.
Before the first program is stopped, if be selected at present to store the one of collected valid data or Multiple idle physics erasing unit has been fully written and maybe will be fully written, the physics that the most more leaves unused erasing unit Can also be chosen and be used to store collected valid data.In following exemplary embodiment, Can also be by the idle physics erasing list being selected to store collected valid data anticipated in the first program Unit be referred to as the 3rd leave unused physics erasing unit.
In the first program, memory management circuitry 502 can select multiple unused material from memory block 602 Reason erasing unit (that is, the 3rd leave unused physics erasing unit) and indicate type nonvolatile mould Block 406 the multiple non-idle physics in memory block 602 is wiped the valid data that stored of unit move to This little 3rd leave unused physics erasing unit in.Such as, in an exemplary embodiment, the first program is default Collected valid data are write full " N number of " idle physics erasing unit, and (that is, the 3rd leaves unused physics erasing Unit) " N+1 " is new at least discharging the thing that can be used to store the data from host computer system 11 Reason erasing unit.Wherein, it is used for storing each idle physics erasing unit of collected valid data Can become non-idle physics erasing unit, and that the valid data stored have been moved away the most is every One non-idle physics erasing unit can become idle physics erasing unit.
In the first program, above-mentioned being used for also can be judged whether to perform first by memory management circuitry 502 The threshold value of program is adjusted to another value from current value (the hereinafter also referred to first threshold value) and (is also referred to as below It is the second threshold value).In this exemplary embodiment, the second threshold value can be more than the first threshold value.And certainly Surely, after stopping the first program, this threshold value then can be adjusted by memory management circuitry 502 from the second threshold value Whole for another value (the hereinafter also referred to the 3rd threshold value).In an exemplary embodiment, the first threshold value, Two threshold values and the 3rd threshold value are the most distinctly preset values, and it will not be along with the execution shape of the first program Condition and change.But, in this exemplary embodiment, the first threshold value is a preset value, the second threshold Value immediately can determine along with the practice condition of the first program, and the 3rd threshold value is equal to the first threshold Value.
In this exemplary embodiment, leave unused physics erasing unit above-mentioned valid data being moved to the 3rd During, memory management circuitry 502 can judge that stored valid data have been moved away many most Whether the number of individual non-idle physics erasing unit (the hereinafter also referred to first non-idle physics erasing unit) accords with Unification preset number.Such as, this preset number is " N+1 ".Wherein, by valid data intactly After some first non-idle physics erasing unit is moved out, the erasing of this first non-idle physics is single Unit becomes an idle physics erasing unit being released.Therefore, in an exemplary embodiment, it is judged that Whether the number of the first non-idle physics erasing unit meets the operation of preset number also can be considered and judges the Whether the number of the idle physics erasing unit being released in one program reaches the operation of preset number.
If it is determined that the number of the first non-idle physics erasing unit meets preset number, memory management circuitry 502 at least one physics erasing lists that storage instantly can be had allochthonous valid data in the first program The number of unit is recorded.In other words, in some exemplary embodiment, the 3rd leave unused physics erasing unit Refer to preset in the first program and can wipe unit for storing the physics of collected valid data, and work as Lower storage has the number of at least one physics erasing unit of allochthonous valid data in the first program then Refer to that this little 3rd leaves unused and currently stored the physics of collected valid data in physics erasing unit The sum of erasing unit.Memory management circuitry 502 can (storage i.e., instantly has according to the number recorded The number of at least one physics erasing unit of allochthonous valid data in the first program) determine the Two threshold values.
Fig. 7 A and Fig. 7 B is the schematic diagram of the first program shown by one example of the present invention embodiment.
Refer to Fig. 7 A, in the first program, make a reservation for be intended to collect to write full " N number of " unused material The valid data of reason erasing unit (that is, the 3rd leave unused physics erasing unit), just can discharge " N+1 " Idle physics erasing unit.
Refer to Fig. 7 B, in this exemplary embodiment, if only collecting write in the first program or writing full The valid data of " M " physics erasing unit have discharged " N+1 " physics erasing unit, Then " M " this value will be recorded.M can be less than or equal to the positive integer of N.
In this exemplary embodiment, memory management circuitry 502 can be according to corresponding to above-mentioned preset number One reference value and the number (such as, " M ") recorded determine the first threshold value and the second threshold value it Between difference.Thereafter, memory management circuitry 502 can determine the second threshold value according to this difference.Example As, it is assumed that preset number is " N+1 ", then the reference value corresponding to preset number can be set to " N " (that is, preset number subtracts one), and reference value " N " can be deducted " M " by memory management circuitry 502 And obtain the difference " E " (that is, E=N-M) between the first threshold value and the second threshold value.Thereafter, deposit Current the first threshold value " T1 " can be obtained the by reservoir management circuit 502 plus this difference " E " Two threshold values " T2 " (that is, T2=T1+E).
It is noted that it is observed that the second threshold value and first from above-mentioned exemplary embodiment Gap between threshold value can with the distribution in memory block 602 of the valid data to be collected in the first program or The execution efficiency of the first program is relevant.Such as, if the valid data to be collected in the first program are in storage Distribution in district 602 is relatively concentrated (as long as i.e., wiping collection significant figure unit from the non-idle physics of minority According to just discharging the new idle physics erasing unit meeting preset number), then " M " recorded May be less, the gap between the second threshold value " T2 " and the first threshold value " T1 " may be relatively simultaneously Greatly；Otherwise, if the distribution that the valid data to be collected in the first program are in memory block 602 is relatively decentralized (that is, it needs to collect from many non-idle physics erasing unit valid data just can discharge meet pre- If the new idle physics erasing unit of number), then " M " recorded may (such as, M can relatively greatly Can level off to N), the gap between the second threshold value " T2 " and the first threshold value " T1 " may simultaneously Less.
Additionally, should be specified, in above-mentioned exemplary embodiment, it is used for calculating the second threshold value " T2 " Concept can be reduced to: the second threshold value " T2 "=first threshold value " T1 "+reference value " N "- " M " recorded.But, in another exemplary embodiment, based on the demand in practice, this concept Any logical operations of can also arranging in pairs or groups is implemented.Or, in another exemplary embodiment, it is also possible to by The ginseng such as one threshold value " T1 ", reference value " N " (or preset number " N+1 ") and " M " that recorded Number input to a preset algorithm or obtains the second threshold value " T2 " by tabling look-up.
In an exemplary embodiment, memory management circuitry 502 also can be according to all of in memory block 602 One total capacity (hereinafter also referred to total physical capacity) and all available the patrolling configured of physics erasing unit One total capacity (hereinafter also referred to total logical capacity) of volume unit determines (or the described reference of described preset number Value).Wherein, total physical capacity can be more than total logical capacity.Such as, total logical capacity can be equal to main frame system Can be used to set by system 11 or memory management circuitry 502 stores a maximum appearance of user data Amount.
Such as, in an exemplary embodiment of Fig. 8, it is assumed that corresponding to type nonvolatile The all available logical block 610 (0)～610 (D) of module 406 or can be used to storage effectively Data and memory block 602 include physics erasing unit 600 (0)～600 (A), the most described preset number " N+1 " (or described reference value " N ") can according to total logical capacity " L " of logical block 610 (0)～610 (D) with Total physical capacity " P " of physics erasing unit 600 (0)～600 (A) determines.Such as, can basis: total Logical capacity " L "/(total physical capacity " P "-total logical capacity " L ") obtains reference value " N ". In this exemplary embodiment, if the reference value that primary Calculation goes out " N " is not a positive integer, then can also By: the result of total logical capacity " L "/(total physical capacity " P "-total logical capacity " L ") takes decimal Point round up, take the unconditional carry of arithmetic point, take Gauss or take a certain immediate meaningful (such as Be the power of 2) positive integer etc. obtain reference value " N ".In another exemplary embodiment, based on reality Demand in business, the computing of above-mentioned acquisition reference value " N " any logical operations of can also arranging in pairs or groups is implemented. Additionally, in another exemplary embodiment, it is also possible to by total logical capacity " L " and total physical capacity " P " Input is to a preset algorithm or obtains reference value " N " (or preset number " N+1 ") by tabling look-up.
In another exemplary embodiment of Fig. 8, total physical capacity " P " can also comprise in system area 606 At least one physics erasing unit capacity.In an exemplary embodiment, above-mentioned total physical capacity can also It is to take with the sum of the multiple physical locations (such as, physics erasing unit) for calculating this total physical capacity Generation, and above-mentioned total logical capacity can also be with the multiple logical blocks for calculating this total logical capacity Sum replace.In an exemplary embodiment, " N " calculated e.g. " 32 ", but If the specification of memory storage apparatus 10 is different, then " N " is also likely to be greater or lesser positive integer.
After starting to perform the first program, if memory management circuitry 502 receives again from main frame system Another write instruction (the hereinafter also referred to second write instruction) of system 11, then memory management circuitry 502 meeting (the hereinafter also referred to the 4th leaves unused physics erasing singly to idle physics erasing unit current in detection memory block 602 Unit) number.Such as, this little 4th number leaving unused physics erasing unit refers in memory block 602 current All idle physics erasing unit sum, and this little 4th leave unused physics erasing unit may wrap It is contained in the idle physics erasing unit being released in the first program.Memory management circuitry 502 can be sentenced Whether this little 4th number leaving unused physics erasing unit disconnected is more than a threshold value.
It is noted that in this exemplary embodiment, threshold value is adjusted to second by the first threshold value Threshold value, therefore memory management circuitry 502 actually judges in memory block 602 that the 4th leaves unused physics wiping Except whether the number of unit is more than this second threshold value.If the 4th leave unused physics erasing unit number little In this second threshold value, memory management circuitry 502 can continuously carry out the first program.About how to perform First program is in preceding description, therefore does not repeats at this.If additionally, the 4th leave unused physics erasing unit Number more than this second threshold value, then memory management circuitry 502 can stop performing the first program.
In this exemplary embodiment, if determining to stop performing the first program, then memory management circuitry 502 Also can will be used for judging whether that the threshold value performing the first program adjusts back default the from this second threshold value One threshold value.Whereby, after stopping first program that performs, if needing again corresponding to from host computer system Some write instruction of 11 and judge that remaining idle physics erasing unit is enough, then memorizer pipe Reason circuit 502 can reuse this first threshold value and judge whether to perform next first program.If certainly Surely perform next first program, then memory management circuitry 502 can holding again according to this first program Row situation determines the second corresponding threshold value.Thereafter, memory management circuitry 502 can be according to being determined The second fixed threshold value judges whether the first program stopped performed by execution and performs corresponding to stopping First program and again adjust threshold value and (such as, threshold value adjusted back first from the second threshold value again Threshold value or other values etc.).About how to utilize the first threshold value to judge whether to perform the first program, as What determines the second corresponding threshold value and how to utilize the second threshold value to decide whether to stop the first journey The operation such as sequence illustrates the most in above-mentioned exemplary embodiment, does not repeats at this.
In other words, relative to being generally used to judge whether to start to perform, data are whole and program and be intended to judge Whether stopping that data are whole and program is all to use identical threshold value, the present invention can be according to data each time The practice condition of whole and program carrys out corresponding setting, and in order to stop, data are whole and the threshold value of program.Such as, exist Determine to start to perform that data are whole and after program, with can and the practice condition of program whole according to current data Would correspond to stop whole and program the threshold value of these data tune up, thus extend that these data are whole and the holding of program OK.
In an exemplary embodiment, if detecting, the number of the first non-idle physics erasing unit meets default Number, then be used for selecting to be intended in the first program the rule of the non-idle physics erasing unit of extracted valid data May change.Such as, in an exemplary embodiment, the first non-idle physics erasing unit detected Number meet preset number before, memory management circuitry 502 can according to a preset rules (the most also It is referred to as the first rule) from memory block 602, select the first program is intended to the non-idle physics of extracted valid data Erasing unit (that is, the first non-idle physics erasing unit).Such as, this first rule can include that selection is deposited The valid data of storage less than the invalid data of a preset value or storage more than this preset value etc. for valid data Move efficiency the most non-idle physics erasing unit.And detecting that the first non-idle physics erasing is single After the number of unit meets preset number, memory management circuitry 502 is then to preset rule according to another Then (hereinafter also referred to Second Rule) selects to also need to be extracted in the first program from memory block 602 (the hereinafter also referred to second non-idle physics erasing is single at least one non-idle physics erasing unit of effect data Unit).Wherein, Second Rule and the first rule are different.Such as, this Second Rule can include selecting storage Valid data more than above-mentioned preset value, storage invalid data less than above-mentioned preset value or randomly choose The non-idle physics erasing unit that efficiency is the best is moved Deng for valid data.
As a example by the exemplary embodiment of Fig. 7 A and Fig. 7 B, it is assumed that be predefined in the first program to be collected permissible Write full " N " individual idle physics erasing unit (that is, the 3rd leave unused physics erasing unit) valid data (as Shown in Fig. 7 A), but when collecting the valid data writing full or write " M " individual physics erasing unit Discharge " N+1 " individual new idle physics erasing unit (as shown in Figure 7 B).In the case, First it is written into the valid data of so far " M " individual physics erasing unit e.g. from selected according to the first rule The multiple non-idle physics erasing unit (that is, the first non-idle physics erasing unit) selected is extracted, and It is written into the valid data of individual to remaining " N-M " or more idle physics erasing unit after a while the most such as It is that (that is, the second non-idle physics erasing is single from wiping unit according to the non-idle physics selected by Second Rule Unit) in extracted.
In other words, relative to Second Rule, the first rule for the screening of non-idle physics erasing unit is The strictest, and select non-idle physics erasing unit also relative to according to second according to the first rule Rule selects non-idle physics erasing unit may need to expend more system resource.Therefore, one In exemplary embodiment, detect discharge meet preset number idle physics erasing unit after, By using Second Rule to select the non-idle physics erasing unit of remaining valid data to be extracted, will The system resource expended finding non-idle physics erasing unit can be saved.Additionally, implement at another example In example, it is also possible to maintain and use the first rule or Second Rule to select to be extracted to have in the first program The all non-idle physics erasing unit of effect data, the present invention is not any limitation as.
Fig. 8 is the flow chart of the storage management method shown by one example of the present invention embodiment.
Refer to Fig. 8, in step S801, receive a write instruction and according to said write instruction from can Multiple physics erasing unit of manifolding formula non-volatile memory module select an idle physics erasing single Unit writes the data corresponding to this write instruction.In step S802, detect described physics erasing unit In do not comprise selected in step S801 idle physics erasing unit remaining idle physics erasing unit Number.In step S803, it is judged that the idle physics erasing unit detected in step S802 Whether number is less than a threshold value.Here, this threshold value is the first threshold value.If the unused material detected The number of reason erasing unit is not less than described first threshold value, then step S801 can be repeatedly executed.
If the number of described remaining idle physics erasing unit is less than described first threshold value, in step In S804, perform that data are whole and idle physics that program (that is, above-mentioned first program) makes new advances with release is wiped Except unit.Additionally, in step S804, according to the practice condition of the first program, be used for judging whether to hold Described first threshold value of row the first program can be adjusted.Here, described threshold value can be by from the first threshold Value is adjusted to the second threshold value.About how to perform the first program and how to adjust threshold value in aforementioned Exemplary embodiment illustrates, does not repeats at this.
In step S805, it is judged that idle physics current in reproducible nonvolatile memorizer module is wiped Except whether the number of unit is more than the second threshold value set in step S804.If step S805 Judged result is no, represents idle physics erasing unit or deficiency, therefore step S804 can be repeatedly executed To discharge more idle physics erasing unit.If the judged result of step S805 is yes, then in step In S806, stop first program that performs and again adjust threshold value.Such as, by threshold value from current Two threshold values are adjusted to the 3rd threshold value.Such as, this second threshold value can be the first threshold value or any Preset value.After step S806, step S801 can be repeatedly executed.
It is noted that in step S804, it is also possible to judge currently used in threshold value be whether First threshold value (or second threshold value).If the threshold value in currently used is the first threshold value, then can root According to the practice condition of executory first program, this threshold value is adjusted to the second threshold value.If currently making Threshold value in is not the first threshold value, such as, currently used in threshold value be adjusted Second threshold value, then this threshold value will not be adjusted again.Whereby, threshold value can be avoided to be repeated to adjust Whole.
But, in Fig. 8, each step has described in detail as above, just repeats no more at this.It should be noted that In Fig. 8, each step can be implemented as multiple procedure code or circuit, and the present invention is not any limitation as.Additionally, The method of Fig. 8 example above embodiment of can arranging in pairs or groups uses, it is also possible to being used alone, the present invention is the most in addition Limit.
In sum, storage management method provided by the present invention, memorizer control circuit unit and deposit Reservoir storage device, is dynamically adjusted for deciding whether that execution moves operation for valid data The threshold value of (that is, data whole and program).Particularly, when the release efficiency for idle physics erasing unit Time very well, the adjustment amplitude of this threshold value can be increased；And when the release effect for idle physics erasing unit When rate is bad, then can reduce the adjustment amplitude of this threshold value.Whereby, by for triggering valid data Move the control of operation, such as, the valid data performed by prolongation move operation, can make to make carbon copies The data access speed of formula non-volatile memory module is relatively stable.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, rather than right It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common Skilled artisans appreciate that the technical scheme described in foregoing embodiments still can be modified by it, Or the most some or all of technical characteristic is carried out equivalent；And these amendments or replacement, and The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.

Claims (24)

1. a storage management method, for reproducible nonvolatile memorizer module, its feature exists In, described reproducible nonvolatile memorizer module includes that multiple physics wipes unit, described memorizer Management method includes:
Receive the first write instruction and the data corresponding to described first write instruction are write to those physics Erasing unit in first leave unused physics erasing unit；
Detect those physics erasing unit in do not comprise described first leave unused physics erasing unit multiple second The number of idle physics erasing unit；
Judge whether those second numbers leaving unused physics erasing unit are less than threshold value；And
If those second numbers leaving unused physics erasing unit are less than described threshold value, perform the first program,
Wherein said first program includes:
Many valid data in those physics erasing unit are moved to those physics erasing unit At least one the 3rd leave unused physics erasing unit in；And
Described threshold value is adjusted to the second threshold value from the first threshold value.
Storage management method the most according to claim 1, it is characterised in that by described threshold value The step being adjusted to described second threshold value from described first threshold value includes:
Record storage valid data described at least one the 3rd leave unused physics erasing unit number；And
Institute is determined according to the number that described in storage valid data at least the 3rd leaves unused physics erasing unit State the second threshold value.
Storage management method the most according to claim 2, it is characterised in that record storage is effectively The leave unused step of number of physics erasing unit of described at least the one the 3rd of data includes:
Judge the valid data the most allochthonous multiple first non-spare time stored in those physics erasing unit Whether the number of glove reason erasing unit meets preset number；And
If the described number of those first non-idle physics erasing unit meets described preset number, record is deposited Storage valid data described at least one the 3rd leave unused physics erasing unit number.
Storage management method the most according to claim 3, it is characterised in that according to storage effectively Described at least the one the 3rd of data leave unused physics erasing unit number to determine the step of described second threshold value Suddenly include:
Not busy with described in storage valid data at least one the 3rd according to the reference value corresponding to described preset number The number of glove reason erasing unit determines the difference between described first threshold value and described second threshold value Value,
Wherein said reference value is that described preset number subtracts one.
Storage management method the most according to claim 3, it is characterised in that also include:
Configure multiple logical block；And
Total physical capacity and total logical capacity of those logical blocks according to those physics erasing unit are come certainly Fixed described preset number,
Wherein said total physical capacity is more than described total logical capacity.
Storage management method the most according to claim 3, it is characterised in that described first program Also include:
Select the erasing of those first non-idle physics single according to the first rule from those physics erasing unit Unit；And
After the number judging those first non-idle physics erasing unit meets described preset number, root Select not comprise those first non-idle physics erasing unit from those physics erasing unit according to Second Rule At least one second non-idle physics erasing unit,
Wherein said first regular and described Second Rule is different.
Storage management method the most according to claim 1, it is characterised in that also include:
After performing described first program, receive the second write instruction；
Detect those physics erasing unit in the multiple 4th leave unused physics erasing unit number；
Judge whether those the 4th numbers leaving unused physics erasing unit are more than described second threshold value；And
If those the 4th numbers leaving unused physics erasing unit perform institute more than described second threshold value, stopping State the first program and described threshold value is adjusted to the 3rd threshold value from described second threshold value.
Storage management method the most according to claim 7, it is characterised in that described 3rd threshold Value is equal to described first threshold value.
9. a memorizer control circuit unit, is used for controlling reproducible nonvolatile memorizer module, It is characterized in that, described memorizer control circuit unit includes:
HPI, is electrically connected to host computer system；
Memory interface, is electrically connected to described reproducible nonvolatile memorizer module, wherein Described reproducible nonvolatile memorizer module includes that multiple physics wipes unit；And
Memory management circuitry, is electrically connected to described HPI and described memory interface,
Wherein said memory management circuitry in order to receive the first write instruction and send write instruction sequence with Indicate first data corresponding to described first write instruction write to those physics erasing unit not busy Glove reason erasing unit,
Wherein said memory management circuitry does not also comprise described the in order to detecting in those physics erasing unit One leave unused physics erasing unit multiple second leave unused physics erasing unit number,
Wherein said memory management circuitry also in order to judge those second leave unused physics erasing unit number Whether less than threshold value,
If wherein those second numbers leaving unused physics erasing unit are less than described threshold value, described memorizer Management circuit also in order to perform the first program,
Wherein said first program includes:
Many valid data in those physics erasing unit are moved to those physics erasing unit At least one the 3rd leave unused physics erasing unit in；And
Described threshold value is adjusted to the second threshold value from the first threshold value.
Memorizer control circuit unit the most according to claim 9, it is characterised in that described in deposit Described threshold value is adjusted to the operation of described second threshold value by reservoir management circuit from described first threshold value Including:
Record storage valid data described at least one the 3rd leave unused physics erasing unit number；And
Institute is determined according to the number that described in storage valid data at least the 3rd leaves unused physics erasing unit State the second threshold value.
11. memorizer control circuit unit according to claim 10, it is characterised in that described in deposit Reservoir management circuit record storage valid data described at least one the 3rd leave unused physics erasing unit number Operation include:
Judge the valid data the most allochthonous multiple first non-spare time stored in those physics erasing unit Whether the number of glove reason erasing unit meets preset number；And
If the described number of those first non-idle physics erasing unit meets described preset number, record is deposited Storage valid data described at least one the 3rd leave unused physics erasing unit number.
12. memorizer control circuit unit according to claim 11, it is characterised in that described in deposit Reservoir management circuit according to storage valid data described at least one the 3rd leave unused physics erasing unit number Determine that the operation of described second threshold value includes:
Not busy with described in storage valid data at least one the 3rd according to the reference value corresponding to described preset number The number of glove reason erasing unit determines the difference between described first threshold value and described second threshold value Value,
Wherein said reference value is that described preset number subtracts one.
13. memorizer control circuit unit according to claim 11, it is characterised in that described in deposit Reservoir management circuit also in order to configure multiple logical block,
Wherein said memory management circuitry also in order to according to those physics erasing unit total physical capacity with Total logical capacity of those logical blocks determines described preset number,
Wherein said total physical capacity is more than described total logical capacity.
14. memorizer control circuit unit according to claim 11, it is characterised in that described in deposit Reservoir management circuit performs the operation of described first program and also includes:
Select the erasing of those first non-idle physics single according to the first rule from those physics erasing unit Unit；And
After the number judging those first non-idle physics erasing unit meets described preset number, root Select not comprise those first non-idle physics erasing unit from those physics erasing unit according to Second Rule At least one second non-idle physics erasing unit,
Wherein said first regular and described Second Rule is different.
15. memorizer control circuit unit according to claim 9, it is characterised in that performing After described first program, described memory management circuitry also in order to receive the second write instruction,
Wherein said memory management circuitry also in order to detect those physics erasing unit in the multiple 4th leave unused The number of physics erasing unit,
Wherein said memory management circuitry also in order to judge those the 4th leave unused physics erasing unit number Whether more than described second threshold value,
If wherein those the 4th leave unused numbers of physics erasing unit are more than described second threshold value, described in deposit Reservoir management circuit also performs described first program and by described threshold value from described second in order to stopping Threshold value is adjusted to the 3rd threshold value.
16. memorizer control circuit unit according to claim 15, it is characterised in that described Three threshold values are equal to described first threshold value.
17. 1 kinds of memory storage apparatus, it is characterised in that including:
Connect interface unit, be electrically connected to host computer system；
Reproducible nonvolatile memorizer module, wipes unit including multiple physics；And
Memorizer control circuit unit, is electrically connected to described connection interface unit non-with described duplicative Volatile,
Wherein said memorizer control circuit unit is in order to receive the first write instruction and to send write instruction sequence Arrange, with instruction, the data corresponding to described first write instruction are write the to those physics erasing unit One leave unused physics erasing unit,
Wherein said memorizer control circuit unit also in order to detect those physics erasing unit in do not comprise institute State first leave unused physics erasing unit multiple second leave unused physics erasing unit number,
Wherein said memorizer control circuit unit is also in order to judge that those second leave unused physics erasing unit Whether number is less than threshold value,
If wherein those second numbers leaving unused physics erasing unit are less than described threshold value, described memorizer Control circuit unit also in order to perform the first program,
Wherein said first program includes:
Many valid data in those physics erasing unit are moved to those physics erasing unit At least one the 3rd leave unused physics erasing unit in；And
Described threshold value is adjusted to the second threshold value from the first threshold value.
18. memory storage apparatus according to claim 17, it is characterised in that described memorizer Described threshold value is adjusted to the operation of described second threshold value by control circuit unit from described first threshold value Including:
Record storage valid data described at least one the 3rd leave unused physics erasing unit number；And
Institute is determined according to the number that described in storage valid data at least the 3rd leaves unused physics erasing unit State the second threshold value.
19. memory storage apparatus according to claim 18, it is characterised in that described memorizer Control circuit unit record storage valid data described at least one the 3rd leave unused physics erasing unit number Operation include:
Judge the valid data the most allochthonous multiple first non-spare time stored in those physics erasing unit Whether the number of glove reason erasing unit meets preset number；And
If the number of those first non-idle physics erasing unit meets described preset number, record storage has Effect data described at least one the 3rd leave unused physics erasing unit number.
20. memory storage apparatus according to claim 19, it is characterised in that described memorizer Control circuit unit according to storage valid data described at least one the 3rd leave unused physics erasing unit number Determine that the operation of described second threshold value includes:
Not busy with described in storage valid data at least one the 3rd according to the reference value corresponding to described preset number The number of glove reason erasing unit determines the difference between described first threshold value and described second threshold value Value,
Wherein said reference value is that described preset number subtracts one.
21. memory storage apparatus according to claim 19, it is characterised in that described memorizer Control circuit unit also in order to configure multiple logical block,
Wherein said memorizer control circuit unit is also in order to hold according to total physics of those physics erasing unit Amount determines described preset number with total logical capacity of those logical blocks,
Wherein said total physical capacity is more than described total logical capacity.
22. memory storage apparatus according to claim 19, it is characterised in that described memorizer Control circuit unit performs the operation of described first program and also includes:
Select the erasing of those first non-idle physics single according to the first rule from those physics erasing unit Unit；And
After the number judging those first non-idle physics erasing unit meets described preset number, root Select not comprise those first non-idle physics erasing unit from those physics erasing unit according to Second Rule At least one second non-idle physics erasing unit,
Wherein said first regular and described Second Rule is different.
23. memory storage apparatus according to claim 17, it is characterised in that described in performing After first program, described memorizer control circuit unit also in order to receive the second write instruction,
Wherein said memorizer control circuit unit also in order to detect those physics erasing unit in the multiple 4th The number of idle physics erasing unit,
Wherein said memorizer control circuit unit is also in order to judge that those the 4th leave unused physics erasing unit Whether number is more than described second threshold value,
If wherein those the 4th leave unused numbers of physics erasing unit are more than described second threshold value, described in deposit Memory control circuit unit also performs described first program and by described threshold value from described in order to stopping Two threshold values are adjusted to the 3rd threshold value.
24. memory storage apparatus according to claim 23, it is characterised in that described 3rd Threshold value is equal to described first threshold value.
CN201510396806.1A 2015-07-08 2015-07-08 Memory management method, memory control circuit unit and memory storage device Active CN106325764B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510396806.1A CN106325764B (en) 2015-07-08 2015-07-08 Memory management method, memory control circuit unit and memory storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510396806.1A CN106325764B (en) 2015-07-08 2015-07-08 Memory management method, memory control circuit unit and memory storage device

Publications (2)

Publication Number Publication Date
CN106325764A true CN106325764A (en) 2017-01-11
CN106325764B CN106325764B (en) 2021-02-26

Family

ID=57726012

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510396806.1A Active CN106325764B (en) 2015-07-08 2015-07-08 Memory management method, memory control circuit unit and memory storage device

Country Status (1)

Country Link
CN (1) CN106325764B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110308876A (en) * 2019-07-01 2019-10-08 合肥兆芯电子有限公司 Storage management method, memory storage apparatus and memorizer control circuit unit
WO2020133728A1 (en) * 2018-12-28 2020-07-02 深圳市德名利电子有限公司 Data storage dynamic recovery processing method and storage device
CN111414128A (en) * 2019-01-07 2020-07-14 群联电子股份有限公司 Memory management method, memory storage device and memory control circuit unit
CN113707192A (en) * 2021-09-01 2021-11-26 合肥兆芯电子有限公司 Memory temperature control frequency modulation method and memory temperature control frequency modulation system

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6341342B1 (en) * 1997-11-04 2002-01-22 Compaq Information Technologies Group, L.P. Method and apparatus for zeroing a transfer buffer memory as a background task
JP2003076604A (en) * 2001-09-03 2003-03-14 Nec Access Technica Ltd Log information collecting system and method for flash memory
CN1627271A (en) * 2003-12-10 2005-06-15 三星电子株式会社 Flash memory and mapping control apparatus and method for flash memory
CN1770319A (en) * 2004-09-29 2006-05-10 索尼株式会社 Storage apparatus and semiconductor apparatus
CN101233499A (en) * 2005-08-03 2008-07-30 桑迪士克股份有限公司 Reclaiming data storage capacity in flash memory systems
CN101438353A (en) * 2006-05-05 2009-05-20 桑迪士克股份有限公司 Non-volatile memory with background data latch caching during read operations and methods therefor
CN101458658A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Data storage method and apparatus for flash memory
CN101615427A (en) * 2008-06-24 2009-12-30 群联电子股份有限公司 The controller of the storage management method of nonvolatile memory and use the method
CN101673243A (en) * 2009-09-29 2010-03-17 威盛电子股份有限公司 Data storage device and method
US20110022778A1 (en) * 2009-07-24 2011-01-27 Lsi Corporation Garbage Collection for Solid State Disks
CN102193869A (en) * 2010-03-01 2011-09-21 群联电子股份有限公司 Memory management and write-in method, memory controller and storage system
CN102473140A (en) * 2009-07-17 2012-05-23 株式会社东芝 Memory management device
CN103488579A (en) * 2012-06-11 2014-01-01 群联电子股份有限公司 Memory management method, memory controller and memory storage device
CN103544115A (en) * 2012-07-10 2014-01-29 群联电子股份有限公司 Data writing method, memorizer controller and memorizer storage device
US20140032817A1 (en) * 2012-07-27 2014-01-30 International Business Machines Corporation Valid page threshold based garbage collection for solid state drive
CN103617124A (en) * 2013-11-26 2014-03-05 北京创毅视讯科技有限公司 Flash memory management method and device
CN103631529A (en) * 2012-08-21 2014-03-12 群联电子股份有限公司 Data writing method, storage controller and storage storing device
US20150067239A1 (en) * 2013-08-30 2015-03-05 Silicon Motion, Inc. Data storage device and flash memory control method

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6341342B1 (en) * 1997-11-04 2002-01-22 Compaq Information Technologies Group, L.P. Method and apparatus for zeroing a transfer buffer memory as a background task
JP2003076604A (en) * 2001-09-03 2003-03-14 Nec Access Technica Ltd Log information collecting system and method for flash memory
CN1627271A (en) * 2003-12-10 2005-06-15 三星电子株式会社 Flash memory and mapping control apparatus and method for flash memory
CN1770319A (en) * 2004-09-29 2006-05-10 索尼株式会社 Storage apparatus and semiconductor apparatus
CN101233499A (en) * 2005-08-03 2008-07-30 桑迪士克股份有限公司 Reclaiming data storage capacity in flash memory systems
CN101438353A (en) * 2006-05-05 2009-05-20 桑迪士克股份有限公司 Non-volatile memory with background data latch caching during read operations and methods therefor
CN101458658A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Data storage method and apparatus for flash memory
CN101615427A (en) * 2008-06-24 2009-12-30 群联电子股份有限公司 The controller of the storage management method of nonvolatile memory and use the method
CN102473140A (en) * 2009-07-17 2012-05-23 株式会社东芝 Memory management device
US20110022778A1 (en) * 2009-07-24 2011-01-27 Lsi Corporation Garbage Collection for Solid State Disks
CN101673243A (en) * 2009-09-29 2010-03-17 威盛电子股份有限公司 Data storage device and method
CN102193869A (en) * 2010-03-01 2011-09-21 群联电子股份有限公司 Memory management and write-in method, memory controller and storage system
CN103488579A (en) * 2012-06-11 2014-01-01 群联电子股份有限公司 Memory management method, memory controller and memory storage device
CN103544115A (en) * 2012-07-10 2014-01-29 群联电子股份有限公司 Data writing method, memorizer controller and memorizer storage device
US20140032817A1 (en) * 2012-07-27 2014-01-30 International Business Machines Corporation Valid page threshold based garbage collection for solid state drive
CN103631529A (en) * 2012-08-21 2014-03-12 群联电子股份有限公司 Data writing method, storage controller and storage storing device
US20150067239A1 (en) * 2013-08-30 2015-03-05 Silicon Motion, Inc. Data storage device and flash memory control method
CN103617124A (en) * 2013-11-26 2014-03-05 北京创毅视讯科技有限公司 Flash memory management method and device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JUNGHO PARK; CHOONKI JANG; JAEJIN LEE: "A Software-Managed Coherent Memory Architecture for Manycores", 《2011 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES》 *
张殿奎: "SAN存储网络管理与存储资源管理的应用分析", 《硅谷》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020133728A1 (en) * 2018-12-28 2020-07-02 深圳市德名利电子有限公司 Data storage dynamic recovery processing method and storage device
CN111414128A (en) * 2019-01-07 2020-07-14 群联电子股份有限公司 Memory management method, memory storage device and memory control circuit unit
CN111414128B (en) * 2019-01-07 2023-03-14 群联电子股份有限公司 Memory management method, memory storage device and memory control circuit unit
CN110308876A (en) * 2019-07-01 2019-10-08 合肥兆芯电子有限公司 Storage management method, memory storage apparatus and memorizer control circuit unit
CN113707192A (en) * 2021-09-01 2021-11-26 合肥兆芯电子有限公司 Memory temperature control frequency modulation method and memory temperature control frequency modulation system

Also Published As

Publication number Publication date
CN106325764B (en) 2021-02-26

Similar Documents

Publication Publication Date Title
US9582416B2 (en) Data erasing method, memory control circuit unit and memory storage apparatus
TWI585770B (en) Memory management method, memory control circuit unit and memory storage device
US9772797B2 (en) Buffer memory management method, memory control circuit unit and memory storage device
CN104765569A (en) Data write-in method, memory control circuit unit and memory storing device
CN104866429A (en) Memory management method, memory control circuit unit and memory storage device
CN105320464A (en) Method for preventing reading interference, storage control circuit unit and storage device
CN106325764A (en) Memory management method, memory control circuit unit and memory storage apparatus
CN103544115A (en) Data writing method, memorizer controller and memorizer storage device
CN104636267A (en) Storage control method, storage storing device and storage control circuit unit
CN105022695A (en) Data storage method, memorizer control circuit unit and memorizer storage device
CN103136111A (en) Data writing method, memorizer controller and memorizer storage device
CN103544118B (en) Memorizer memory devices, its Memory Controller and method for writing data
CN103678162A (en) System data storage method, memorizer controller and memorizer storing device
CN103914391B (en) Method for reading data, Memory Controller and memory storage apparatus
CN105988950A (en) Memory management method, memory control circuit unit and memory storage device
CN106445397B (en) Storage management method, memorizer control circuit unit and memory storage apparatus
CN105224238A (en) Storage management method, memory storage apparatus and memorizer control circuit unit
US9778862B2 (en) Data storing method for preventing data losing during flush operation, memory control circuit unit and memory storage apparatus
CN103513930A (en) Memorizer management method, memorizer controller and memorizer storage device
CN103218308B (en) Buffer storage supervisory method, Memory Controller and memorizer memory devices
CN106354651B (en) Average wear method, memory control circuit unit and memory storage device
CN104731710A (en) Memory management method, memory control circuit unit and memory storage device
CN108108118B (en) Data writing method and storage controller
CN102087632B (en) Data storage method for flash memory, controller and storage system
CN103488579A (en) Memory management method, memory controller and memory storage device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant