CN105810245A - Data sampling circuit module, data sampling method and memory storage device - Google Patents
Data sampling circuit module, data sampling method and memory storage device Download PDFInfo
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- CN105810245A CN105810245A CN201410849276.7A CN201410849276A CN105810245A CN 105810245 A CN105810245 A CN 105810245A CN 201410849276 A CN201410849276 A CN 201410849276A CN 105810245 A CN105810245 A CN 105810245A
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Abstract
The invention provides a data sampling circuit module, a data sampling method and a memory storage device. The data sampling method comprises receiving a differential signal, producing a sensing voltage pair according to the differential signal, wherein the sensing voltage pair comprises first sensing voltage and second sensing voltage, the first sensing voltage value is related to a first differential signal in the differential signal and the second sensing voltage value is related to a second differential signal in the differential signal, receiving the sensing voltage and outputting sampling data stream according to a related relationship of a clock rate of the differential signal and voltages of the sensing voltage pair.
Description
Technical field
The invention relates to a kind of data-sampling circuit module, and in particular to a kind of data-sampling circuit module, method of data samples and memorizer memory devices.
Background technology
It is said that in general, for the power consumption saving signal transmission, some data can be transmitted in the way of differential wave.After receiving end device receives one group of differential wave, this differential wave can be responded into an input data stream.This input data stream is made up of a series of pulse, and the waveform of these pulses can be relevant with the Bit data being intended to transmission.Such as, a certain waveform indicates that transmitted bit data " 1 ", and another kind of waveform indicates that transmitted bit data " 0 ".
Traditionally, in order to identify the waveform of each pulse in above-mentioned input data stream, this data stream can be sampled in large quantities by receiving end device by the clock signal that clock frequency is very high, and the signal obtained by analytical sampling is to fall within logic high in data stream or logic low, reconstructs the impulse waveform in data stream.But, this sampling mode needs the clock signal using frequency very high, and the power consumption for system is relatively big, and uses upper efficiency also not good.
Summary of the invention
The present invention provides a kind of data-sampling circuit module, method of data samples and memorizer memory devices, can effectively promote the efficiency that the differential wave received is processed.
One example of the present invention embodiment provides a kind of data-sampling circuit module, and it includes sensing circuit and sample circuit.Described sensing circuit is in order to receive differential wave and to produce sensing voltage pair according to described differential wave, wherein said sensing voltage is to including the first sensing voltage and the second sensing voltage, first magnitude of voltage of described first sensing voltage is relevant with the first differential wave in described differential wave, and the second magnitude of voltage of described second sensing voltage is relevant with the second differential wave in described differential wave.Described sample circuit is electrically connected to described sensing circuit, wherein said sample circuit in order to receive described sensing voltage to and export sampled data crossfire according to the seasonal pulse of described differential wave and the voltage relativeness of described sensing voltage pair.
In one example of the present invention embodiment, described sensing circuit includes sense amplifying circuits and voltage-current converter circuit.Described sense amplifying circuits is in order to receive described differential wave and described differential wave to perform sensing amplification to export rectification pulse signal.Described voltage-current converter circuit is electrically connected to described sense amplifying circuits, and wherein said voltage-current converter circuit is in order to receive described rectification pulse signal and to perform charge/discharge operation to produce described sensing voltage pair according to described rectification pulse signal.
In one example of the present invention embodiment, described voltage-current converter circuit includes the first charge/discharge circuit and the second charge/discharge circuit.Described first charge/discharge circuit is corrected pulse signal in order to receive in described rectification pulse signal first and performs the first charge/discharge operation to produce described first sensing voltage according to described first rectification pulse signal.Described second charge/discharge circuit is corrected pulse signal in order to receive in described rectification pulse signal second and performs the second charge/discharge operation to produce described second sensing voltage according to described second rectification pulse signal.
In one example of the present invention embodiment, described first charge/discharge circuit includes the first capacitor cell, the first charging current source and the first charge switch.Wherein said first sensing voltage refers to the first electric potential difference of described first capacitor cell.Described first charge switch is serially connected with the first charge path between described first capacitor cell and described first charging current source and corrects the first charge path described in pulse signal and on and off in order to react on described first.
In one example of the present invention embodiment, described first charge/discharge circuit also includes the first discharge current source and the first discharge switch.Described first discharge switch is serially connected with the first discharge path between described first capacitor cell and described first discharge current source and corrects pulse signal in order to react on described first and close or turn on described first discharge path.
In one example of the present invention embodiment, described second charge/discharge circuit includes the second capacitor cell, the second charging current source and the second charge switch.Wherein said second sensing voltage refers to the second electric potential difference of described second capacitor cell.Described second charge switch is serially connected with the second charge path between described second capacitor cell and described second charging current source and corrects the second charge path described in pulse signal and on and off in order to react on described second.
In one example of the present invention embodiment, described second charge/discharge circuit also includes the second discharge current source and the second discharge switch.Described second discharge switch is serially connected with the second discharge path between described second capacitor cell and described second discharge current source and corrects pulse signal in order to react on described second and close or turn on described second discharge path.
In one example of the present invention embodiment, described sample circuit includes comparison circuit.Described comparison circuit in order to receive described sensing voltage to and carry out the first magnitude of voltage described in comparison with described second magnitude of voltage to obtain described voltage relativeness according to the described seasonal pulse of described differential wave, if wherein described voltage relativeness is that described first magnitude of voltage is more than described second magnitude of voltage, described comparison circuit exports the first sampled data, if wherein described voltage relativeness be described first magnitude of voltage less than described second magnitude of voltage, described comparison circuit exports the second sampled data.
In one example of the present invention embodiment, described sensing circuit also includes reset circuit.Described reset circuit is electrically connected to described sense amplifying circuits and described voltage-current converter circuit and in order to reset described sensing voltage pair according to the described seasonal pulse of described differential wave.
In one example of the present invention embodiment, described differential wave is to utilize pulse width modulation (PulseWidthModulation, abbreviation: PWM) pulse width modulating signal produced by technology.
In one example of the present invention embodiment, described data-sampling circuit module is configured in memorizer memory devices, wherein when the memorizer control circuit unit of described memorizer memory devices or described memorizer memory devices is in non-normal working pattern, described data-sampling circuit module is activated, wherein when described memorizer memory devices or described memorizer control circuit unit are in normal mode of operation, described data-sampling circuit module is not activated by.
Another example of the present invention embodiment provides a kind of method of data samples, comprising: receive differential wave and produce sensing voltage pair according to described differential wave, wherein said sensing voltage is to including the first sensing voltage and the second sensing voltage, first magnitude of voltage of described first sensing voltage is relevant with the first differential wave in described differential wave, and the second magnitude of voltage of described second sensing voltage is relevant with the second differential wave in described differential wave；And receive described sensing voltage to and export sampled data crossfire according to the seasonal pulse of described differential wave and the voltage relativeness of described sensing voltage pair.
In one example of the present invention embodiment, the described differential wave of described reception and the step according to the described differential wave described sensing voltage pair of generation include: receive described differential wave and described differential wave perform sensing amplification to export rectification pulse signal；And receive described rectification pulse signal and perform charge/discharge operation to produce described sensing voltage pair according to described rectification pulse signal.
In one example of the present invention embodiment, described reception described rectification pulse signal and according to described rectification pulse signal perform described charge/discharge operation step include: receive in described rectification pulse signal first correct pulse signal and according to described first correct pulse signal perform first charge/discharge operation with produce described first sensing voltage；And receive the second rectification pulse signal in described rectification pulse signal and perform the second charge/discharge operation to produce described second sensing voltage according to described second rectification pulse signal.
In one example of the present invention embodiment, described first sensing voltage refers to the first electric potential difference of the first capacitor cell, and corrects pulse signal according to described first and perform the step of described first charge/discharge operation and include: reacts on described first and corrects pulse signal and the first charge path between the first capacitor cell and the first charging current source described on and off.
In one example of the present invention embodiment, the described step according to the described first described first charge/discharge operation of rectification pulse signal execution also includes: reacts on described first and corrects pulse signal and close or turn on the first discharge path between described first capacitor cell and the first discharge current source.
In one example of the present invention embodiment, described second sensing voltage refers to the second electric potential difference of the second capacitor cell, and corrects pulse signal according to described second and perform the step of described second charge/discharge operation and include: reacts on described second and corrects pulse signal and the second charge path between the second capacitor cell and the second charging current source described on and off.
In one example of the present invention embodiment, the described step according to the described second described second charge/discharge operation of rectification pulse signal execution also includes: reacts on described second and corrects pulse signal and close or turn on the second discharge path between described second capacitor cell and the second discharge current source.
In one example of the present invention embodiment, the described step exporting described sampled data crossfire with the described voltage relativeness of described sensing voltage pair according to the described seasonal pulse of described differential wave includes: receive described sensing voltage to and compare described first magnitude of voltage with described second magnitude of voltage to obtain described voltage relativeness according to the described seasonal pulse of described differential wave；If described voltage relativeness be described first magnitude of voltage more than described second magnitude of voltage, export the first sampled data；And if described voltage relativeness be described first magnitude of voltage less than described second magnitude of voltage, export the second sampled data.
In one example of the present invention embodiment, the described step according to the described differential wave described sensing voltage pair of generation also includes: reset described sensing voltage pair according to the described seasonal pulse of described differential wave.
In one example of the present invention embodiment, described method of data samples is used for a memorizer memory devices, wherein when the memorizer control circuit unit of described memorizer memory devices or described memorizer memory devices is in non-normal working pattern, perform described method of data samples, wherein when described memorizer memory devices or described memorizer control circuit unit are in normal mode of operation, do not perform described method of data samples.
Another example of the present invention embodiment provides a kind of memorizer memory devices, and it includes connecting interface unit, rewritable non-volatile memory module and memorizer control circuit unit.Described connection interface unit is electrically connected to host computer system.Described rewritable non-volatile memory module includes multiple entity erasing unit.Described memorizer control circuit unit is electrically connected to described connection interface unit and described rewritable non-volatile memory module, wherein said connection interface unit includes data-sampling circuit module, and described data-sampling circuit module includes sensing circuit and sample circuit.Described sensing circuit is in order to receive differential wave and to produce sensing voltage pair according to described differential wave, wherein said sensing voltage is to including the first sensing voltage and the second sensing voltage, first magnitude of voltage of described first sensing voltage is relevant with the first differential wave in described differential wave, and the second magnitude of voltage of described second sensing voltage is relevant with the second differential wave in described differential wave.Described sample circuit is electrically connected to described sensing circuit, wherein said sample circuit in order to receive described sensing voltage to and export sampled data crossfire according to the seasonal pulse of described differential wave and the voltage relativeness of described sensing voltage pair.
Based on above-mentioned, after receiving differential wave, the present invention can according to the sensing voltage that this differential wave produces to be correlated with to and export sampled data crossfire according to the seasonal pulse of this differential wave and the voltage relativeness of sensing voltage pair.Therefore, the efficiency that the differential wave received is processed can effectively be promoted.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the data-sampling circuit module shown by one example of the present invention embodiment；
Fig. 2 is the schematic diagram of the data-sampling circuit module shown by one example of the present invention embodiment；
Fig. 3 is the schematic diagram of the charge/discharge circuit shown by one example of the present invention embodiment；
Fig. 4 is the schematic diagram of the signal waveform shown by one example of the present invention embodiment；
Fig. 5 is the schematic diagram of the charge/discharge circuit shown by another example of the present invention embodiment；
Fig. 6 is the flow chart of the method for data samples shown by one example of the present invention embodiment；
Fig. 7 is the schematic diagram of the host computer system shown by one example of the present invention embodiment and memorizer memory devices；
Fig. 8 is the schematic diagram of the computer system shown by one example of the present invention embodiment and input/output device；
Fig. 9 is the schematic diagram of the host computer system shown by one example of the present invention embodiment and memorizer memory devices；
Figure 10 is the schematic block diagram illustrating the memorizer memory devices shown in Fig. 7；
Figure 11 is the schematic block diagram of the memorizer control circuit unit shown by one example of the present invention embodiment.
Description of reference numerals:
10,20: data-sampling circuit module；
11,21: sensing circuit；
12,22: sample circuit；
211: sense amplifying circuits；
212: voltage-current converter circuit；
213: reset circuit；
2121,2122,3121,3122,5121,5122: charge/discharge circuit；
221: comparison circuit；
331,332: capacitor cell；
341,343: charging current source；
342,344: discharge current source；
351,353: charge switch；
352,354: discharge switch；
CLK: seasonal pulse；
RS: reset signal；
RXDP, RXDN: differential wave；
SDS: sampled data crossfire；
SV1, SV2: sensing voltage；
T1～T5: time point；
Vreset: preset value；
S601, S602: step；
100: memorizer memory devices；
1000: host computer system；
1100: computer；
1102: microprocessor；
1104: random access memory；
1106: input/output device；
1108: system bus；
1110: data transmission interface；
1202: mouse；
1204: keyboard；
1206: display；
1208: printer；
1212:USB flash disk；
1214: storage card；
1216: solid state hard disc；
1310: digital camera；
1312:SD card；
1314:MMC card；
1316: memory stick；
1318:CF card；
1320: embedded storage device；
1002: connect interface unit；
1004: memorizer control circuit unit；
1006: rewritable non-volatile memory module；
304 (0)～304 (R): entity erasing unit；
202: memory management circuitry；
204: HPI；
206: memory interface；
252: buffer storage；
254: electric power management circuit；
256: error checking and correcting circuit.
Detailed description of the invention
Multiple embodiment set forth below illustrates the present invention, but the present invention is not limited only to illustrated multiple embodiments.Suitable combination is also still allowed for again between embodiment." electric connection " word used in this case description in full (including claim) can refer to any direct or indirect connection means.For example, if first device described in literary composition is electrically connected at the second device, then should be construed as this first device and can be directly connected to this second device, or this first device can be coupled indirectly to this second device by other devices or certain connection means.Additionally, " signal " word can refer at least one electric current, voltage, electric charge, temperature, data or any other one or more signal.
Fig. 1 is the schematic diagram of the data-sampling circuit module shown by one example of the present invention embodiment.
Refer to Fig. 1, data-sampling circuit module 10 includes sensing circuit 11 and sample circuit 12.
Sensing circuit 11 is in order to receive differential wave RXDP and RXDN and to produce one group of sensing voltage to (sensingvoltagepairs) according to differential wave RXDP and RXDN.In this exemplary embodiment, differential wave RXDP can be described as the first differential wave, and differential wave RXDN can be described as the second differential wave, and differential wave RXDP and RXDN can be collectively referred to as one group of differential wave pair.In another exemplary embodiment, differential wave RXDN is also referred to as the second differential wave, and differential wave RXDP is also referred to as the second differential wave.Differential wave RXDP and RXDN utilizes pulse width modulation (PulseWidthModulation, abbreviation: PWM) pulse width modulating signal produced by technology.In general, the amplitude of differential wave RXDP and RXDN is identical, and the opposite in phase of differential wave RXDP and RXDN.
Sensing voltage is to including sensing voltage SV1 (sensing voltage also referred to as first) and sensing voltage SV2 (sensing voltage also referred to as second).The magnitude of voltage (also referred to as the first magnitude of voltage) of sensing voltage SV1 is relevant with one of them (such as, the differential wave RXDP) of differential wave RXDP and RXDN.The magnitude of voltage (also referred to as the second magnitude of voltage) of sensing voltage SV2 is with relevant with another (such as, the differential wave RXDN) therein of differential wave RXDP and RXDN.Such as, the magnitude of voltage of sensing voltage SV1 is relevant with the waveform of differential wave RXDP, and the magnitude of voltage sensing voltage SV2 is relevant with the waveform of differential wave RXDN.
In this exemplary embodiment, the time span that the magnitude of voltage of sensing voltage SV1 is such as logic high (logicalhigh) with differential wave RXDP is proportionate, and the magnitude of voltage sensing voltage SV2 is such as that the time span of logic high with differential wave RXDN is proportionate.Or, opposite in phase due to differential wave RXDP and RXDN, therefore the time span that the magnitude of voltage of sensing voltage SV1 is such as logic high with differential wave RXDP is proportionate, and the magnitude of voltage sensing voltage SV2 is such as that the time span of logic low (logicallow) with differential wave RXDP is proportionate.
Sample circuit 12 is electrically connected to sensing circuit 11.Sample circuit 12 in order to receive sensing voltage to and according to the seasonal pulse of differential wave RXDP and RXDN and sense the voltage relativeness of voltage pair and export sampled data crossfire SDS.In this exemplary embodiment, the voltage relativeness of sensing voltage pair refers to that the magnitude of voltage of sensing voltage SV1 is greater than or less than the magnitude of voltage sensing voltage SV2.In another exemplary embodiment, the voltage relativeness of sensing voltage pair may also mean that whether the magnitude of voltage of sensing voltage SV1 is more than a threshold value, and/or whether the magnitude of voltage of sensing voltage SV2 is less than this threshold value or another threshold value.Additionally, in another exemplary embodiment, the voltage relativeness of sensing voltage pair can also be arbitrarily useful numerical relation, and the present invention is not any limitation as.
Specifically, sample circuit 12 at the specific time point magnitude of voltage to sensing voltage SV1 according to the seasonal pulse CLK of differential wave RXDP and RXDN (or, clock frequency) and can sense the magnitude of voltage of voltage SV2 and is sampled.In general, in differential wave RXDP and RXDN, the Bit data of transmission is using a clock cycle as unit, for instance, the pulse belonging to same clock cycle is to transmit a Bit data.Therefore, in this exemplary embodiment, this specific time point is the edge of each clock cycle in seasonal pulse CLK.If the voltage relativeness that sample circuit 12 judges sensing voltage pair is belonging to first kind relation, then sample circuit 12 can export the sampled data (also referred to as the first sampled data) of the first type；If the voltage relativeness that sample circuit 12 judges sensing voltage pair is belonging to Equations of The Second Kind relation, then sample circuit 12 can export the sampled data (also referred to as the second sampled data) of the second type.In this exemplary embodiment, the sampled data of the first type refers to bit " 1 ", and the sampled data of the second type refers to bit " 0 ".In another exemplary embodiment, the sampled data of the first type refers to bit " 0 ", and the sampled data of the second type refers to bit " 1 ".But, in another exemplary embodiment, the sampled data of each type may also mean that the combination (such as, " 01 " or " 010 " etc.) of multiple bit, and the present invention is not any limitation as.Seasonal pulse CLK according to differential wave RXDP and RXDN (or, clock frequency), sample circuit 12 can export the sampled data crossfire SDS with same or similar seasonal pulse (or, clock frequency).
Fig. 2 is the schematic diagram of the data-sampling circuit module shown by one example of the present invention embodiment.
Refer to Fig. 2, data-sampling circuit module 20 includes sensing circuit 21 and sample circuit 22.Sensing circuit 21 and sample circuit 22 are same or similar in sensing circuit 11 and sample circuit 12 respectively.Sensing circuit 21 includes sense amplifying circuits 211 and voltage-current converter circuit 212.Sample circuit 22 includes comparison circuit 221.
Sense amplifying circuits 211 is in order to receive differential wave RXDP and RXDN and differential wave RXDP and RXDN to perform sensing amplification to export rectification pulse signal.Relative to differential wave RXDP and RXDN, the signal intensity correcting pulse signal is all stronger with noise resisting ability.Additionally, the waveform relative to differential wave RXDP and RXDN, the waveform correcting pulse signal is likely to closer to square wave (SquareWave).In this exemplary embodiment, correct pulse signal and include the first rectification pulse signal and the second rectification pulse signal of individual transmission.First rectification pulse signal is to be amplified by differential wave RXDP sensing and obtain, and the second rectification pulse signal is differential wave RXDN sensing amplification to be obtained.Additionally, in another exemplary embodiment, correct pulse signal and can first be performed phasing back before being input to voltage-current converter circuit 212, thus the first rectification pulse signal and second producing phase with one another contrary corrects pulse signal.
Voltage-current converter circuit 212 is electrically connected to sense amplifying circuits 211.Voltage-current converter circuit 212 is in order to receive rectification pulse signal and to perform charge/discharge operation to produce sensing voltage pair according to correcting pulse signal.
Specifically, voltage-current converter circuit 212 includes charge/discharge circuit 2121 and charge/discharge circuit 2122.Charge/discharge circuit 2121 is in order to receive the first rectification pulse signal and to perform a charge/discharge operation (operating also referred to as the first charge/discharge) to produce sensing voltage SV1 according to the first rectification pulse signal.Charge/discharge circuit 2122 is in order to receive the second rectification pulse signal and to perform another charge/discharge operation (operating also referred to as the second charge/discharge) to produce sensing voltage SV2 according to the second rectification pulse signal.
Comparison circuit 221 is electrically connected to charge/discharge circuit 2121 and charge/discharge circuit 2122.The magnitude of voltage of sensing voltage SV1 is sampled with the magnitude of voltage of sensing voltage SV2 at above-mentioned particular point in time by comparison circuit 221 in order to receive the sensing voltage seasonal pulse CLK to (that is, sensing voltage SV1 and SV2) and according to differential wave RXDP and RXDN.Then, comparison circuit 221 can compare the magnitude of voltage of the sensing voltage SV1 sampled with the magnitude of voltage sensing voltage SV2 sampled to obtain the voltage relativeness of sensing voltage pair.If the magnitude of voltage that the magnitude of voltage that this voltage relativeness is sensing voltage SV1 is more than sensing voltage SV2, comparison circuit 221 can determine and export the first sampled data.If the magnitude of voltage that the magnitude of voltage that this voltage relativeness is sensing voltage SV1 is less than sensing voltage SV2, then comparison circuit 221 can determine and export the second sampled data.Comparison circuit 221 can include one or more D-type flip-flop (D-typeflip-flop) and can export sampled data crossfire SDS according to the seasonal pulse CLK of differential wave RXDP and RXDN and the sampled data determined.
In this exemplary embodiment, sensing circuit 21 also includes reset circuit 213.Reset circuit 213 is electrically connected to sense amplifying circuits 211 and voltage-current converter circuit 212.Reset circuit 213 is in order to reset sensing voltage pair according to the seasonal pulse of differential wave RXDP and RXDN.Such as, after comparison circuit 221 each time obtains the magnitude of voltage of sensing voltage SV1 and the magnitude of voltage of sensing voltage SV2, reset circuit 213 can send a reset signal RS to charge/discharge circuit 2121 and charge/discharge circuit 2122；The magnitude of voltage of sensing voltage SV1 can be adjusted to a preset value with the magnitude of voltage of SV2 according to this reset signal RS respectively by charge/discharge circuit 2121 with charge/discharge circuit 2122.Thereafter, from then on charge/discharge circuit 2121 can start to perform above-mentioned first charge/discharge operation respectively with above-mentioned second charge/discharge operation with the magnitude of voltage adjusting sensing voltage SV1 and SV2 that continues by preset value with charge/discharge circuit 2122.But, in another exemplary embodiment, sensing circuit 21 can not also comprise reset circuit 213, and the present invention is not any limitation as.
Fig. 3 is the schematic diagram of the charge/discharge circuit shown by one example of the present invention embodiment.
Refer to Fig. 3, charge/discharge circuit 3121 and charge/discharge circuit 3122 are same or similar in charge/discharge circuit 2121 and charge/discharge circuit 2122 respectively.
Charge/discharge circuit 3121 includes capacitor cell 331, charging current source 341, charge switch 351, discharge current source 342 and discharge switch 352.
Capacitor cell 331 includes one or more electric capacity etc. and may be used to store the electronic component of electric charge.First end of capacitor cell 331 is electrically connected to sample circuit 22 and the second end ground connection of capacitor cell 331.Namely above-mentioned sensing voltage SV1 refers to the electric potential difference between two end points of capacitor cell 331.Charging current source 341 is in order to provide a charging current to the first end of capacitor cell 331.Charge switch 351 is serially connected with on the charge path (also referred to as the first charge path) between the first end of capacitor cell 331 and charging current source 341 and in order to react on the first rectification pulse signal and on and off the first charge path.Discharge current source 342 is in order to provide a discharge current to earth terminal.Discharge switch 352 is serially connected with on the discharge path (also referred to as the first discharge path) between the first end of capacitor cell 331 and discharge current source 342 and closes or turn on the first discharge path in order to react on the first rectification pulse signal.In this exemplary embodiment, if the first voltage correcting pulse signal is in logic high, then charge switch 351 can turn on the first charge path, and discharge switch 352 can cut off the first discharge path, and capacitor cell 331 can be charged (as shown in Figure 3) by charging current source 341；If the first voltage correcting pulse signal is in logic low, then charge switch 351 can cut off the first charge path, and discharge switch 352 can turn on the first discharge path, and capacitor cell 331 can be discharged by discharge current source 342.
Charge/discharge circuit 3122 includes capacitor cell 332, charging current source 343, charge switch 353, discharge current source 344 and discharge switch 354.
Capacitor cell 332 includes one or more electric capacity etc. and may be used to store the electronic component of electric charge.First end of capacitor cell 332 is electrically connected to sample circuit 22 and the second end ground connection of capacitor cell 332.Namely above-mentioned sensing voltage SV2 refers to the electric potential difference between two end points of capacitor cell 332.Charging current source 343 is in order to provide a charging current to the first end of capacitor cell 332.Charge switch 353 is serially connected with on the charge path (also referred to as the second charge path) between the first end of capacitor cell 332 and charging current source 343 and in order to react on the second rectification pulse signal and on and off the second charge path.Discharge current source 344 is in order to provide a discharge current to earth terminal.Discharge switch 354 is serially connected with on the discharge path (also referred to as the second discharge path) between the first end of capacitor cell 332 and discharge current source 344 and closes or turn on the second discharge path in order to react on the second rectification pulse signal.In this exemplary embodiment, if the second voltage correcting pulse signal is in logic high, then charge switch 353 can turn on the second charge path, and discharge switch 354 can cut off the second discharge path, and capacitor cell 332 can be charged by charging current source 343；If the second voltage correcting pulse signal is in logic low, then charge switch 353 can cut off the second charge path, and discharge switch 354 can turn on the second discharge path, and capacitor cell 332 can be discharged (as shown in Figure 3) by discharge current source 344.
In other words, first corrects pulse signal and second corrects the opposite in phase of pulse signal, therefore when the first charge path and the second discharge path are switched on, the first discharge path and the second charge path can be cut off (as shown in Figure 3)；When the first discharge path and the second charge path are switched on, the first charge path and the second discharge path can be cut off.
Fig. 4 is the schematic diagram of the signal waveform shown by one example of the present invention embodiment.
Refer to Fig. 4, at this, differential wave RXDP and RXDN represents with solid line and dotted line respectively.Differential wave RXDP and RXDN uses and assumes that it is in order to sequentially transmitted bit data " 1 ", " 0 ", " 1 ", " 0 ", " 0 ", " 1 " and " 1 " together.
At time point T1, react on the first rectification pulse signal (or, differential wave RXDP) it is in logic low, the first charge path can be cut off, and the first discharge path can be switched on and capacitor cell 331 can be discharged by discharge current source 342 by the first discharge path；Simultaneously, react on the second rectification pulse signal (or, differential wave RXDN) it is in logic high, the second charge path can be switched on, the second discharge path can be cut off and charging current source 343 begins through the second charge path and capacitor cell 332 is charged.
At time point T2, react on the first rectification pulse signal (or, differential wave RXDP) it is in logic high, the first charge path is switched on, the first discharge path is closed and charging current source 341 begins through the first charge path and capacitor cell 331 is charged；Simultaneously, react on the second rectification pulse signal (or, differential wave RXDN) it is in logic low, the second charge path is closed, the second discharge path switched on and discharge current source 344 begins through the second discharge path and capacitor cell 332 is discharged.
At time point T3 (that is, particular point in time), the seasonal pulse CLK according to differential wave RXDP and RXDN, the magnitude of voltage of sensing voltage SV1 and SV2 can be sampled and be compared with each other.At this, owing to the magnitude of voltage sensing voltage SV1 sampled is more than the magnitude of voltage sensing voltage SV2 sampled, therefore the first sampled data (that is, bit " 1 ") can be determined and be output.On the other hand, after the magnitude of voltage sensing voltage SV1 and SV2 is sampled, the magnitude of voltage of sensing voltage SV1 and SV2 is reset as preset value Vreset.Then, react on the first rectification pulse signal (or, differential wave RXDP) it is in logic low, the first charge path can be cut off, and the first discharge path can be switched on and capacitor cell 331 can be discharged by discharge current source 342 by the first discharge path；Simultaneously, react on the second rectification pulse signal (or, differential wave RXDN) it is in logic high, the second charge path can be switched on, the second discharge path can be cut off and charging current source 343 begins through the second charge path and capacitor cell 332 is charged.
At time point T4, react on the first rectification pulse signal (or, differential wave RXDP) it is in logic high, the first charge path is switched on, the first discharge path is closed and charging current source 341 begins through the first charge path and capacitor cell 331 is charged；Simultaneously, react on the second rectification pulse signal (or, differential wave RXDN) it is in logic low, the second charge path is closed, the second discharge path switched on and discharge current source 344 begins through the second discharge path and capacitor cell 332 is discharged.
At time point T5 (that is, particular point in time), the seasonal pulse CLK according to differential wave RXDP and RXDN, the magnitude of voltage of sensing voltage SV1 and SV2 can be sampled and be compared with each other.At this, owing to the magnitude of voltage sensing voltage SV1 sampled is less than the magnitude of voltage sensing voltage SV2 sampled, therefore the second sampled data (that is, bit " 0 ") can be determined and be output.On the other hand, after the magnitude of voltage sensing voltage SV1 and SV2 is sampled, the magnitude of voltage of sensing voltage SV1 and SV2 is reset as preset value Vreset again.Then, react on the first rectification pulse signal (or, differential wave RXDP) it is in logic low, the first charge path can be cut off, and the first discharge path can be switched on and capacitor cell 331 can be discharged by discharge current source 342 by the first discharge path；Simultaneously, react on the second rectification pulse signal (or, differential wave RXDN) it is in logic high, the second charge path can be switched on, the second discharge path can be cut off and charging current source 343 begins through the second charge path and capacitor cell 332 is charged.The follow-up operation in order to export Bit data " 1 ", " 0 ", " 0 ", " 1 " and " 1 " is referred to Fig. 4 and aforesaid operations is analogized, and does not just repeat to repeat at this.
Should be noted, circuit shown in Fig. 2 and Fig. 3 is only an exemplary embodiment of the present invention, in another exemplary embodiment, any useful electronic component can additionally be added to the circuit shown in Fig. 2 and Fig. 3, or, the electronic component of part can also be removed from the circuit shown in Fig. 2 or Fig. 3, and the present invention is not any limitation as.
Fig. 5 is the schematic diagram of the charge/discharge circuit shown by another example of the present invention embodiment.
Refer to the difference of the exemplary embodiment of Fig. 5, this exemplary embodiment and Fig. 3 to be in that, in the charge/discharge circuit of this exemplary embodiment, above-mentioned first discharge path and the second discharge path are all absent from.In other words, in this exemplary embodiment, charge/discharge circuit 5121 includes capacitor cell 331, charging current source 341 and charge switch 351, and charge/discharge circuit 5122 includes capacitor cell 332, charging current source 343 and charge switch 353.Capacitor cell 331, charging current source 341, charge switch 351, capacitor cell 332, charging current source 343 and charge switch 353 had done explanation all in the exemplary embodiment of Fig. 3, therefore did not just repeat at this.The charge/discharge circuit 2121 and 2122 of Fig. 2 can select the embodiment adopting the exemplary embodiment of Fig. 3 or Fig. 5 to implement, and the present invention is not any limitation as.Additionally, any useful electronic component can additionally be added to the circuit shown in Fig. 5, the present invention is not any limitation as.
Fig. 6 is the flow chart of the method for data samples shown by one example of the present invention embodiment.
Refer to Fig. 6, in step s 601, receive differential wave and produce sensing voltage pair according to described differential wave, wherein said sensing voltage is to including the first sensing voltage and the second sensing voltage, first magnitude of voltage of described first sensing voltage is relevant with the first differential wave in described differential wave, and the second magnitude of voltage of described second sensing voltage is relevant with the second differential wave in described differential wave.In step S602, receive described sensing voltage to and export sampled data crossfire according to the seasonal pulse of described differential wave and the voltage relativeness of described sensing voltage pair.
But, in Fig. 6, each step has described in detail as above, just repeats no more at this.It should be noted that in Fig. 6, each step can implementation be multiple procedure code or circuit, the present invention is not any limitation as.Additionally, the method for Fig. 6 can be arranged in pairs or groups, example above embodiment uses, it is also possible to being used alone, the present invention is not any limitation as.
In this exemplary embodiment, data-sampling circuit module set forth above and method of data samples be for memorizer memory devices (also referred to as, memory storage system) in, or it is used in the memorizer control circuit unit in order to control this memorizer memory devices.But, in another exemplary embodiment, data-sampling circuit module set forth above and method of data samples can also be that the present invention is not any limitation as various electronic installations or communicators such as smart mobile phone, panel computer, notebook computers.
In general, memorizer memory devices includes rewritable non-volatile memory module and controller (also referred to as, control circuit).Being commonly stored device storage device is use together with host computer system, so that host computer system can write data into memorizer memory devices or read data from memorizer memory devices.
Fig. 7 is the schematic diagram of the host computer system shown by one example of the present invention embodiment and memorizer memory devices.Fig. 8 is the schematic diagram of the computer system shown by one example of the present invention embodiment and input/output device.Fig. 9 is the schematic diagram of the host computer system shown by one example of the present invention embodiment and memorizer memory devices.
Refer to Fig. 7, host computer system 1000 generally comprises computer 1100, and (input/output is called for short: I/O) device 1106 with input/output.RAM) 1104, system bus 1108 and data transmission interface 1110 computer 1100 includes microprocessor 1102, (randomaccessmemory, is called for short random access memory:.Input/output device 1106 includes such as the mouse 1202 of Fig. 8, keyboard 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device 1106 of device shown in Fig. 8, input/output device 1106 can also include other devices.
Memorizer memory devices 100 is to be electrically connected by other elements of data transmission interface 1110 with host computer system 1000.Can be write data into memorizer memory devices 100 by the running of microprocessor 1102, random access memory 1104 and input/output device 1106 or from memorizer memory devices 100, read data.Such as, memorizer memory devices 100 can be that (SolidStateDrive is called for short: SSD) the rewritable non-volatile memory storage device of 1216 grades for USB flash drive 1212 as shown in Figure 8, storage card 1214 or solid state hard disc.
It is said that in general, host computer system 1000 is any system that can coordinate to store data substantially with memorizer memory devices 100.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, but, in another exemplary embodiment of the present invention, host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player.Such as, when host computer system is digital camera (video camera) 1310, rewritable non-volatile memory storage device is then for its SD card 1312 used, mmc card 1314, memory stick (memorystick) 1316, CF card 1318 or embedded storage device 1320 (as shown in Figure 9).Embedded storage device 1320 includes embedded multi-media card, and (EmbeddedMMC is called for short: eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host computer system.
Figure 10 is the schematic block diagram illustrating the memorizer memory devices shown in Fig. 7.
Refer to Figure 10, memorizer memory devices 100 includes connecting interface unit 1002, memorizer control circuit unit 1004 and rewritable non-volatile memory module 1006.
In this exemplary embodiment, connecting interface unit 1002 is be compatible to sequence advanced person's adnexa (SerialAdvancedTechnologyAttachment, abbreviation: SATA) standard.nullBut，It must be appreciated，The invention is not restricted to this，Connect interface unit 1002 and can also be consistent with advanced adnexa (ParallelAdvancedTechnologyAttachment side by side，It is called for short: PATA) standard、Institute of Electrical and Electric Engineers (InstituteofElectricalandElectronicEngineers，It is called for short: IEEE) 1394 standards、High-speed peripheral component connecting interface (PeripheralComponentInterconnectExpress，It is called for short: PCIExpress) standard、Universal serial bus (UniversalSerialBus，It is called for short: USB) standard、A ultrahigh speed generation (UltraHighSpeed-I，It is called for short: UHS-I) interface standard、Secondary (the UltraHighSpeed-II of ultrahigh speed，It is called for short: UHS-II) interface standard、Safe digital (SecureDigital，It is called for short: SD) interface standard、Memory stick (MemoryStick，It is called for short: MS) interface standard、Multi Media Card (MultiMediaCard，It is called for short: MMC) interface standard、Compact flash (CompactFlash，It is called for short: CF) interface standard、Integrated driving electrical interface (IntegratedDeviceElectronics，It is called for short: IDE) standard or other standards being suitable for.In this exemplary embodiment, connecting interface unit can be encapsulated in a chip with memorizer control circuit unit, or is laid in outside a chip comprising memorizer control circuit unit.
In an exemplary embodiment, above-mentioned data-sampling circuit module 10 or 20 is disposed on connecting in interface unit 1002, thus can receiving from differential wave RXDP and the RXDN of host computer system 1000 and exporting corresponding sampled data crossfire SDS and use for memorizer control circuit unit 1004.
Memorizer control circuit unit 1004 is in order to perform the multiple gates with hardware pattern or firmware pattern implementation or control instruction, and the instruction according to host computer system 1000 carries out the runnings such as the write of data, reading and erasing in rewritable non-volatile memory module 1006.
Rewritable non-volatile memory module 1006 is electrically connected to memorizer control circuit unit 1004, and in order to store the data that host computer system 1000 writes.Rewritable non-volatile memory module 1006 includes entity erasing unit 304 (0)～304 (R).Entity erasing unit 304 (0)～304 (R) can belong to same memory crystal grain (die) or belong to different memory crystal grain.Each entity erasing unit is respectively provided with a plurality of entity programming unit, and the entity programming unit wherein belonging to same entity erasing unit can be written independently and simultaneously be wiped.In this exemplary embodiment, each entity erasing unit is made up of 64 entity programming units.But, in other exemplary embodiment of the present invention, each entity erasing unit is made up of 128,256 entity programming units or other arbitrarily individual entity programming units.
In more detail, entity programming unit is the minimum unit of programming.That is, entity programming unit is the minimum unit of write data.Such as, entity programming unit is physical page or entity fan (sector).If entity programming unit is physical page, then each entity programming unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises multiple entity fan, and in order to store the data of user, and redundancy ratio special zone is in order to the data (such as, error correcting code) of stocking system.In this exemplary embodiment, each data bit district comprises 32 entities fan, and an entity fan be sized to 512 bit groups (byte, B).But, in other exemplary embodiment, data bit district also can comprise 8,16 or the more or less of entity fan of number, the present invention is not limiting as size and the number of entity fan.On the other hand, entity erasing unit is the least unit of erasing.That is, each entity erasing unit contains the memory element being wiped free of in the lump of minimal amount.Such as, entity erasing unit is physical blocks.
In this exemplary embodiment, rewritable non-volatile memory module 1006 is multi-level cell memory (MultiLevelCell, it is called for short: MLC) NAND type flash memory module (that is, the flash memory module of 2 Bit datas can be stored in a memory element).But, the invention is not restricted to this, rewritable non-volatile memory module 1006 may also be single-order memory element (SingleLevelCell, it is called for short: SLC) NAND type flash memory module is (namely, one memory element can store the flash memory module of 1 Bit data), Complex Order memory element (TrinaryLevelCell, it is called for short: TLC) NAND type flash memory module is (namely, one memory element can store the flash memory module of 3 Bit datas), other flash memory module or other there is the memory module of identical characteristics.
Figure 11 is the schematic block diagram of the memorizer control circuit unit shown by one example of the present invention embodiment.
Refer to Figure 11, memorizer control circuit unit 1004 includes memory management circuitry 202, HPI 204, memory interface 206.
Memory management circuitry 202 is in order to control the overall operation of memorizer control circuit unit 1004.Specifically, memory management circuitry 202 has multiple control instruction, and when memorizer memory devices 100 operates, these a little control instructions can be performed to carry out the runnings such as the write of data, reading and erasing.
In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with firmware pattern.Such as, memory management circuitry 202 has microprocessor unit (not shown) and a read only memory (not shown), and these a little control instructions are to be programmed so far in the read only memory.When memorizer memory devices 100 operates, these a little control instructions can be performed to carry out the runnings such as the write of data, reading and erasing by microprocessor unit.
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also procedure code pattern be stored in the specific region (such as, being exclusively used in the system area of storage system data in memory module) of rewritable non-volatile memory module 1006.Additionally, memory management circuitry 202 has microprocessor unit (not shown), read only memory (not shown) and random access memory (not shown).Particularly, this read only memory has driving code, and when memorizer control circuit unit 1004 is enabled, microprocessor unit can first carry out this and drive code section the control instruction being stored in rewritable non-volatile memory module 1006 to be loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor unit can operate these a little control instructions to carry out the runnings such as the write of data, reading and erasing.
Additionally, in another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 a hardware pattern can also carry out implementation.Such as, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memorizer write circuit, memory reading circuitry, memorizer erasing circuit and data processing circuit.Storage Unit Management circuit, memorizer write circuit, memory reading circuitry, memorizer erasing circuit and data processing circuit are electrically connected to microcontroller.Wherein, Storage Unit Management circuit wipes unit in order to the entity managing rewritable non-volatile memory module 1006；Memorizer write circuit in order to assign write instruction to write data into rewritable non-volatile memory module 1006 to rewritable non-volatile memory module 1006；Memory reading circuitry in order to assign reading instruction to read data from rewritable non-volatile memory module 1006 to rewritable non-volatile memory module 1006；Memorizer erasing circuit in order to assign erasing instruction data to be wiped from rewritable non-volatile memory module 1006 to rewritable non-volatile memory module 1006；And data processing circuit in order to process be intended to write to the data of rewritable non-volatile memory module 1006 and from rewritable non-volatile memory module 1006 read data.
HPI 204 is electrically connected to memory management circuitry 202 and instruction and data in order to receive with identify that host computer system 1000 transmits.It is to say, the instruction that host computer system 1000 transmits can be sent to memory management circuitry 202 by HPI 204 with data.In this exemplary embodiment, HPI 204 is to be compatible to SATA standard.But, it must be appreciated and the invention is not restricted to this, HPI 204 can also be compatible to PATA standard, IEEE1394 standard, PCIExpress standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other data transmission standards being suitable for.
Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access rewritable non-volatile memory module 1006.It is to say, the data being intended to write to rewritable non-volatile memory module 1006 can be converted to the receptible form of rewritable non-volatile memory module 1006 via memory interface 206.Specifically, if memory management circuitry 1102 to access rewritable non-volatile memory module 406, memory interface 1106 can transmit the job sequence of correspondence.These job sequences can include one or more signal or the data in bus.Such as, in reading job sequence, the information such as the identification code of reading, memorizer address can be included.
In an exemplary embodiment, memorizer control circuit unit 1004 also includes buffer storage 252, electric power management circuit 254 and error checking and correcting circuit 256.
Buffer storage 252 is electrically connected to memory management circuitry 202 and is configured to temporarily store the data and instruction or the data coming from rewritable non-volatile memory module 1006 that come from host computer system 1000.
Electric power management circuit 254 is electrically connected to memory management circuitry 202 and in order to control the power supply of memorizer memory devices 100.
Error checking and correcting circuit 256 are electrically connected to memory management circuitry 202 and in order to perform error checking with correction program to guarantee the correctness of data.Specifically, when memory management circuitry 202 receives write instruction from host computer system 1000, error checking produces corresponding error checking and correcting code (ErrorCheckingandCorrectingCode with the data that correcting circuit 256 can be this write instruction corresponding, it is called for short: ECCCode), and the data of this write instruction corresponding can be write to rewritable non-volatile memory module 1006 with correcting code with corresponding error checking by memory management circuitry 202.Afterwards, error checking corresponding to these data and correcting code can be read when memory management circuitry 202 reads data from rewritable non-volatile memory module 1006 simultaneously, and error checking and correcting circuit 256 can perform error checking and correction program according to this error checking with the correcting code data to reading.
It is worth mentioning that, in an exemplary embodiment, if memorizer control circuit unit 1004 or memorizer memory devices 100 are in the non-normal working patterns such as dormancy, standby or low power consumption, host computer system 1000 can send a wake-up signal to memorizer memory devices 100.This wake-up signal is in order to memorizer control circuit unit 1004 or memorizer memory devices 100 to be waken up from the non-normal working patterns such as dormancy, standby or low power consumption.By above-mentioned data-sampling circuit module 10, memory management circuitry 202 can correctly identify out from whether the signal of host computer system 1000 is wake-up signal.If memory management circuitry 202 judges current from the signal of host computer system 1000 it is wake-up signal, then memorizer control circuit unit 1004 or memorizer memory devices 100 can be switched to normal mode of operation by memory management circuitry 202.
In an exemplary embodiment, reacting on memorizer control circuit unit 1004 or the mode of operation of memorizer memory devices 100, data-sampling circuit module 10 meeting voluntarily or is decided whether to start by memorizer control circuit unit 1004.Such as, when memorizer control circuit unit 1004 or memorizer memory devices 100 are in the non-normal working patterns such as dormancy, standby or low power consumption, data-sampling circuit module 10 can be activated；And when memorizer control circuit unit 1004 or memorizer memory devices 100 are in normal mode of operation, data-sampling circuit module 10 will not be activated.But, in another exemplary embodiment, data-sampling circuit module 10 is then to be activated all the time.Such as, reacting on memorizer memory devices 100 and power on or start shooting, data-sampling circuit module 10 will be activated, until memorizer memory devices 100 is de-energized or shuts down.
In sum, after receiving differential wave, the present invention can perform charge/discharge according to this differential wave and operate to produce the sensing voltage pair being correlated with.Then, the magnitude of voltage of sensing voltage pair can be sampled by the present invention according to the seasonal pulse of this differential wave, and exports sampled data crossfire according to the voltage relativeness sensing voltage pair further.Therefore, the efficiency differential wave received processed can effectively promote.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；Although the present invention being described in detail with reference to foregoing embodiments, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein some or all of technical characteristic is carried out equivalent replacement；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (33)
1. a data-sampling circuit module, it is characterised in that including:
One sensing circuit, in order to receive a differential wave and to produce a sensing voltage pair according to this differential wave, wherein this sensing voltage is to including one first sensing voltage and one second sensing voltage, one first magnitude of voltage of this first sensing voltage is relevant with one first differential wave in this differential wave, and one second magnitude of voltage of this second sensing voltage is relevant with one second differential wave in this differential wave；And
One sample circuit, is electrically connected to this sensing circuit, wherein this sample circuit in order to receive this sensing voltage to and export a sampled data crossfire according to a seasonal pulse of this differential wave and a voltage relativeness of this sensing voltage pair.
2. data-sampling circuit module according to claim 1, it is characterised in that this sensing circuit includes:
One sense amplifying circuits, in order to receive this differential wave and this differential wave to perform a sensing amplification to export a rectification pulse signal；And
One voltage-current converter circuit, is electrically connected to this sense amplifying circuits, and wherein this voltage-current converter circuit is in order to receive this rectification pulse signal and to perform a charge/discharge operation to produce this sensing voltage pair according to this rectification pulse signal.
3. data-sampling circuit module according to claim 2, it is characterised in that this voltage-current converter circuit includes:
One first charge/discharge circuit, corrects pulse signal in order to receive in this rectification pulse signal one first and performs one first charge/discharge operation to produce this first sensing voltage according to this first rectification pulse signal；And
One second charge/discharge circuit, corrects pulse signal in order to receive in this rectification pulse signal one second and performs one second charge/discharge operation to produce this second sensing voltage according to this second rectification pulse signal.
4. data-sampling circuit module according to claim 3, it is characterised in that this first charge/discharge circuit includes:
One first capacitor cell, wherein this first sensing voltage refers to one first electric potential difference of this first capacitor cell；
One first charging current source；
One first charge switch, is serially connected with one first charge path between this first capacitor cell and this first charging current source and first corrects pulse signal and this first charge path of on and off in order to react on this.
5. data-sampling circuit module according to claim 4, it is characterised in that this first charge/discharge circuit also includes:
One first discharge current source；And
One first discharge switch, is serially connected with one first discharge path between this first capacitor cell and this first discharge current source and closes or turn on this first discharge path in order to react on this first rectification pulse signal.
6. data-sampling circuit module according to claim 3, it is characterised in that this second charge/discharge circuit includes:
One second capacitor cell, wherein this second sensing voltage refers to one second electric potential difference of this second capacitor cell；
One second charging current source；
One second charge switch, is serially connected with one second charge path between this second capacitor cell and this second charging current source and second corrects pulse signal and this second charge path of on and off in order to react on this.
7. data-sampling circuit module according to claim 6, it is characterised in that this second charge/discharge circuit also includes:
One second discharge current source；And
One second discharge switch, is serially connected with one second discharge path between this second capacitor cell and this second discharge current source and closes or turn on this second discharge path in order to react on this second rectification pulse signal.
8. data-sampling circuit module according to claim 1, it is characterised in that this sample circuit includes:
One comparison circuit, in order to receive this sensing voltage to and compare this first magnitude of voltage with this second magnitude of voltage to obtain this voltage relativeness according to this seasonal pulse of this differential wave,
If wherein this voltage relativeness is this first magnitude of voltage more than this second magnitude of voltage, this comparison circuit output one first sampled data,
If wherein this voltage relativeness is that this first magnitude of voltage is less than this second magnitude of voltage, this comparison circuit output one second sampled data.
9. data-sampling circuit module according to claim 2, it is characterised in that this sensing circuit also includes:
One reset circuit, is electrically connected to this sense amplifying circuits and this voltage-current converter circuit and in order to reset this sensing voltage pair according to this seasonal pulse of this differential wave.
10. data-sampling circuit module according to claim 1, it is characterised in that this differential wave is to utilize pulse width modulating signal produced by a pulse width modulation (PWM) technology.
11. data-sampling circuit module according to claim 1, it is characterised in that this data-sampling circuit module is configured in a memorizer memory devices,
Wherein when a memorizer control circuit unit of this memorizer memory devices or this memorizer memory devices is in a non-normal working pattern, this data-sampling circuit module is activated,
Wherein when this memorizer memory devices or this memorizer control circuit unit are in a normal mode of operation, this data-sampling circuit module is not activated by.
12. a method of data samples, it is characterised in that including:
Receive a differential wave and produce a sensing voltage pair according to this differential wave, wherein this sensing voltage is to including one first sensing voltage and one second sensing voltage, one first magnitude of voltage of this first sensing voltage is relevant with one first differential wave in this differential wave, and one second magnitude of voltage of this second sensing voltage is relevant with one second differential wave in this differential wave；And
Receive this sensing voltage to and export a sampled data crossfire according to a seasonal pulse of this differential wave and a voltage relativeness of this sensing voltage pair.
13. method of data samples according to claim 12, it is characterised in that receive this differential wave and produce the step of this sensing voltage pair according to this differential wave and include:
Receive this differential wave and this differential wave performed a sensing amplification to export a rectification pulse signal；And
Receive this rectification pulse signal and perform a charge/discharge operation to produce this sensing voltage pair according to this rectification pulse signal.
14. method of data samples according to claim 13, it is characterised in that receive this rectification pulse signal and according to this rectification pulse signal perform this charge/discharge operation step include:
Receive in this rectification pulse signal one first correct pulse signal and perform one first charge/discharge operation to produce this first sensing voltage according to this first rectification pulse signal；And
Receive in this rectification pulse signal one second correct pulse signal and perform one second charge/discharge operation to produce this second sensing voltage according to this second rectification pulse signal.
15. method of data samples according to claim 14, it is characterised in that this first sensing voltage refers to one first electric potential difference of one first capacitor cell, and the step performing this first charge/discharge operation according to this first rectification pulse signal includes:
React on this and first correct pulse signal and one first charge path between this first capacitor cell of on and off and one first charging current source.
16. method of data samples according to claim 15, it is characterised in that also include according to the step that this first rectification pulse signal performs this first charge/discharge operation:
React on this first one first discharge path corrected pulse signal and close or turn between this first capacitor cell and one first discharge current source.
17. method of data samples according to claim 14, it is characterised in that this second sensing voltage refers to one second electric potential difference of one second capacitor cell, and the step performing this second charge/discharge operation according to this second rectification pulse signal includes:
React on this and second correct pulse signal and one second charge path between this second capacitor cell of on and off and one second charging current source.
18. method of data samples according to claim 17, it is characterised in that also include according to the step that this second rectification pulse signal performs this second charge/discharge operation:
React on this second one second discharge path corrected pulse signal and close or turn between this second capacitor cell and one second discharge current source.
19. method of data samples according to claim 12, it is characterised in that include according to the step that this voltage relativeness of this seasonal pulse of this differential wave Yu this sensing voltage pair exports this sampled data crossfire:
Receive this sensing voltage to and compare this first magnitude of voltage with this second magnitude of voltage to obtain this voltage relativeness according to this seasonal pulse of this differential wave；
If this voltage relativeness is that this first magnitude of voltage is more than this second magnitude of voltage, output one first sampled data；And
If this voltage relativeness is that this first magnitude of voltage is less than this second magnitude of voltage, output one second sampled data.
20. method of data samples according to claim 13, it is characterised in that the step producing this sensing voltage pair according to this differential wave also includes:
This seasonal pulse according to this differential wave resets this sensing voltage pair.
21. method of data samples according to claim 12, it is characterised in that this differential wave is to utilize pulse width modulating signal produced by a pulse width modulating technology.
22. method of data samples according to claim 12, it is characterised in that this method of data samples is used for a memorizer memory devices,
Wherein when a memorizer control circuit unit of this memorizer memory devices or this memorizer memory devices is in a non-normal working pattern, perform this method of data samples,
Wherein when this memorizer memory devices or this memorizer control circuit unit are in a normal mode of operation, do not perform this method of data samples.
23. a memorizer memory devices, it is characterised in that including:
One connects interface unit, is electrically connected to a host computer system；
One rewritable non-volatile memory module, wipes unit including multiple entities；And
One memorizer control circuit unit, is electrically connected to this connection interface unit and this rewritable non-volatile memory module,
Wherein this connection interface unit includes a data-sampling circuit module, and this data-sampling circuit module includes:
One sensing circuit, in order to receive a differential wave and to produce a sensing voltage pair according to this differential wave, wherein this sensing voltage is to including one first sensing voltage and one second sensing voltage, one first magnitude of voltage of this first sensing voltage is relevant with one first differential wave in this differential wave, and one second magnitude of voltage of this second sensing voltage is relevant with one second differential wave in this differential wave；And
One sample circuit, is electrically connected to this sensing circuit, wherein this sample circuit in order to receive this sensing voltage to and export a sampled data crossfire according to a seasonal pulse of this differential wave and a voltage relativeness of this sensing voltage pair.
24. memorizer memory devices according to claim 23, it is characterised in that this sensing circuit includes:
One sense amplifying circuits, in order to receive this differential wave and this differential wave to perform a sensing amplification to export a rectification pulse signal；And
One voltage-current converter circuit, is electrically connected to this sense amplifying circuits, and wherein this voltage-current converter circuit is in order to receive this rectification pulse signal and to perform a charge/discharge operation to produce this sensing voltage pair according to this rectification pulse signal.
25. memorizer memory devices according to claim 24, it is characterised in that this voltage-current converter circuit includes:
One first charge/discharge circuit, corrects pulse signal in order to receive in this rectification pulse signal one first and performs one first charge/discharge operation to produce this first sensing voltage according to this first rectification pulse signal；And
One second charge/discharge circuit, corrects pulse signal in order to receive in this rectification pulse signal one second and performs one second charge/discharge operation to produce this second sensing voltage according to this second rectification pulse signal.
26. memorizer memory devices according to claim 25, it is characterised in that this first charge/discharge circuit includes:
One first capacitor cell, wherein this first sensing voltage refers to one first electric potential difference of this first capacitor cell；
One first charging current source；
One first charge switch, is serially connected with one first charge path between this first capacitor cell and this first charging current source and first corrects pulse signal and this first charge path of on and off in order to react on this.
27. memorizer memory devices according to claim 26, it is characterised in that this first charge/discharge circuit also includes:
One first discharge current source；And
One first discharge switch, is serially connected with one first discharge path between this first capacitor cell and this first discharge current source and closes or turn on this first discharge path in order to react on this first rectification pulse signal.
28. memorizer memory devices according to claim 25, it is characterised in that this second charge/discharge circuit includes:
One second capacitor cell, wherein this second sensing voltage refers to one second electric potential difference of this second capacitor cell；
One second charging current source；
One second charge switch, is serially connected with one second charge path between this second capacitor cell and this second charging current source and second corrects pulse signal and this second charge path of on and off in order to react on this.
29. memorizer memory devices according to claim 28, it is characterised in that this second charge/discharge circuit also includes:
One second discharge current source；And
One second discharge switch, is serially connected with one second discharge path between this second capacitor cell and this second discharge current source and closes or turn on this second discharge path in order to react on this second rectification pulse signal.
30. memorizer memory devices according to claim 23, it is characterised in that this sample circuit includes:
One comparison circuit, in order to receive this sensing voltage to and compare this first magnitude of voltage with this second magnitude of voltage to obtain this voltage relativeness according to this seasonal pulse of this differential wave,
If wherein this voltage relativeness is this first magnitude of voltage more than this second magnitude of voltage, this comparison circuit output one first sampled data,
If wherein this voltage relativeness is that this first magnitude of voltage is less than this second magnitude of voltage, this comparison circuit output one second sampled data.
31. memorizer memory devices according to claim 24, it is characterised in that this sensing circuit also includes:
One reset circuit, is electrically connected to this sense amplifying circuits and this voltage-current converter circuit and in order to reset this sensing voltage pair according to this seasonal pulse of this differential wave.
32. memorizer memory devices according to claim 24, it is characterised in that this differential wave is to utilize pulse width modulating signal produced by a pulse width modulating technology.
33. memorizer memory devices according to claim 24, it is characterised in that when this memorizer memory devices or this memorizer control circuit unit are in a non-normal working pattern, this data-sampling circuit module is activated,
Wherein when this memorizer memory devices or this memorizer control circuit unit are in a normal mode of operation, this data-sampling circuit module is not activated by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410849276.7A CN105810245B (en) | 2014-12-31 | 2014-12-31 | Data-sampling circuit module, method of data samples and memorizer memory devices |
Applications Claiming Priority (1)
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